Abstract: Multiprocessor decoding is accomplished in a first mode by generating with a series of n processors, from a set of data macroblocks, the entropy decoding output of each data macroblock and storing the entropy decoding output of each data macroblock in n storage elements, respectively, associated with the processors and in the second mode decoding the macroblock data from its associated storage element in response to the macroblock entropy decoding output from its associated storage element stored in an nth previous period, predetermined data from one or more adjacent macroblocks, and data produced from a previous processor in the series.

Abstract: Apparatus and methods are disclosed, such as those involving an electronic device. One such apparatus includes a transmitter; a receiver; and a transmit/receive switch configured to electrically block the receiver from the transmitter during a transmit period. The transmit/receive switch includes one or more MOSFETs coupled between an input node and an output node, the input node being electrically coupled to the transmitter, the output node being electrically coupled to the receiver. The one or more MOSFETs are configured to be off during the transmit period. The transmit/receive switch further includes a clamp circuit configured to couple the output node to ground during the transmit period. This configuration effectively protects the receiver while minimizing switching artifacts.

Abstract: A current mirror circuit provided in an emitter follower configuration achieves linear output currents over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.

Abstract: A method of forming a surface micromachined MEMS device applies an insulator to a substrate, and then deposits a conductive path on the insulator. The conductive path is capable of transmitting an electronic signal between two points on the MEMS device. The insulator electrically isolates the conductive path from the substrate. The MEMS device illustratively is free of semiconductor junctions formed by the substrate and the conductive path.

Abstract: Backside recesses in a base member host components, such as sensors or circuits, to allow closer proximity and efficient use of the surface space and internal volume of the base member. Recesses may include covers, caps, filters and lenses, and may be in communication with circuits on the frontside of the base member, or with circuits on an active backside cap. An array of recessed components may a form complete, compact sensor system.

Abstract: A bias current generator for generating bias current is described. The generator comprises an amplifier having an inverting input, a non-inverting input and an output. A first bipolar transistor is associated with one of the inverting and non-inverting inputs of the amplifier. A load MOS device is associated with the other one of the inverting and non-inverting inputs of the amplifier. The load MOS device is driven by the amplifier to operate in the triode region with a corresponding drain-source resistance ron. The first bipolar transistor and the load MOS device are arranged such that a voltage derived from the first bipolar transistor is developed across the drain-source resistance ron of the load MOS device thereby generating a bias current.

Abstract: An apparatus and method for determining characterizing attributes of an actuator is provided. An actuator may be moved to a maximum capacitance position. At the maximum capacitance position, an initial measurement of the actuator capacitance is made. The actuator is moved a predetermined increment toward a first extreme position, and the actuator capacitance is again measured. If the capacitance changed by a threshold amount, the signal preceding the signal that caused the actuator to move is recorded as an approximate response curve end point, or the first extreme position. The actuator is again moved a predetermined increment toward a second extreme position. After each move, the capacitance is measured. If it is determined the capacitance did change by a threshold amount from the previously measured capacitance, the signal related to the previously measured capacitance is recorded as an approximate response curve end point, or the second extreme position.

Abstract: A stacked die package in which an adhesive pad separates a bottom die from a top die. The pad may be in the form of a wall of adhesive about a central hollow area. The bottom die is attached to a base with a low temperature curing adhesive or a snap cure adhesive.

Abstract: Embodiments of the present invention provide improved accuracy of displacement control by using a multi-segment transformation of an actuator's non-linear response. The present invention may set intermediate points to effectively divide the actuator response into multiple segments. Each segment may be assigned a transform function that represents the actuator's response in that particular segment. The present invention may operate in two modes, a calibration mode and a normal operations mode. During calibration mode, the intermediate points and the segment transforms may be set. During normal operations mode, a drive signal may be generated according to the calibrated set values.

Abstract: A system and method for testing capacitance of a load circuit connected to an output pin of a driving circuit In one embodiment, the method may comprise driving a voltage at the output pin to a first voltage; a predetermined current to the output pin; comparing the voltage at the output pin to a reference voltage; and when the voltage at the output pin matches the reference voltage, generating an estimate of capacitance present at the output pin based on a number of clock cycles occurring between an onset of a timed voltage change period and a time at which the voltage at the output pin matches the reference voltage.

Abstract: An improved radiation sensor device includes a cap attached to an integrated circuit chip which has a radiation sensor on a surface with a cap spaced from and covering the radiation sensor; the cap and integrated circuit chip with radiation sensor are encapsulated in an encapsulant with a transparent portion of at least one of the cap and integrated circuit chip proximate the radiation sensor being exposed at the boundary of the encapsulant.

Abstract: An auto-nulled bandgap reference system employing a substrate bandgap reference circuit with primary and auxiliary amplifiers and a switching circuit which in a first mode develops a voltage to null the offset and noise errors of the auxiliary amplifier and then in the second mode uses the nulled auxiliary amplifier to develop a voltage to null the offset and noise errors of the primary amplifier; and a strobe circuit including an output storage device and a strobe control circuit for periodically powering up a bandgap reference circuit to charge the output storage device and powering down the bandgap reference circuit to conserve power.

Abstract: An analog-to-digital conversion system includes an analog-to-digital converter (ADC), a plurality of receivers, each for capturing input analog signals, a multiplexer having inputs coupled to each of the receivers and an output coupled to the ADC, the multiplexer establishing a signal path between a selected one of the inputs and the output in response to an index signal, and a mux controller to supply a random sequence of index signals to the multiplexer.

Abstract: Error sources relating to the drive signal applied to the resonator of an inertial sensor, such as in-phase offset errors relating to the drive signal and/or electronic pass-through of the drive signal to accelerometer sense electronics, are detected by modulating the drive signal and sensing accelerometer signals that are induced by the modulated drive signal. Error sources related to aerodynamics of an inertial sensor resonator are detected by modulating the distance between the resonator and the underlying substrate and sensing accelerometer signals that are induced by such modulation. Compensating signals may be provided to substantially cancel errors caused by such error sources.

Abstract: An integrator is described that may include a level-shifting capacitor, a feedback capacitor, a pre-amplifier stage and a multi-path amplifier module. The integrator may have inputs for connected an input signal source to the level-shifting capacitor. The level-shifting capacitor is connected to an input of a pre-amplifier stage of an integration signal path and to the input. The level-shifting capacitor may level shift the voltage at the input of the circuit to a lower voltage at the input of the pre-amplifier stage. Thereby, the supply voltage to the pre-amplifier stage may be reduced as well as have limited power consumption, limited temperature rise, and reduced noise that may be attributed to any thermal effects.

Abstract: A Galois field divider engine and method inputs a 1 and a first Galois field element to a Galois field reciprocal generator to obtain an output, multiplies in the Galois field reciprocal generator the first Galois field element by the output of the Galois field reciprocal generator for predicting the modulo remainder of the square of the polynomial product of an irreducible polynomial m?2 times to obtain the reciprocal of the first Galois field element, and multiplies the reciprocal element by a second Galois field element for predicting the quotient of the two Galois field elements in m cycles; in a broader sense the invention includes a compound Galois field engine for performing a succession of Galois field linear transforms on a succession of polynomial inputs to obtain an ultimate output where each input except the first is the output of the previous Galois field linear transform.

Abstract: A circuit die to circuit die interface system includes a first circuit die with a first circuit having a first default signal, at least a second circuit die with a second circuit having a second default signal; and a logic circuit disposed on one of the first and second circuit dies and enabled by a default signal from all but one of the circuits to transmit a communication signal from the remaining circuit.

Abstract: A multi-branch frequency translation system converts a plurality of independent input clocks to a common frequency. One of the converted clock signals is selected as a dominant clock. The remaining converted clock signals are edge-synchronized with the dominant clock. When the system selects another converted clock signal for use as the dominant clock, the newly selected signal already is edge-synchronized with the dominant clock and, therefore, switchover losses can be avoided. The dominant clock can be subject of further frequency translation processes and output from the system.

Abstract: Voltage converter are provided for efficient generation of voltage signals in a load. The converters are formed with a group of inductors and at least two sets of buck and sync transistors that are arranged with the group so that conducted currents through each of the sets are directed through a respective one of the inductors and further directed to magnetically couple induced currents in the respective inductor of at least an associated one of the sets. Efficiency is particularly enhanced with an operational mode that is directed to light load conditions. In this mode and in at least a selected one of the sets, the buck transistor is turned off throughout the operational mode and the sync transistor is turned off for at least the time that an associated buck transistor is turned on in an associated set which couples induced currents in the respective inductor of the selected set.

Abstract: The invention is a novel scheme of calibrating a voltage-mode digital to analog converter using a current-mode digital to analog converter. A DAC system is comprised of a voltage-mode DAC with an R-2R architecture structure and includes a ROM lookup table where calibration codes associated with each of a plurality of input codes are stored. A reference current is scaled with the calibration codes to output a calibration current that induces adjustments in an output voltage to counteract non-linearities that may be induced by resistor mismatch.