Abstract: Disclosed embodiments are directed to an electrical overstress protection circuit. The electrical overstress protection circuit may include an intermediate node receiving a reference voltage, a first pair of clamp devices, having opposite polarity, clamping an input signal line to the intermediate node, and a second pair of clamp devices, each clamping the intermediate node to one of two reference potentials. The electrical overstress protection circuit may also include a filter connected to the intermediate node to reduce noise at the intermediate node.

Abstract: A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.

Abstract: Operational amplifier embodiments are provided to enhance amplifier parameters such as bandwidth, stability, and headroom. In an amplifier embodiment, transistor followers are arranged with first and second differential pairs to facilitate selective positioning of first and second transfer function poles to enhance bandwidth and resistors and inductors are arranged to facilitate selective positioning of complex third transfer function poles to enhance phase margin. In another amplifier embodiment, the transistor followers are arranged to reduce headroom limitations to thereby enhance the voltage swing of output signals.

Abstract: An identification system and method for recognizing a device as one of a plurality of different types of devices connected to at least one terminal of an information handling system includes supplying a test signal to a device in a test mode; measuring an electrical characteristic of the device in response to the test signal being applied to the device in the test mode; and matching a representation of the electrical characteristic of the device with representations of the electrical characteristics of the plurality of devices for recognizing the device connected to the terminal as one of the plurality of different devices.

Abstract: A sampling-rate conversion method receives N input channels which have been digitized at an input sampling rate, and converts the sampling rate of each input channel to produce N output channels at an output sampling rate. The method comprises computing a common FIR interpolating function which depends upon the input and output sample clocks and the instantaneous output time, and applying the common FIR interpolating function to all N input channels to compute all N output channels.

Abstract: Inertial sensors with reduced sensitivity to quadrature errors and micromachining inaccuracies include a gyroscope incorporating two specially-configured single-axis gyroscopes for sensing rotations about two orthogonal axes (the axes of sensitivity) in the device plane, where each single-axis gyroscope includes a resonator having two rotationally-dithered shuttles interconnected by a fork and each shuttle is configured to tilt out-of-plane along a tilt axis perpendicular to the axis of sensitivity and includes corresponding Coriolis sensing electrodes positioned along an axis perpendicular to the tilt axis (i.e., parallel to the axis of sensitivity). The two single-axis gyroscopes may be interconnected, e.g., by one or more in-phase or anti-phase couplings interconnecting the forks and/or the shuttles.

Abstract: A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock and a second input for a feedback signal, and outputting a difference signal representing a phase and/or frequency difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word.

Abstract: A microphone includes a diaphragm assembly supported by a substrate. The diaphragm assembly includes at least one carrier, a diaphragm, and at least one spring coupling the diaphragm to the at least one carrier such that the diaphragm is spaced from the at least one carrier. An insulator (or separate insulators) between the substrate and the at least one carrier electrically isolates the diaphragm and the substrate.

Abstract: Proximity detection is accomplished by determining with a moving average calculation a moving average level of input data; setting a threshold level in response to the average level and a sensitivity factor; producing a proximity detection output when the input data meets the threshold level; and changing the weighting used by the average level calculation in response to a proximity detection output.

Abstract: A digital to analog converter (DAC) includes a pair of operational amplifiers each having a first input coupled to a respective high or low reference voltage. The DAC includes a plurality of switch-controlled cells, each of which includes a resistor and two force/sense switch pairs. Within each cell, all four switches are coupled to the resistor. A first force switch is coupled to an output of a first op amp and an associated sense switch is coupled to an inverting input of the first op amp. A second force switch is coupled to an output of a second op amp and an associated sense switch is coupled to an inverting input of the second op amp. Thus, the force switches provide selectively conductive paths to permit either op amp to drive a given cell.

Abstract: A circuit can include an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, a circuit node, and a connection element connecting the n-well to the circuit node. The connection element can include a diode having an anode terminal connected to the circuit node and a cathode terminal connected to the n-well, a resistor having a first terminal connected to the circuit node and a second terminal connected to the n-well, a conductor directly connecting the n-well to the circuit node, or a well switch configured to connect the n-well to the circuit node during an enable phase of a switching signal and to electrically float the n-well during a non-enable phase of the switching signal. The diode can include a diode-connected transistor. The circuit node can be configured to receive a predetermined voltage having a magnitude equal to or greater than an upper supply voltage.

Abstract: An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.

Abstract: A bandgap voltage reference circuit which provides a bandgap reference voltage without requiring a resistor. The circuit comprises an amplifier having an inverting input, a non-inverting input and an output. First and second bipolar transistors are provided which operate at different current densities each coupled to a corresponding one of the inverting and non-inverting inputs of the amplifier. A load MOS transistor of a first aspect ratio is driven by the amplifier to operate in the triode region with a corresponding drain-source resistance ron. The load MOS device is operably coupled to the second bipolar transistor such that a base-emitter difference (?Vbe) resulting from the collector current density difference between the first and second bipolar transistors is developed across the drain-source resistance ron, of the load MOS device. A cascoded MOS device of a second aspect ratio is operably coupled to the load MOS device and is driven by the amplifier to operate in the triode region.

Abstract: An amplifier includes an amplifier section having selectable signal paths to provide discrete gain settings, and logic to incrementally select the signal paths. The logic may be configured to increment the gain in response to digital gain control signals or an analog gain control signal. Another amplifier has an input section with one or more input cells and an output section with one or more output cells. Either the input section or the output section includes at least two cells that may be selected to provide discrete gain settings. A loop amplifier is configured in a feedback arrangement with the input section. The input and output sections may have multiple selectable cells to provide coarse and fine gain steps. The gain of the loop amplifier may be coordinated with the gain of the input section to provide constant bandwidth operation.

Abstract: An electronics package has a wafer level chip scale package (WLCSP) die substrate containing electronic circuits. Through-silicon vias through the die substrate electrically connect the electronic circuits to the bottom surface of the die substrate. A package sensor is coupled to the die substrate for sensing an environmental parameter. A protective encapsulant layer covers the top surface of the die substrate. A sensor aperture over the package sensor provides access for the package sensor to the environmental parameter.

Abstract: A compute unit with an internal bit FIFO circuit includes at least one data register, a lookup table, a configuration register including FIFO base address, length and read/write mode fields for configuring a portion of the lookup table as a bit FIFO circuit and a read/write pointer register responsive to an instruction having a lookup table identification field, length of bits field and register extract/deposit field for selectively transferring in a single cycle between the FIFO circuit and the data register a bit field of specified length.

Abstract: A class G headphone amplifier circuit with improved power efficiency and low EMI. It may use an automatic signal level detector to detect the signal level of incoming signals and determine positive and negative power supplies for headphone amplifiers accordingly. A voltage generator may generate pairs of differential output voltages at a plurality of amplitude steps, and supply to headphone amplifiers the pair with the amplitude determined by the automatic signal level detector. As a result, headphone amplifiers are biased according to the input signal level, and the multiple voltage rails may improve power efficiency and avoid clipping.

Abstract: Disclosed are a method, device, and system for a microelectromechanical (MEM) device control system that can control the operation of a MEM device. The system can include a microelectromechanical device and a control circuit. The micromechanical device can include a moveable member coupled to an electrical terminal, a sensor, responsive to a movement of the moveable member, can output a sensor signal based on the movement of the moveable member, and an actuating electrode for receiving a control signal. The control circuit can be responsive to the signals output by the sensor and outputs the control signal to the actuating electrode.

Abstract: Finite impulse response filtering is achieved by broadcasting to at least one compute unit an instruction having a plurality of data samples, a conditional field associated with each compute unit, and a set of operator values for operating on each data sample; providing a function of each the data sample in accordance with an associated set of operator values identified by the conditional field; and combining the functions to obtain an intermediate finite impulse response of the data samples.

Abstract: Noise reduction for a switching amplifier system having a differential output stage and demodulator filter responsive to complementary PWM signals includes generating in-phase PWM signals and gradually adjusting their duty cycle between a low duty cycle and the full duty cycle of the complementary PWM signals, generating full duty cycle PWM signals and gradually shifting their relative phase between in-phase and out-of-phase; and in response to a turn-on signal, adjusting the in-phase PWM signals from low to full duty cycle and shifting the relative phase from in-phase to out-of-phase, and in response to a turn-off signal shifting the relative phase from out-of-phase to in-phase and adjusting the in-phase PWM signals from full to low duty cycle for maintaining balanced charge on the demodulation filter to reduce audible noise.