Abstract: Methods and apparatus for amplifying signals over a wide frequency range to generate high voltage outputs feature a pair of switching modules which are connected in series. Switching modules, e.g., field-effect transistors (FETs), operate based on the voltage difference between an amplified signal and a fixed DC signal at two of their terminals, thereby generating an output waveform that has peak-to-peak voltage higher than, e.g. twice, the breakdown voltage of the transistors within the amplifier. The DC signals applied at the switching modules may be varied using an AC signal to improve the risetime of the output waveform and achieve a faster operational speed of the amplifier.

Abstract: A system for randomizing aperture delay in a time interleaved ADC system that includes a plurality of selection switch stages corresponding to each of the ADCs in the system and a second selection switch stage coupled to a voltage source. A plurality of conductors extend between the second selection switch stage and each of the selection switch stages, in excess of the number of ADCs in the system. For each of N ADCs in the system, the selection switch stages and the second selection switch stage support at least N+1 selectable conductive paths extending from each of the sampling capacitors of the ADCs to the voltage source. Random selection of the N+1 paths can randomize aperture delay.

Abstract: A mode matching servo for an inertial sensor having a resonator and an accelerometer provides a test signal at a frequency higher than a predetermined inertial sensor response frequency and lower than an accelerometer resonance mode frequency so as to induce acceleration signals from the accelerometer substantially at the test signal frequency when the modes are not matched. A feedback signal is provided in response to such induced signals to substantially nullify the signals.

Abstract: A ?-type voltage-controlled variable attenuator is disclosed. The variable attenuator may include variably resistive components in the series and shunt arms. The variably resistive components may be implemented as field effect transistors. The shunt arms may be coupled to the series arm, and the variable attenuator may lack capacitors between the series arm and shunt arms. The series arm and shunt arms may display variable resistances which, in combination, operate to provide a variable level of attenuation of an input signal. The variable attenuator may provide any level of attenuation of an input signal over a wide frequency range. The variable attenuator may be implemented as an integrated circuit.

Abstract: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.

Abstract: A method of forming a microphone having a variable capacitance first deposits high temperature deposition material on a die. The high temperature material ultimately forms structure that contributes to the variable capacitance. The method then forms circuitry on the die after depositing the deposition material. The circuitry is configured to detect the variable capacitance.

Abstract: An SAR analog-to-digital converter performs bit decisions in each of a plurality of clock cycles. A sense circuit monitors signals input to a latch within a comparator of the ADC and, when the signals are sufficient to establish a bit decision, the sense circuit terminates a currently active clock cycle causes a bit decision to occur in advance of a normal expiration of the clock cycle. If the signals are insufficient to establish a bit decision prior to a default expiration time of the clock cycle, the clock cycle concludes at the default expiration time.

Abstract: Synchronous analog to digital conversion including providing a voltage analog to digital converter and a current analog to digital converter, synchronizing the converters, providing a signal conditioning circuit associated with the input of each converter, providing a current input to one of the signal conditioning currents and a voltage input to the other; and processing the inputs with gains differing by substantially an order of magnitude with substantially balanced time delays; and providing those conditioned inputs to the associated converters.

Abstract: The invention provides a new approach which is better suited to FFT design as applied to multicarrier modulation systems such as OFDM. The signals are scaled so that overflow, rather than being completely avoided, occurs with low probability throughout the IFFT and FFT structures. The size of the error that results from an overflow depends on how overflow is handled in the DSP. To minimize the degradation, overflow should result in saturation of the value at the maximum positive or negative value option. This is equivalent to clipping the signal. Using the new technique, signals within the FFT structure are scaled to balance the effect of clipping and round-off. Clipping may result in comparatively large errors in a few signal values but because of the spreading effect of the FFT and because OFDM systems typically include error coding/correction, system performance depends on the total error or, in other words the total noise power, across all of the FFT outputs rather than on any individual value.

Abstract: A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second operating mode in response to a transition in instruction addresses between a first address space and a second address space, wherein addresses in the first and second address spaces access a common memory space; in the first operating mode, accessing instructions in the first address space; in the second operating mode, accessing instructions in the second address space; and executing the accessed instructions of the code sequence. Instructions of different instruction lengths may be utilized in the first and second operating modes.

Abstract: Embodiments of the present invention are directed to an image processing system. The image processing system may comprise a content detection module having an input to receive a sequence of input pixels and configured to generate an adjustable parameter based on detected differences between adjacent pairs of input pixels, and a digital filter having an input for the sequence of input pixels and a control input coupled to an output of the content detection module. The digital filter may adjust filtering coefficients according to the parameter.

Abstract: A micromachined microphone is formed from a silicon or silicon-on-insulator (SOI) wafer. A fixed sensing electrode for the microphone is formed from a top silicon layer of the wafer. Various polysilicon microphone structures are formed above a front side of the top silicon layer by depositing at least one oxide layer, forming the structures, and then removing a portion of the oxide underlying the structures from a back side of the top silicon layer through trenches formed through the top silicon layer. The trenches allow sound waves to reach the diaphragm from the back side of the top silicon layer. In an SOI wafer, a cavity is formed through a bottom silicon layer and an intermediate oxide layer to expose the trenches for both removing the oxide and allowing the sound waves to reach the diaphragm. An inertial sensor may be formed on the same wafer, with various inertial sensor structures formed at substantially the same time and using substantially the same processes as corresponding microphone structures.

Abstract: An embodiment of an amplifier circuit includes a plurality of amplifiers connected between input and output terminals to form at least partially parallel amplification paths between the terminals. A first plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common first series-connected amplifier, and a second plurality of the amplification paths have different first amplifiers. Optionally, a third plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common last series-connected amplifier, and a fourth plurality of the amplification paths have different last amplifiers. Alternatively, a first plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common last series-connected amplifier, and a second plurality of the amplification paths have different last amplifiers.

Abstract: A nickel-based material is used on one or both wafers to be bonded, and the two wafers are bonded at low temperature and pressure through interdiffusion of the nickel-based material with either another nickel-based material or aluminum. In various embodiments, nickel-based walls are formed on one wafer, and corresponding walls are formed on the other wafer from a nickel-based material or aluminum. The walls of the two wafers are placed in contact with one another under sufficient pressure and temperature to cause bonding of the walls through interdiffusion.

Abstract: A transceiver for use in a bidirectional optical communication link over a multimode channel is provided. The transceiver includes a single transverse mode light source in a transmitter. A waveguide or fiber based bidirectional coupler projects the transmitter mode to the high modes of the multimode channel. A detector coupled to predominantly all the modes of the channel via the waveguide or fiber based bidirectional coupler.

Abstract: Reference network embodiments are provided for use in pipelined signal converter systems. The network embodiments are fast and power efficient and they generate low-impedance reference signals through the use of at least one output transistor, a diode-coupled transistor coupled to the output transistor, and a controller. The controller is configured to provide a backgate voltage to the diode-coupled transistor to thereby establish a substantially-constant output current. The controller is further configured to provide a gate voltage to the output transistor to establish a reference voltage.

Abstract: A circuit includes an NMOS transistor having a drain and a source, a p-well containing the drain and the source, an n-well under the p-well, and a first well switch configured to selectively connect the n-well to a predetermined voltage in response to an enable phase of a first switching signal. The first well switch can be configured to connect the n-well to the predetermined voltage during the enable phase of the first switching signal and to electrically float the n-well during a non-enable phase of the first switching signal.

Abstract: A method of manufacturing semiconductor devices by applying a pattern of adhesive pads on an active surface of a semiconductor wafer, the semiconductor wafer product so made and a stacked die package in which an adhesive wall leaves an air gap atop a bottom die. The wall may be in the form of a ring of adhesive about a central hollow area. The wafer carrying the pattern of adhesive pads on its active surface is singulated into individual dies, each die having an adhesive pad thereon. The bottom die is attached to a base with an adhesive which cures without curing the adhesive pad.

Abstract: Channel estimation for high mobility OFDM channels is achieved by identifying a set of channel path delays from an OFDM symbol stream including carrier data, inter-channel interference noise and channel noise; determining the average channel impulse response for the identified set of channel path delays in each symbol; storing the average channel impulse responses for the identified channel path delays; generating a path delay curvature for each channel path delay in each symbol based on stored average channel impulse responses for the identified channel path delays; estimating the carrier data in the symbols in the OFDM symbol stream in the presence of inter-channel interference noise and channel noise from the OFDM symbol stream and the average impulse responses for the identified channel path delays; reconstructing the inter-channel interference noise in response to the path delay curvature, the identified set of channel path delays and estimated carrier data; and subtracting the reconstructed inter-channe

Abstract: An exemplary method and system of addressing an integrated circuit within a daisy chain network. In the exemplary method, the address of the integrated circuit may be initialized to a predetermined initial address. The integrated circuit may receive a command that includes a type identifier and an address field. Based on the type identifier, the type of command may be determined. As a result of the determination, reading the address from the address field. The read address may be stored in a register. The address may be modified, and may be output. Upon receipt of the data or a command, the integrity of the data including data within the received command, may be confirmed by an error checking algorithm.