Abstract: An integrated-circuit 12-bit digital-to-analog converter comprising binarily-scaled constant-current sources with associated switch cells employing bipolar transistors to direct the bit currents either to a summing bus or to ground. The switch cells include a first differential transistor pair to translate a single-ended binary logic signal to double-ended (balanced) format, and a second, fully-balanced differential pair operated by the balanced logic signal to direct the bit current correspondingly. A bias-generating circuit maintains a constant collector-base voltage at the constant-current source. The threshold voltage for the logic signals can be set for TTL logic or, by pin-programming, for CMOS logic of either low-voltage or high-voltage type.

Abstract: An isolation amplifier comprising an input section coupled by a multi-winding transformer to an output section. A blocking oscillator produces in the transformer a signal comprising a positive power pulse followed by a negative flyback pulse. The flyback pulse magnitude is modulated by a half-wave diode-capacitor rectifier circuit which supplies negative supply current to an amplifier in the input section. Other half-wave diode-capacitor rectifier circuits in the input section develop (1) a positive supply voltage for the amplifier, (2) a negative feedback signal for the amplifier, and (3) a level-shifting voltage to be combined with the feedback signal. The output section includes additional half-wave diode-capacitor rectifier circuits to develop a demodulation signal derived from the flyback pulse, and a bias voltage to be combined with that signal to develop an input signal for the output amplifier.

Abstract: An analog signal is converted into an n bit digital signal by n comparator circuits which compare the analog input to 2.sup.n -1 reference inputs. Each comparator output alternates as the analog signal increases through the reference levels. Logic circuitry including n-1 exclusive-OR gates decodes the comparator outputs into an n bit code.A comparator circuit for comparing the analog input signal with each of several reference levels and providing an alternating output includes a pair of differential input transistors and a current sink transistor associated with each reference level. The collectors of the differential transistor pairs are cross coupled to two output resistors which are connected to a differential exclusive-OR gate. A latching circuit is operable to latch the comparator output when the comparator is in other than the comparing mode.

Abstract: Signal-processing circuitry including at least two pairs of bipolar transistors with the transistors of one pair being series-connected with the transistors of the second pair, and the second pair being cross-connected from collector-to-base. Other circuitry includes (1) an input arrangement for converting a single-ended input voltage to a complementary pair of currents, (2) a differential emitter-follower providing 2V.sub.BEs of level-shifting, (3) means for obtaining an output signal proportional to the square of an input signal, and (4) a simple active rectifier.

Abstract: A temperature-compensated band-gap reference of the type employing two transistors operated at different current densities to develop a positive TC current. This current flows through a first resistor of nominal TC to develop a positive TC voltage which is connected in series with a negative TC voltage developed by the base-to-emitter voltage of a transistor, to produce a composite temperature compensated output voltage. The circuitry further includes a second resistor connected in series with the first resistor and having a positive TC to produce an additional compensating voltage having a temperature coefficient following a parabolic expression. This additional voltage, when connected with the other components of the output voltage, reduces the small residual inherent TC of the band-gap reference to provide a more stable reference source.

Abstract: An IC chip having a Zener diode with a subsurface breakdown junction to assure stable operation. The diode is formed by a triple diffusion process compatible with conventional bipolar processing. A deep p.sup.++ diffusion first is applied, reaching through the epitaxial region to the buried n.sup.+ layer; next, a shallow p.sup.+ diffusion is formed over the deep p.sup.++ diffusion and extending laterally beyond that diffusion; finally, a shallow n.sup.+ diffusion is applied over the p diffusions, to form a subsurface breakdown junction therewith. The topology of the mask windows is selected to provide concentration profiles which insure that the breakdown occurs at the subsurface junction, and that other desirable diode characteristics are achieved.

Abstract: An integrated-circuit 12-bit digital-to-analog converter comprising binarily-scaled constant-current sources with associated switch cells employing bipolar transistors to direct the bit currents either to a summing bus or to ground. The switch cells include a first differential transistor pair to translate a single-ended binary logic signal to double-ended (balanced) format, and a second, fully-balanced differential pair operated by the balanced logic signal to direct the bit current correspondingly. A bias-generating circuit maintains a constant collector-base voltage at the constant-current source. The threshold voltage for the logic signals can be set for TTL logic or, by pin-programming, for CMOS logic of either low-voltage or high-voltage type.

Abstract: An IC chip having a Zener diode with a subsurface breakdown junction to assure stable operation. The diode is formed by a triple diffusion process compatible with conventional bipolar processing. A deep p.sup.++ diffusion first is applied, reaching through the epitaxial region to the buried n.sup.+ layer; next, a shallow p.sup.+ diffusion is formed over the deep p.sup.++ diffusion and extending laterally beyond that diffusion; finally, a shallow n.sup.+ diffusion is applied over the p diffusions, to form a subsurface breakdown junction therewith. The topology of the mask windows is selected to provide concentration profiles which insure that the breakdown occurs at the subsurface junction, and that other desirable diode characteristics are achieved.

Abstract: An integrated circuit two terminal temperature transducer providing an accurate current output that is linearly related to absolute temperature over an extended temperature range. The circuit is of the type using first and second transistors having conductive areas of different sizes, and control transistors for supplying equal currents through the first and second transistors to operate them at different current densities, and a resistor responsive to the base-to-emitter voltages of the first and second transistors for developing currents therethrough proportional to absolute temperature. Improved accuracy over an extended temperature range is provided in a two terminal device by means of a third transistor coupled to the first and second transistors to generate another controlled current varying linearly with absolute temperature to be combined with the currents through the first and second transistors to form an output current.

Abstract: A protective case for an electrical instrument on a circuit board, arranged to mount the instrument upon a panel in an opening provided therein. The case is characterized by a housing having an end opening for introduction of the circuit board therein and a snap-in mounting structure for automatically and securely mounting a circuit board within the housing. The mounting structure includes means forming a ledge, provided for example by four corner platforms molded into the housing, for supporting one side of the circuit board. Two pairs of opposed resilient fingers, preferably molded integrally with the walls of the housing, extend with an inward cant along the path of the circuit board from opposite interior sides of the housing to be flexed outwardly by the edges of the circuit board as it is introduced into the housing.

Abstract: An analog-to-digital converter of the successive-approximation type including a digital-to-analog converter (DAC) comprising a plurality of independently-switchable current sources producing identical currents and connected to respective junction points of an R-2R ladder network. The common ladder terminal is driven by an operational amplifier so that the potential of the common terminal tracks that of the ladder output terminal. The ladder common terminal is connected to a comparator together with a sense ground lead. The output of the comparator is directed to bit sequencer circuitry which controls the switching of the DAC current sources to effect a match between the analog input current and the ladder output current.

Abstract: A digital-to-analog converter of the type formed with a plurality of current source transistors arranged to carry different levels of current according to a predetermined weighting pattern, e.g., a binary weighting pattern. In the converter, a plurality of identically sized current source transistors carry the different levels of current and thus operate at different current densities with different base-to-emitter voltages subject to temperature drift. Stable emitter voltages, providing accurate levels of weighted current, are developed by means of resistances between the bases of successive current source transistors and a current source for developing across the interbase resistances a voltage linearly varying with absolute temperature, corresponding to the difference between base-to-emitter voltages of the successive current source transistors.

Abstract: A digital-to-analog converter comprising an IC switch module providing four switch transistors and associated switch-control buffering circuitry. The emitter areas of the switch transistors are binarily weighted to provide equal current densities. The IC substrate also is formed with a fifth transistor to serve as a reference transistor for adjusting the supply voltage as necessary to maintain constant current through the switch transistors. To construct a digital-to-analog converter having a high bit resolution, a number of such "quad" switch modules may be combined, for example in a printed circuit card assembly including a thin-film resistor module providing binarily-weighted resistors on a glass substrate to set the current levels through the switch transistors.

Abstract: A digital-to-analog converter having means to suppress the transient signals present at the output of the converter in response to a clock pulse synchronized with the transient signal. The clock pulse applies a forward bias to a pair of series-connected diodes which clamp the digital-to-analog converter output to ground. An integrator is connected to the converter output terminal to stabilize and filter the output signal while the terminal is clamped to ground.

Abstract: A transistor amplifier of the Darlington type, in which successive transistors have their collectors connected in common and in which the emitter of the first transistor is connected to the base of the second transistor, is characterized by a source of bias current for the first transistor which tends to suppress variations in transistor current gain and which permits the Darlington amplifier to operate in differential configurations with low offset voltage drift and low offset current drift. The bias current source is arranged to direct between the emitter of the first transistor and the emitter of the second transistor a bias current which is a predetermined fraction, e.g., one-tenth, of the collector current of the second transistor, thereby stabilizing the operation of the first transistor.

Abstract: A digital-to-analog converter comprising an IC switch module providing four switch transistors and associated switch-control buffering circuitry. The emitter areas of the switch transistors are binarily weighted to provide equal current densities. The IC substrate also is formed with a fifth transistor to serve as a reference transistor for adjusting the supply voltage as necessary to maintain constant current through the switch transistors. To construct a digital-to-analog converter having a high bit resolution, a number of such "quad" switch modules may be combined, for example in a printed circuit card assembly including a thin-film resistor module providing binarily-weighted resistors on a glass substrate to set the current levels through the switch transistors.

Abstract: An integrated-circuit 12-bit digital-to-analog converter comprising binarily-scaled constant-current sources with associated switch cells employing bipolar transistors to direct the bit currents either to a summing bus or to ground. The switch cells include a first differential transistor pair to translate a single-ended binary logic signal to double-ended (balanced) format, and a second, fully-balanced differential pair operated by the balanced logic signal to direct the bit current correspondingly. A bias-generating circuit maintains a constant collector-base voltage at the constant-current source. The threshold voltage for the logic signals can be set for TTL logic or, by pin-programming, for CMOS logic of either low-voltage or high-voltage type.

Abstract: A digital-to-analog converter the output circuit of which comprises a set of switching transistors arranged as current generators. The currents through the switching transistors are maintained constant by means of a supply voltage adjusting circuit comprising a separate reference transistor matched to one of the switching transistors and energized by the same voltage supply lines as the switching transistors. The supply voltage adjusting circuit includes an operational amplifier which senses the collector current of the reference transistor, and adjusts the supply voltage so as to maintain that collector current constant. This automatic adjustment of the supply voltage also maintains the current through the switching transistors constant.

Abstract: An analog-to-digital converter of the ramp-integrator type utilizing a special technique to reduce errors due to offset voltages. The integrator first is ramped up and then back to a reference level, by sequential application of opposite-polarity reference signals. A digital determination of net offset error then is made by comparing the total time of ramp-up-and-back with a fixed time period set by a clock generator. During the subsequent conversion operation, integration of the analog signal is controlled in accordance with the amount of net offset error so as to provide a feed-forward error correction. Integration is always in the same direction away from zero for analog signals of either polarity, thus avoiding the effects of discontinuity around zero input.

Abstract: A solid-state (IC) regulated voltage supply compensated for effects of changes in temperature comprising first and second transistors operated at different current densities. Associated circuitry develops a voltage proportional to the .DELTA.V.sub.BE of the two transistors and having a positive temperature coefficient. This voltage is connected in series with the V.sub.BE voltage of one of the two transistors, having a negative temperature coefficient, to produce a resultant voltage with nearly zero temperature coefficient. A feedback circuit responsive to current flow through the two transistors automatically adjusts the base voltages to maintain a predetermined ratio of current density for the two transistors. Other embodiments provide higher-level DC outputs and compensation for base current flow.