Abstract: A digital-to-analog converter capable of high resolution performance, e.g. for converting 16-bit digital signals, comprising a cascaded two-stage device wherein the first stage consists of a segment converter with a series-connected string of resistors and switches operable by a set of high-order input bits for selecting the voltage across any one of the resistors, buffer amplifiers for directing the selected voltage to the input of a second-stage converter comprising a CMOS DAC with an R/2R ladder controlled by a set of lower order bits to interpolate between the limits of the selected voltage from the first stage, and wherein the switches for the first stage function to interchange the roles of the buffer amplifiers for each step up (or down) the resistor string so as to eliminate or minimize differential non-linearity errors due to offset mismatch between the buffer amplifiers.

Abstract: A two-stage analog-to-digital converter wherein the first stage is a resistor-string d-to-a converter controlled by a successive-approximation register, functioning in a first phase of the conversion operation to determine a set of higher order bits of the digital output signal. The second stage is a dual-slope integrating-type a-to-d converter functioning in a second phase of the conversion operation to determine the remaining lower-order bits of the digital output signal. The dual-slope converter receives a reference signal derived from two adjacent junction points of the first-stage resistor-string d-to-a converter corresponding to the higher order bits determined in the first phase of operation, thereby to assure high resolution performance.

Abstract: A single-chip 8-bit DAC with bipolar current sources, an output buffer amplifier for developing an output voltage, a regulated reference for producing a calibrated output, and operated by a single-voltage supply, e.g. +5 volts. The buffer amplifier includes means providing for driving the output voltage virtually to ground level when the DAC output is zero. The current sources comprise a single-transistor cell driven by an I.sup.2 L flip-flop circuit, and the reference supply is merged with the reference transistor circuit regulating the DAC current levels, both aiding in reducing required chip area. A highly efficient bias network is utilized to supply the high-level bias currents required.

Abstract: A technique for enclosing microelectronic circuit elements in hermetically sealed packages comprising a planar ceramic substrate with a box-like ceramic cover sealed thereto by a fused glass coating. The glass sealant is applied to the substrate in the form of a paste which thereafter is fired at high temperature and cooled to produce a smooth glass coating. With the cover in place on the substrate, the glass coating is remelted by heat developed by infra-red radiation impinging on all sides of the package structure from heaters in an infra-red furnace. A reflective shield on top of the cover reduces the inflow of heat through that surface, and a heat sink beneath the substrate removes heat, thereby to reduce the temperature rise experienced by circuit elements in the package interior.

Abstract: A universal trigonometric function generator which is selectively programmable by pin-strapping to generate any of the standard trigonometric functions (sine, cosine, tangent, cotangent, secant and cosecant). The circuit includes two identical sine-function generating networks each of which produces an output signal proportional to the sine of a corresponding angle input. These networks are so interrelated that the composite output signal is proportional to the angle input of one network and inversely proportional to the angle input of the other network, producing an output ##EQU1## where A is a controllable amplitude, .theta..sub.1 -.theta..sub.2 is the angle input to one network, and .phi..sub.1 -.phi..sub.2 is the angle input to the other network. By selectively connecting the input terminals for .theta..sub.1, .theta..sub.2, .phi..sub.1, .phi..sub.2 to an angle control signal and reference voltages corresponding to 0.degree. and 90.degree., any one of the standard trigonometric functions can be generated.

Abstract: An integrated-circuit thermocouple signal conditioner having on a single chip an amplifier and a transistor circuit responsive to the chip temperature for developing a cold-junction compensation signal referred to 0.degree. Celsius. The amplifier includes two matched differential input amplifiers the outputs of which are summed and used to control a high-gain main amplifier. Thermocouple signals are applied to one of the input amplifiers, serving as a floating input stage, and the main amplifier output is connected through a feedback network to the input of the other differential amplifier. A cold junction compensation signal also is applied to the input of the other differential amplifier. The compensation is a differential voltage proportional to the Celsius temperature of the chip; the compensation voltage comprises two components having positive and negative temperature coefficients.

Abstract: A sine-function generator comprising a plurality of bipolar transistors with their collectors connected to a pair of output terminals in alternating antiphase and their emitters connected in common to a single current source. The bases of the transistors are connected to respective nodal points of a base-bias network comprising a series-connected string of equal resistors. Current sources supply equal currents to the network nodal points to develop base voltages at those points according to a predetermined distribution pattern establishing a peak voltage along a line representing the nodal sequence. An input signal applied to the ends of the resistor string controls the location of this voltage peak along the nodal line, thereby controlling the current flow through the transistors in such a way that the net differential output current is proportional to the sine of the angle represented by the input signal. A ladder-type base-bias network also is disclosed.

Abstract: An analog-to-digital converter operable in sequential phases and including a main digital-to-analog converter (DAC) controlled by a successive-approximation-register to develop a first digital signal representing a first approximation of the analog input signal. In subsequent phases, the residual difference between the anolog input signal and the output of the main DAC is converted to a second digital signal representing the proportion which the residual signal bears to the difference between the first analog output of the main DAC and a second analog output of that DAC after it has been incremented by one least-significant-bit beyond the first DAC input developed in the successive-approximation phase. This proportioning operation is in one embodiment performed by a multiplying A-to-D converter, and in other embodiments is performed by an interpolation DAC. Microcomputer control of the various operations is disclosed.

Abstract: Apparatus for determining the number of turns of a test coil wound on a magnetic core comprising a reference coil with a pre-fixed number of turns wound on a reference core and coupled to a resistive load. The test coil is linked to the reference coil by a single-turn primary supplied with a-c current of substantially constant amplitude. An adjustable resistive load is connected across the test coil. Both load resistors are of low ohmic value, to operate the two coils as heavily-burdened current transformers. The coil voltages are compared by a phase-sensed comparator, and the adjustable resistor is set to produce a null comparison condition. At this condition, the number of turns of the test coil will be proportional to the resistance of the adjustable resistor, and this number is indicated by a calibrated digital read-out device.

Abstract: An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I.sup.2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.

Abstract: An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I.sup.2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.

Abstract: An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I.sup.2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC.

Abstract: A method of laser trimming thin film resistors on semiconductive substrates wherein the laser is set to a frequency equal to or less than E.sub.g /h, where E.sub.g is the optical band-gap energy of the doped semiconductor substrate, and h is Planck's constant.

Abstract: A signal isolator including a coupling transformer with modulate/demodulate switches in series with the primary and secondary windings. The switches are driven in synchronism by an oscillator. Resonating capacitors are connected in parallel with the transformer windings to form an LC tank circuit tuned approximately to the operating frequency of the switch-drive oscillator. When the switches are closed, the current in the transformer windings ramps in a linear fashion in response to application of the input voltage, and when the switches are opened, the current varies in a cosine curve to provide smooth transitions at both ends to the ramp current, thus controlling the flux in the transformer core so as to minimize instability effects.

Abstract: A signal isolator including a coupling transformer with modulate/demodulate switches in series with the primary and secondary windings. The switches are driven in synchronism by an oscillator. Resonating capacitors are connected in parallel with the transformer windings and tuned to the switch operating frequency to control the flux in the transformer core. A transformer turns-ratio of less than unity introduces a corresponding attenuation, and a following amplifier counteracts that attenuation to produce an output signal at the original level. A return current resistor is connected between the output signal and the transformer secondary to produce a back-flow of current towards the transformer. This current provides for supplying the losses of the coupling circuit in a symmetrical fashion, both from the isolator input and its output, to reduce significantly variations in performance resulting from changes in ambient temperature.

Abstract: This invention relates to a method of trimming an element of an integrated circuit with a laser beam. A reflective, or otherwise optically opaque, template-like layer is placed over a portion of the circuit element to control the trimming operation. The laser beam is directed along the sharp edge of this layer in such a way that the maximum energy portion of the beam strikes a part of the circuit element, while low energy portions of the beam are prevented from reaching other parts of the element where they might adversely affect its characteristics.

Abstract: A digital-to-analog converter comprising a plurality of identical transistor current sources with their emitters connected to respective shunt legs of an R-2R ladder network for establishing binary weighting of the transistor currents. The effects of variations in transistor offset voltage are compensated for by returning the ladder termination resistor to a voltage which is 2(kT/q)1n 2 more positive than the last active stage of the converter.

Abstract: A digital-to-analog converter capable of high resolution performance, e.g. for converting 16-bit digital signals, comprising a cascaded two-stage device wherein the first stage consists of a segment converter with a series-connected string of resistors and switches operable by a set of higher-order input bits for selecting the voltage across any one of the resistors, buffer amplifiers for directing the selected voltage to the input of a second-stage converter comprising a CMOS DAC with an R/2R ladder controlled by a set of lower order bits to interpolate between the limits of the selected voltage from the first stage, and wherein the switches for the first stage function to interchange the roles of the buffer amplifiers for each step up (or down) the resistor string so as to eliminate or minimize differential non-linearity errors due to offset mismatch between the buffer amplifiers.

Abstract: A single-chip 8-bit DAC with bipolar current sources, an output buffer amplifier for developing an output voltage, a regulated reference for producing a calibrated output, and operated by a single-voltage supply, e.g. +5 volts. The buffer amplifier includes means providing for driving the output voltage virtually to ground level when the DAC output is zero. The current sources comprise a single-transistor cell driven by an I.sup.2 L flip-flop circuit, and the reference supply is merged with the reference transistor circuit regulating the DAC current levels, both aiding in reducing required chip area. A highly efficient bias network is utilized to supply the high-level bias currents required.

Abstract: A temperature-compensated IC voltage reference comprising a Zener diode serving as the principal voltage source, in combination with a compensating voltage source including a transistor providing a forward-biased junction, and control circuitry. The compensating voltage is summed with the Zener voltage to produce a reference voltage. The compensating voltage source includes an adjustment element for trimming the reference output to a specified voltage, and the control circuitry operates with that adjustment element to automatically produce optimum temperature compensation when the output has been adjusted to the specified value.