Abstract: Apparatus and methods for phasing detection of asynchronous dividers are provided herein. In certain embodiments, a clock and data recovery system includes a first divider that outputs a first divided clock signal, a second divider that outputs a second divided clock signal, and an asynchronous clock phasing detection circuit that generates a detection signal indicating a relative phase difference between the first divided clock signal and the second divided clock signal. The asynchronous clock phasing detection circuit includes a quantization and logic circuit that generates an output signal indicating when the first divided clock signal and the second divided clock signal are in different states, an oscillator that outputs a control clock signal, a first counter controlled by the control clock signal and configured to count the output signal, and a control circuit that processes a first count signal from the first counter to generate the detection signal.

Abstract: Apparatus and methods for controlling a clock signal are provided. In certain embodiments, a semiconductor die includes a core circuit and a clock interface circuit that provides a clock signal to the core circuit. The clock interface circuit includes an oscillator for generating an oscillator signal, and a comparator for controlling operation of the clock interface circuit in a selected clock control mode based on comparing an electrical characteristic of the clock interface pin to a comparison threshold. The selected clock control mode is chosen from a first clock control mode in which the clock interface circuit generates the clock signal based on an input clock signal received on a clock interface pin, or a second clock control mode in which the clock interface circuit generates the clock signal based on the oscillator signal.

Abstract: Systems and methods for performing calibration of antenna arrays with dual-polarization antenna elements are disclosed. An example system includes an antenna array and a calibration circuitry. The antenna array includes a plurality of antenna cells arranged in K rows and L columns, each cell including a plurality of dual-polarization antenna elements. Antenna cells in columns 1 through Y form a first sub-array, while antenna cells in columns Y+1 through L form a second sub-array. The calibration circuitry is configured to perform calibration by individually calibrating each column of antenna cells of the first sub-array, calibrating different columns of antenna cells of the first sub-array with respect to one another, individually calibrating each column of antenna cells of the second sub-array, calibrating different columns of antenna cells of the second sub-array with respect to one another, and calibrating antenna elements of the first and second sub-arrays with respect to one another.

Abstract: Time-of-flight (ToF) systems which use pulsed laser diodes, are required to measure distances with high level of precision and control. The present disclosure provides a method and a corresponding system for controlling a temporal response of a laser diode, in particular pulsed laser diodes. In particular, the present disclosure provides a method and a related system for driving a laser diode so as to obtain predominantly a peak pulse response while minimising or completely avoiding the post-peak response in a temporal response of the laser diode.

Abstract: Techniques for controlling a current of a battery cell during formation and/or testing are described. A current sensor is used to measure the current of the battery cell, which is used as a feedback signal for controlling the current to achieve a target current. The transfer function of the current sensor is used to improve the accuracy of the current measurement. Because the transfer function can be regularly determined during formation/testing, a lower-cost current sensor with relatively poor temperature coefficient may be used. Any change in the gain of the current sensor may be detected by the transfer function determination and corrected for. Therefore, high current control accuracy may be achieved at lower cost.

Abstract: A data converter circuit comprises timing circuitry configured to time stages of a conversion performed by the data converter circuit; a level shifter circuit configured to receive a control signal associated with the conversion and provide a level shifted version of the control signal to one or more switch circuits of the data converter circuit; and a time delay circuit element including a replica circuit of the level shifter circuit that adds a circuit delay to a transition of the control signal at the timing circuitry.

Abstract: High-performance radio frequency analog-to-digital converters (RF ADCs) demand high bandwidth, high linearity, and low noise input amplifiers. A Class-AB amplifier, including common-gate transistor devices and common-source transistor devices operating in parallel, offers high bandwidth and high linearity, while offering lower power operation when compared to Class-A amplifiers. The Class-AB amplifier can be followed by a Class-AB unity gain buffer comprising common-source transistor devices to provide additional isolation for the RF ADC from the circuitry preceding the Class-AB amplifier.

Abstract: An impedance sensing circuit includes three impedance elements and a sensing element arranged in a bridge configuration. A first input terminal is coupled to two of the impedance elements to apply a stimulus signal. In a mutual-sensing mode, a second input terminal is coupled to the third impedance element and the sensing impedance element to apply an opposite phase stimulus signal. The impedance sensing circuit may be configured in a self-sensing mode, in which the opposite phase stimulus signal is decoupled from the third impedance element and the sensing impedance element. At least one of the impedance elements is variable and may be adjusted to balance an offset impedance load on the sensing element.

Abstract: A closed loop switch control system and a corresponding method is provided for controlling an impedance of a switch. The switch, which usually comprises a transistor switch, may be part of an external circuit. The system comprises the switch and a control unit coupled to the switch. The control unit is configured to regulate an impedance of the switch to a reference impedance while also enabling a fast switch response time. This is achieved by configuring the control unit to have a frequency response comprising a plurality of dominant poles and at least one zero.

Abstract: Techniques are provided for a multiple-layer planar transformer having center taps of a segmented winding. In an example, a multiple-layer planar transformer can be a coupled inductor circuit including a first winding comprising a conductive coil having an electrical path defining and encircling the central axis, a second winding configured to magnetically couple with the first winding, the second winding having a plurality of individual segments, wherein each individual segment forms a fraction of one turn of the second winding, and a first output inductor coupled to a first common node of the second winding. The first common node can directly couple a first node of a first individual segment of the plurality of individual segments with a first node of a second individual segment of the plurality of individual segments.

Abstract: A measurement circuit comprises an electronic circuit, multiple measurement channels, and a combining circuit. The electronic circuit includes a first terminal, a second terminal, and a non-resistive circuit element. Each of the multiple measurement channels includes a differential input connected to the electronic circuit. The differential inputs of the multiple measurement channels are connected in series and include a differential input coupled to the non-resistive circuit element. One input of a differential input of a first measurement channel of the multiple measurement channels is connected to the first terminal of the electronic circuit and one input of a differential input of a second measurement channel of the multiple measurement channels is connected to the second terminal of the electronic circuit. The combining circuit receives multiple outputs from the multiple measurement channels and produce a composite output signal.

Abstract: An exponential scale pulse width modulation (PWM) controller comprises a waveform generator circuit configured to generate a logarithmic waveform signal that has the shape of an increasing logarithm function; and a first comparator circuit including a first input to receive the logarithmic waveform signal, a second input to receive an input signal, and an output that provides a PWM control signal that includes signal pulses having a duty cycle that changes exponentially with respect to the input signal.

Abstract: Techniques for improving efficiency of wireless power transfer to shunt-based receiver are provided. In an example, techniques can optimize wireless power transfer by comparing instantaneous peak voltage of a transmit coil of a wireless power transmitter to an average peak voltage of the transmit coil, and then, based on the comparison, adjust a setpoint of the wireless power transmitter to a more efficient level.

Abstract: Phased arrays to be used for Tx and Rx communications in different frequency bands are disclosed. The phased arrays presented herein are non-uniformly thinned half-duplex phased arrays with dual-band antenna elements. Such phased arrays are “half-duplex” in that they are configured for communication in one direction at a time, i.e., either for Tx or for Rx, while utilizing a common array. Such phased arrays are “with dual-band antenna elements” in that, in addition to using antenna elements configured for Tx or for Rx only, they implement some antenna elements that are configured for both Tx and Rx. Such phased arrays are “thinned” in that they are formed according to a method of optimizing array geometry known as “thinning.” Such phased arrays are thinned “non-uniformly” in that different antenna elements used for Tx may have different numbers of nearest and/or second-nearest neighbor antenna elements used for Rx, or vice versa.

Abstract: An image processing system having on-the-fly calibration uses the placement of the imaging sensor and the light source for calibration. The placement of the imaging sensor and light source with respect to each other affect the amount of signal received by a pixel as a function of distance to a selected object. For example, an obstruction can block the light emitter, and as the obstruction is positioned an increasing distance away from the light emitter, the signal level increases as light rays leave the light emitters, bounce off the obstruction and are received by the imaging sensor. The system includes a light source configured to emit light, and an image sensor to collect incoming signals including reflected light, and a processor to determine a distance measurement at each of the pixels and calibrate the system.

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: An integrated circuit (IC) die is disclosed. The IC die can include a signal via extending through the IC die. The IC die can include a transmission line extending laterally within the IC die in a direction non-parallel to the signal via, the transmission line configured to transfer an electrical signal to the signal via. The IC die can include a matching circuit disposed between the transmission line and the signal via. The matching circuit can include inductance and capacitance matching circuitry to compensate for parasitic inductance and capacitance introduced by transition from the IC die to an underlying carrier.

Abstract: The present disclosure enables firmware-based interleaved-ADC gain calibration and provides hardware-thresholding enhancements. An on-chip memory may store subADC samples and a microprocessor accesses these stored samples for use with the calibration algorithm. Power estimates may be performed using square of each subADC sample to estimate gain error. Thresholding may be applied to the subADC samples, such as Maximum Amplitude Thresholding, Minimum Power Thresholding, and/or using Histogram Output Memory, to determine that samples are valid and may be used for calibration or that subADC data are to be discarded and a new subADC data capture is to be started.

Abstract: Systems and methods that enable LED drivers to generate drive signals by implementing a modulation technique referred to herein as “stochastic frequency pulse modulation” (SFPM) are disclosed. The SFPM is based on randomly increasing or decreasing, during every cycle of a drive signal, the amount of time the drive signal is high or low, tracking the deviation of the total amount of time (i.e., for multiple cycles) that the drive signal is high or low from what it should be to provide to a LED a target average power dictated by a target dimming level, and using the tracking to set limits of ranges from which the durations of the time periods when the drive signal is high or low may be randomly selected.

Abstract: A device having a structure to measure a battery parameter of a battery of a set of multiple batteries can be implemented in a variety of applications. The device can be structured to measure alternating current (AC) electrical impedance of a battery cell by processing a difference between the battery cell and another battery cell. The battery cell being measured is subjected to AC excitation while the other one is not, where the two battery cells share a common load current. This differencing method can reduce the measurement's sensitivity to noisy battery load current, which is common to both battery cells. This differencing method also can remove or substantially reduce a large direct current (DC) offset, that is, the battery potential itself under which the AC signal measurement is burdened.