Abstract: One embodiment is a microelectronic assembly including an assembly support structure; a first die including a pair of hot via comprising through-substrate-via (TSVs) extending through the first die between first and second sides thereof and a plurality of ground vias surrounding the pair of hot vias and extending through the first die between the first and second sides thereof. The first die further includes a pair of signal interconnect structures electrically connected to the pair of hot vias disposed on the second side of the first die. The assembly further includes a second die between the assembly support structure and the first die the pair of signal interconnect structures disposed on the first side thereof. The first die is connected to the second die via a signal die-to-die (DTD) interconnect structure including the signal interconnect structures of the first and second dies.

Abstract: Systems, devices, and methods related to performing digital predistortion in radio frequency (RF) systems are provided. A digital predistortion (DPD) arrangement includes a DPD actuator circuit to predistort, using DPD coefficients, at least a portion of an input signal, the DPD coefficients associated with a characteristic of a nonlinear component. The DPD arrangement further includes a DPD capture circuit to perform, based on a capture cycle timing, multiple captures of a feedback signal, the feedback signal indicative of an output of the nonlinear component; compute, based on one or more characteristics of the multiple captures, one or more criteria for a subsequent capture of the feedback signal; and perform, based on the one or more criteria, the subsequent capture of the feedback signal. The DPD arrangement circuit further includes a DPD adaptation circuit to update the DPD coefficients based at least in part on the subsequent capture.

Abstract: Video systems with video receivers for receiving video signals transmitted in analog format over a video link are described. An example video receiver includes an interferer identification circuit and an interferer removal circuit. The interferer identification circuit is configured to identify a periodic interference signal (e.g., from one or more of vertical blanking intervals (VBIs)) of a received video signal. The interferer removal circuit is configured to generate a filtered video signal, where generation of the filtered video signal includes, for each line of a given frame of the received video signal, generating an adjusted interference signal by adjusting a phase of the identified interference signal to match a phase of a periodic noise signal in at least a portion of a horizontal blanking interval (HBI) associated with the line, and subtracting the adjusted interference signal from a plurality of active pixel values of the line.

Abstract: Circuits and methods for protecting against over-current conditions of switches are described. Over-current conditions can damage switches and the circuits they connect. Some embodiments of the present application provide a sense switch in parallel with the load switch. The sense switch is smaller than the load switch, and is used to sense an over-current condition of the load switch. The sense switch can remain on even when the load switch is turned off in response to detection of an over-current condition.

Abstract: A hybrid temperature sensor for an integrated circuit includes two temperature sensors—an application temperature sensor for measuring temperature during normal use of the integrated circuit, and a calibration temperature sensitive element. By providing two temperature sensitive elements within the integrated circuit, it is possible to take advantage of different characteristics of temperature sensors to achieve high accuracy calibration of the application temperature sensor relatively quickly and at low cost, whilst also maintaining desirable characteristics for the application temperature sensor, such as high speed, low power consumption, high resolution, etc.

Abstract: Electrical overstress protection for electronic systems subject to electromagnetic compatibility fault conditions are provided herein. In certain implementations, a stacked thyristor protection structure with a high holding voltage includes a protection device having a trigger voltage and a holding voltage. A trigger voltage of the stacked thyristor protection structure is substantially equal to the trigger voltage of the protection device. The stacked thyristor protection structure further includes at least one resistive thyristor electrically connected to the protection device and operable to increase a holding voltage of the stacked thyristor protection structure relative to the holding voltage of the protection device. The at least one resistive thyristor comprising a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and a conductor connecting a collector of the PNP bipolar transistor to a collector of the NPN bipolar transistor.

Abstract: Voltage-to-current converters that include two current mirrors are disclosed. In an example voltage-to-current converter each current mirror is a complementary current mirror in that one of its input and output transistors is a P-type transistor and the other one is an N-type transistor. Such voltage-to-current converters may be implemented using bipolar technology, CMOS technology, or a combination of bipolar and CMOS technologies, and may be made sufficiently compact and accurate while operating at sufficiently low voltages and consuming limited power.

Abstract: A charge control structure is provided for a bipolar junction transistor to control the charge distribution in the depletion region extending into the bulk collector region when the collector-base junction is reverse-biased. The charge control structure comprises a lateral field plate above the upper surface of the collector and dielectrically isolated from the upper surface of the collector and a vertical field plate which is at a side of the collector and is dielectrically isolated from the side of the collector. The charge in the depletion region extending into the collector is coupled to the base as well as the field-plates in the charge-control structure, instead of only being coupled to the base of the bipolar junction transistor. In this way, a bipolar junction transistor is provided where the dependence of collector current on the collector-base voltage, also known as Early effect, can be reduced.

Abstract: Customizable tunable filters are provided herein. In certain implementations, a tunable filter including: a first filter bank including a plurality of high-pass filters each having a different cutoff frequency, and a second filter bank including a plurality of low-pass filters each having a different cutoff frequency. The tunable filter further includes a first pair of switches configured to select a first filter chosen from the first filter bank, and a second pair of switches configured to select a second filter chosen from the second filter bank. The tunable filter operates with a first cutoff frequency of the first filter and with a second cutoff frequency of the second filter.

Abstract: A semiconductor device having a back-side field plate includes a buffer layer that includes a first compound semiconductor material, where the buffer layer is epitaxial to a crystalline substrate. The semiconductor device also includes field plate layer that is disposed on a surface of the buffer layer. The semiconductor device further includes a first channel layer disposed over the field plate layer, where the first channel layer includes the first compound semiconductor material. The semiconductor device further includes a region comprising a two-dimensional electron gas, where the two-dimensional electron gas is formed at an interface between the first channel layer and a second channel layer. The semiconductor device additionally includes a back-side field plate that is formed by a region of the field plate layer and is electrically isolated from other regions of the field plate layer.

Abstract: An antenna apparatus for calibrating one or more of a plurality of antenna elements of an antenna array using one or more probes is disclosed. The apparatus includes an upconverter and/or downconverter (UDC) circuit and a calibration arrangement that includes a switching circuit. The switching circuit is configured to enable operation of the UDC in a first mode or in a second mode. When the UDC is in the first mode, the one or more probes are electrically disconnected from the UDC circuit and the UDC may be connected to at least one of the antenna elements. When the UDC is in the second mode, at least one of the one or more probes is connected to the UDC circuit.

Abstract: Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Abstract: Various embodiments relate to an electrical feedthrough assembly an elongate conductor and a collar at least partially surrounding the elongate conductor along a portion of a length of the elongate conductor. The collar can be composed of a material having a thermal conductivity of at least 170 W/(m-K). A shell can be disposed around the collar. At one or more operating frequencies, at least a portion of a length of the electrical feedthrough assembly can be selected to provide at least one quarter wave transform.

Abstract: High power radio frequency (RF) switches with low leakage current and low insertion loss are provided. In one embodiment, an RF switch includes a plurality of terminals including an antenna terminal, a receive terminal, and a transmit terminal. The RF switch also includes a plurality of transistors that are controllable to set the RF switch in a first mode or a second mode, and an inductor electrically connected between the antenna terminal and the receive terminal.

Abstract: An example log power detector includes a gain or attenuation circuit and a detector circuit. The gain or attenuation circuit includes a plurality of gain or attenuation elements arranged in a sequence, each gain or attenuation element configured to generate an output signal that is an amplified or attenuated version of an input signal provided thereto. The detector circuit includes a plurality of detectors, each detector configured to receive the output signal from a different one of the gain or attenuation elements and to generate a signal indicative of a power of the received output signal. At least the last detector is configured to receive a DC offset signal that is different from a DC offset signal received by at least one other detector. Such a log detector may provide effective noise compensation to reduce errors caused by input noise, especially for low-power and/or high-frequency input signals.

Abstract: Disclosed herein is a symmetric transformer in the context of a DC-DC isolated converter. The symmetric transformer reduces or eliminates asymmetry in the distribution of parasitic capacitance across the isolation barrier going from one end to another end of a primary coil, and as a result, undesirable electromagnetic interference (EMI) due to common mode dipole emission across the isolation barrier may be reduced. In some embodiments, a primary winding is split into separate first and second coils, with a serial impedance connected in between the first and second coils. The transformer is symmetric in the sense that a capacitive coupling of the first coil to a secondary winding is the same as a capacitive coupling of the second coil to the secondary winding, such that common mode EMI may be reduced.

Abstract: Different approaches that aim to extend scan range of phased array antennas by means of altering surface waves and/or altering the coupling are disclosed. One approach includes providing a phased array antenna where a surface of a substrate that houses antenna elements of the array includes openings such as trenches or grooves. Such openings in the surface effectively reduce the dielectric constant of the substrate, are easy to manufacture, and may reduce or eliminate the need to use exotic and expensive low-k dielectric materials. Another approach includes providing a phased array antenna where antenna elements are disposed over a substrate in the form of surface mount (SMT) components that are reduced in size/footprint. Using SMT antenna elements with a reduced size allows achieving the same gain while spacing antenna elements farther apart with gaps in between the antenna elements, thus also reducing the overall dielectric constant of the substrate.

Abstract: Microelectromechanical system (MEMS) inertial sensors exhibiting reduced parasitic capacitance are described. The reduction in the parasitic capacitance may be achieved by forming localized regions of thick dielectric material. These localized regions may be formed inside trenches. Formation of trenches enables an increase in the vertical separation between a sense capacitor and the substrate, thereby reducing the parasitic capacitance in this region. The stationary electrode of the sense capacitor may be placed between the proof mass and the trench. The trench may be filled with a dielectric material. Part of the trench may be filled with air, in some circumstances, thereby further reducing the parasitic capacitance. These MEMS inertial sensors may serve, among other types of inertial sensors, as accelerometers and/or gyroscopes. Fabrication of these trenches may involve lateral oxidation, whereby columns of semiconductor material are oxidized.

Abstract: Disclosed herein is a symmetric split planar transformer in the context of a DC-DC isolated converter. The symmetric split planar transformer reduces or eliminates asymmetry in the distribution of parasitic capacitance across the isolation barrier going from one end to another end of a primary coil, and as a result, undesirable electromagnetic interference (EMI) due to common mode dipole emission across the isolation barrier may be reduced. In some embodiments, the primary winding is split into at least a first coil and a second coil, each occupying a different area side-by-side on a substrate. The transformer is symmetric in the sense that a capacitive coupling of the first coil to a secondary winding is the same as a capacitive coupling of the second coil to the secondary winding, such that common mode EMI may be reduced. Each coil may include stacked spiral coil portions in multiple metal planes to increase inductive density across the isolation barrier.

Abstract: A semiconductor die with high-voltage tolerant electrical overstress circuit architecture is disclosed. One embodiment of the semiconductor die includes a signal pad, a ground pad, a core circuit electrically connected to the signal pad, and a stacked thyristor protection device. The stacked thyristor includes a first thyristor and a resistive thyristor electrically connected in a stack between the signal pad and the ground pad, which enhances the holding voltage of the circuit relatively to an implementation with only the thyristor. Further, the resistive thyristor includes a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and an electrical connection between a collector of the PNP bipolar transistor and a collector of the NPN bipolar transistor. This allows the resistive thyristor to exhibit both thyristor characteristics and resistive characteristics based on a level of current flow.