Abstract: Systems, devices, and methods related to phase shifters are provided. An example true time-delay (TTD) phase shifter structure includes a signal conductive line disposed on a first layer of the structure; a first switchable ground plane comprising a first conductive plane disposed on a second layer of the structure; a second switchable ground plane comprising a second conductive plane disposed on a third layer of the structure, where the first, second, and third layers are separate layers of the structure; a first switch coupled between the first switchable ground plane and a first ground element, the first ground element disposed on the second layer; and a second switch coupled between the second switchable ground plane and a second ground element, the second ground element disposed on the third layer.

Abstract: Systems, devices, and methods related to phase shifters are provided. An example apparatus includes a first node to receive an input signal, a second node, a first signal path coupled between the first node and the second node, and a second signal path coupled between the first node and the second node. The first signal path includes a positively coupled transformer. The second signal path includes a negatively coupled transformer. The second signal path is out-of-phase with the first signal path at the second node. The apparatus further includes a plurality of switches to select the first signal path or the second signal path. The apparatus may further include tuning capacitors to improve phase-shifting performance of the apparatus.

Abstract: A radio timing controller equipped with one or more sequence controllers is disclosed. Sequence controllers enable high degree of programmability of the radio timing controller, e.g., in terms of the number of general purpose input/outputs (GPIOs), mapping of GPIOs to specific radio controls, setting of the radio control output states, timing to sequence events at radio symbol boundaries, etc.

Abstract: A gain stage, such as an amplifier, e.g., an instrumentation amplifier, can receive an input signal and adjust the level of the input signal, e.g., amplify or attenuate. An output voltage of the gain stage can be applied to a subsequent circuit. Using various techniques, a second stage of an instrumentation amplifier, which can include a transconductance stage that converts a current to a voltage that can be applied to an output node of the instrumentation amplifier, can be removed. Removal of such a second stage can allow an output current from the gain stage to be applied directly from a current output node to an input node of a subsequent circuit.

Abstract: A voltage generator circuit can be structured to provide an output voltage having a substantially flat temperature coefficient by use of a circuit loop having transistors and a resistor arranged such that, in operation, current through the resistor has a signed temperature coefficient. The current behavior can be controlled by an output transistor coupled to another transistor, which is coupled to the circuit loop, with this other transistor sized such that, in operation, a voltage of this other transistor has a signed temperature coefficient that is opposite in sign to the signed temperature coefficient of the current through the resistor. Embodiments of voltage generator circuits can also include additional components to trim output voltage, to provide unconditional stability, or other features for the respective voltage generator circuit. In various embodiments, a voltage generator circuit can be implemented as a low drop-out (LDO) voltage regulator.

Abstract: The present disclosure relates to configuring at least one pair of devices in a physical unclonable function (PUF) apparatus and reading out at least one pair of devices for determining a persistent random PUF output. The pair of devices may be readout by measuring a physical difference between the devices/components caused by random manufacturing differences, which may then be used to determine a persistence random PUF output. Configuring the pair of devices includes measuring the random manufacturing difference and, based on that measurement, setting a readout condition for the pair of devices, which dictates aspects of the readout process that should be used for that pair of devices. Each time the pair of devices is readout in the future, it may be readout in accordance with the condition that was set at configuration.

Abstract: A hybrid silicon carbide (SiC) device includes a first device structure having a first substrate comprising SiC of a first conductivity type and a first SiC layer of the first conductivity type, where the first SiC layer is formed on a face of the first substrate. The first device structure also includes a second SiC layer of a second conductivity type that is formed on a face of the first SiC layer and a first contact region of the first conductivity type, where the first contact region traverses the second SiC layer and contacts the first SiC. The device also includes a second device structure that is bonded to the first device structure. The second device structure includes a switching device formed on a second substrate and a second contact region that traverses a first terminal region of the switching device and contacts the first contact region.

Abstract: For inductor-based DC-DC converters, a current shunt switch can provide an alternate path for the inductor current to flow that does not include the output capacitor. An amplifier circuit can be included and coupled with a control node of the current shunt switch to adjust a voltage on the control node to control an amount of inductor current diverted away from the output node. A fast linear loop can be included to ensure smooth transitions when engaging or disengaging the current shunt switch. These techniques can minimize the amount and duration of the subsequent negative output voltage excursion, which can be dependent on the specific ESL and ESR values of the output voltage capacitor, for the cases when the final value of the step-down load-transient is not zero. These techniques can improve a positive output voltage response caused by an output load transient in the negative direction.

Abstract: A Power over Data Lines (PoDL) system provides a DC voltage and differential data signals on the same wire pair. A Powered Device (PD) load is coupled to the wire pair, via a gyrator, for being powered by the DC voltage. The gyrator emulates the DC-coupling properties of inductors using active components. The gyrator includes transistors that are controlled to act as a full-bridge rectifier for ensuring a correct polarity DC voltage is applied to the PD load. Since the transistors operate in saturation and are coupled to be insensitive to differential data signals on the wire pair, the current supplied to the PD load is substantially unaffected by the differential data signals. Negative feedback circuits in the gyrator reduce fluctuations in current through the gyrator due to differential data signals on the wire pair. No inductors are required in the gyrator. A PHY is AC-coupled to the wire pair via capacitors.

Abstract: A contactless charging system for smart garments having coils whose centroids are not colinear. Folding a coil in half through its centroid will null out its inductance. A smart garment having 3 coils that have centroids that are not colinear is proposed. Accordingly, there is no single folding line that intersects all 3 centroids thereby nullifying inductance. Power can be combined with one or more rectifiers such that power is not cancelled. The present disclosure is suitable for any charging environment or apparatus, such as, drawer or hanger.

Abstract: Embodiments of the present disclosure relate to various methods and example systems for carrying out analog-to-digital conversion of data acquired by arrays of nanogap sensors. The nanogap sensors described herein may operate as molecular sensors to help identify chemical species through electrical measurements using at least a pair of electrodes separated by a nanogap. In general, the methods and systems proposed herein rely on digitizing the signal as the signal is being integrated, and then integrating the digitized results. With such methods, the higher sample rate used in the digitizer reduces the charge per quantization and, therefore, the size of sampling capacitors used. Consequently, sampling capacitors may be made factors of magnitude smaller, requiring less valuable space on a chip compared to sampling capacitors used in conventional nanogap sensor arrays.

Abstract: Uniformly-sampled, residue-generating analog-to-digital converters (ADCs), such as uniformly-sampled continuous-time pipelined ADCs, suffer from over-ranging of the residue signal, which can lead to severe signal distortion. Conventionally, power consuming techniques and oversampling are used to address the over-ranging problem. To reduce the range of the residue signal and reduce other impairments, an event-driven sub-quantizer (sub-ADC) and a sub-digital-to-analog converter (sub-DAC) can be implemented in at least one of the stages of the residue-generating ADC, to generate a continuous-time residue signal.

Abstract: High voltage tolerant electrical overstress protection with low leakage current and low capacitance is provided. In one embodiment, a semiconductor die includes a signal pad, an internal circuit electrically connected to the signal pad, a power clamp electrically connected to an isolated node, and one or more isolation blocking voltage devices electrically connected between the signal pad and the isolated node. The one or more isolation blocking voltage devices are operable to isolate the signal pad from a capacitance of the power clamp. In another embodiment, a semiconductor die includes a signal pad, a ground pad, a high voltage/high speed internal circuit electrically connected to the signal pad, and a first thyristor and a second thyristor between the signal pad and the ground pad.

Abstract: A laser emitter circuit comprises a laser diode; a driver circuit configured to generate a drive signal; and a resonant circuit coupled to the driver circuit and the laser diode, wherein the resonant circuit is configured to use the drive signal of the driver circuit to generate a continuous wave sinusoidal drive signal to drive the laser diode.

Abstract: Isolators having a back-to-back configuration for providing electrical isolation between two circuits are described, in which multiple isolators formed on a single monolithic substrate are connect in series to achieve a higher amount of electrical isolation for a single substrate than for one of the isolators alone. A pair of isolators in the back-to-back configuration have top and bottom isolator components where the top isolator components are connected together and electrically isolated from the underlying substrate, resulting in floating top isolator components. The back-to-back isolator may provide one or more communication channels for transfer of information and/or power between different circuits.

Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to power semiconductor devices in which effects of charge trapping are compensated. A radio frequency (RF) power transmitter system comprises a RF power semiconductor device that outputs a time-varying gain characteristic from a RF signal input waveform originating from a digital input, wherein the time-varying gain characteristic includes a gain error associated with charge-trapping events having a memory effect on the RF power semiconductor device lasting longer than 1 microsecond. The RF power transmitter system further comprises circuitry configured to apply an analog gate bias waveform to the RF power semiconductor device based on the time-varying gain characteristic to reduce the gain error.

Abstract: Differential switching output stage for audio, power and digital data transmission can cause a common mode error due to asymmetric transition between positive and negative outputs. Systems and methods are provided for common mode error correction. In particular, summing nodes, novel error amps an edge switching can be used for common-mode feedback (CMFB) in differential signaling and other applications.

Abstract: Systems and methods are provided for increasing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters. In some examples, systems and methods are provided for reducing total capacitance in an embedded excess loop delay compensation digital-to-analog converter (DAC) in a quantizer for a continuous time delta-sigma ADC. In other examples, the excess loop delay compensation DAC can be a current domain DAC, a charge domain DAC, or a voltage domain DAC. Additionally, methods are provided for digitally controlling the gain of an excess loop delay DAC. Furthermore, methods are provided to calibrate a gain mismatch between a main successive approximation register DAC and an excess loop delay DAC. The systems and methods provided herein improve performance of continuous time delta-sigma ADCs. Continuous time delta-sigma ADCs are high precision and power efficient ADCs, often used in audio playback devices and medical devices.

Abstract: Systems and methods of monitoring electrodermal activity (EDA) in human subjects suitable for use in wearable electronic devices. An EDA monitoring system can include first and second dry electrodes, an alternating current (AC) excitation signal source, a trans-impedance amplifier, an analog-to-digital (A-to-D) converter, a discrete Fourier transform (DFT) processor, and a microprocessor. The AC excitation signal source can produce an AC excitation signal having a predetermined excitation frequency, such as about 100 or 120 Hertz (Hz). The analog-to-digital (A-to-D) converter can include a sample-and-hold circuit that operates at a predetermined sampling frequency, such as about four times (4×) the predetermined excitation frequency of 100 or 120 Hz. The DFT processor can generate complex frequency domain representations of digitized, sampled voltage level sequences provided by the A-to-D converter for use in obtaining measures of a user's skin impedance or skin conductance.

Abstract: Systems and methods are provided for architectures for a digital class D driver that increase the power efficiency of the class D driver. In particular, systems and methods are provided for a digital class D driver having a feedback analog-to-digital converter (ADC) that can have a latency of 1 cycle or more than 1 cycle. A feedback ADC with a latency of 1 cycle or more is significantly lower power than a low latency feedback ADC. Systems and methods are disclosed for a power efficient digital class D driver architecture that allows for a latency of one or more cycles in the feedback ADC.