Abstract: Single-axis teeter-totter accelerometers having a plurality of anchors are disclosed. The plurality of anchors may be arranged about a rotation axis of the teeter-totter proof mass. Each of the plurality of anchors may be coupled to the proof mass by two torsional springs each extending along the rotation axis. The plurality of anchors allows an increased number of torsional springs to be coupled to the proof mass and thus greater torsional stiffness for the proof mass may be achieved. Due to the higher torsional stiffness, the disclosed single-axis teeter-totter accelerometers may be deployed in high-frequency environments where such increased torsional stiffness is required, for example, around 20 kHz and above.

Abstract: A receiver for a light detection and range finding system is disclosed. The receiver can include an optoelectrical device to receive a pulse of light reflected from a target and to convert the pulse of light to a current pulse. The receiver can also include a transimpedance amplifier (TIA) to convert the current pulse to a voltage pulse. The receiver can also include a tunable filter that has an input coupled to an output of the TIA. The tunable filter can have a frequency response that is adjustable. The TIA and the tunable filter can be disposed on a single integrated circuit (IC) die.

Abstract: A PoDL system that uses a center-tapped transformer, for galvanic isolation of the PHY, has AC-coupling capacitors in series between the transmission wires and the transformer's secondary windings for blocking DC voltages generated by a PSE power supply. The center tap is conventionally connected to ground. As a result, one capacitor sees the full VPSE voltage across it, and the other capacitor sees approximately 0 V across it. Since the effective value of a ceramic capacitor significantly reduces with increasing DC bias voltages across it, the effective values of the capacitors will be very different, resulting in unbalanced data paths. This can lead to conversion of common mode noise and corrupt the data. To avoid this, a resistor divider is used to generate VPSE/2, and this voltage is applied to the center tap of the transformer. Therefore, the DC voltage across each capacitor is approximately VPSE/2, so their values remain equal.

Abstract: An integrated circuit (IC) die having a first side and a second side opposite the first side is disclosed. The IC die can include a signal via through the IC die. The IC die can include processing circuitry. The IC die can include transition circuitry providing electrical communication between the processing circuitry and the signal via. The transition circuitry can comprise a first transmission line, a second transmission line, and a transition transmission line between the first and second transmission lines. In various embodiments, the first transmission line can comprise a microstrip (MS) line, and the second transmission line can comprise a grounded coplanar waveguide (CPW).

Abstract: The present disclosure relates to integrated circuits which include various structural elements designed to reduce the impact of strain on the electronic components of the circuit. In particular, a combination of trenches and cavities are used to mechanically isolate the integrated circuit from the surrounding substrate. The trenches may be formed such that they surround the integrated circuit, and the cavities may be formed under the integrated circuit. As such, the integrated circuit may be formed on a portion of the substrate that forms a platform. In order that the platform does not move, it may be tethered to the surrounding substrate. By including such mechanical elements, variation in the electrical characteristics of the integrated circuit are reduced.

Abstract: Techniques are described for calibrating sensors for use in systems in the presence of offset. Sensors may be used to generate sense signals which represent true signals that are part of a system. When the sensors are not calibrated, inefficiency due to offset can be introduced into a system that incorporates the generated sense signal. Flipping techniques may be used to mitigate offset. Applicant has appreciated that when the sensor gains are mismatched, the offset calibration associated with a sensor is not independent from the offset calibration associated with the other sensors. Some of the flipping techniques described herein account for gain mismatch by flipping the polarity of each sensor in a one-at-a-time fashion, and by combining the results in a common system of equations to determine the gain mismatch and the offset of each sensor.

Abstract: Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

Abstract: Digital to analog converter generates an analog output corresponding to a digital input by controlling DAC cells using bits of the digital input. The DAC cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the DAC cells may have duty cycle error or mismatches. To compensate for the duty cycle error of a DAC cell, a small amount of charge is injected into a low-impedance node of a DAC cell when the data signal driving the DAC cell transitions, or changes state. The small amount of charge is generated using a capacitive T-network, and the polarity of the charge injected is opposite of the error charge caused by duty cycle error. The opposite amount of charge thus compensates or cancels out the duty cycle error, and duty cycle error present at the output of the DAC cell is reduced.

Abstract: Disclosed herein are systems and techniques for serial peripheral interface (SPI) functionality for node transceivers in a two-wire communication bus. For example, in some embodiments, a node transceiver may include SPI circuitry and upstream or downstream transceiver circuitry. SPI commands received via the SPI circuitry may be executed by the node transceiver, or transmitted upstream or downstream along the two-wire bus for execution by another node transceiver or a slave device coupled to another node transceiver.

Abstract: Charge pumps with accurate output current limiting are provided herein. In certain embodiments, a charge pump includes an output terminal for providing a regulated output voltage, a switched capacitor, and switches that control connectivity of the switched capacitor to selectively charge or discharge the switched capacitor. The switches are operable in two or more phases including a charging phase in which the switched capacitor is charged with a charging current and a discharging phase in which the switched capacitor is coupled to the output terminal. The charge pump further includes an output current limiting circuit that controls the charging current to limit an amount of output current delivered by the charge pump to the output terminal. The output current limiting circuit limits the output current based on comparing a reference signal to an integral of an observation current that changes in relation to the charging current.

Abstract: An electronic module can include a first integrated device package comprising a first substrate and an electronic component mounted to the first substrate. A first vertical interconnect can be mounted to and electrically connected to the first substrate. The first vertical interconnect can extend outwardly from the first substrate. The electronic module can include a second integrated device package comprising a second substrate and a second vertical interconnect having a first end mounted to and electrically connected to the second substrate. The second vertical interconnect can have a second end electrically connected to the first vertical interconnect. The first and second vertical interconnects can be disposed between the first and second substrates.

Abstract: Disclosed herein are systems and techniques for audio and lighting control in a bus system. For example, in some embodiments, a bus system may be configured for operation as a light organ and/or to generate sound effects based on accelerometer data.

Abstract: Systems and methods are provided for circuit configurations that maintain audio playback performance while reducing power consumption. In particular, a gain for a current analog-to-digital converter in an audio playback path is adjusted based on an amplitude of the input signal. Additionally, systems and methods are provided for transitioning between a modes of operation for large signals and mode of operation for small signals.

Abstract: Techniques for fabricating low-loss magnetic vias within a magnetic core are provided. According to some embodiments, vias with small, well-defined sizes may be fabricated without reliance on precise alignment of layers. According to some embodiments, a magnetic core including a low-loss magnetic via can be wrapped around conductive coils of an inductor. The low-loss magnetic vias can improve performance of an inductive component by improving the quality factor relative to higher loss magnetic vias.

Abstract: A bipolar junction transistor is provided with a multilayer collector structure. The layers of the collector are individually grown in separate epitaxial growth stages. For a PNP transistor, each layer, after it is grown, is doped with a p-type dopant in a dedicated implant stage. By providing separate epitaxial growth stages and separate dopant implant stages for each layer of the collector, the dopant concentration profile in the collector region can be better controlled to optimize the speed and breakdown voltage of a bipolar junction transistor.

Abstract: Herein disclosed are multiple embodiments of a signal-processing circuit that may be utilized in various circuits, including conversion circuitry. The signal-processing circuit may receive an input and produce charges on multiple different capacitors during different phases of operation based on the input. The charges stored on two or more of the multiple different capacitors may be utilized for producing an output of the signal-processing circuit, such as by combing the charges stored on two or more of the multiple different capacitors. Utilizing the charges on the multiple different capacitors may provide for a high level of accuracy and robustness to variations of environmental factors, and/or a low noise level and power consumption when producing the output.

Abstract: Aspects of this disclosure relate to systems and methods for calibration of antenna arrays. The calibration may be based on determining a reference value for the beamformer derived from measurements of phase and/or amplitude for each channel within the beamformer. The measurements of phase and/or amplitude can be stored in non-volatile memory. Using a difference between the reference value and the measured values for each channel, a portion of a global configuration table may be copied to each channel's memory. Each channel can be separately calibrated based on the portion of the global configuration table copied to the local memory of each channel.

Abstract: Devices and methods that aim to improve flicker noise rejection in switched-capacitor (SC) integrators are disclosed. An example SC integrator includes a first and a second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. By adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at every clock cycle of a master clock and by keeping the time distance/delay between those samples relatively small regardless of the master clock frequency, such a SC integrator may provide improvements in terms of rejecting the flicker noise of the amplifier.

Abstract: Embodiments may relate to an electronic device that includes a processor communicatively coupled with a hardware accelerator. The processor may be configured to identify, based on an indication of a priority level in a task control block (TCB), a location at which the TCB should be inserted in a queue of TCBs. The hardware accelerator may perform jobs related to the queue of TCBs in an order related to the order of TCBs within the queue. Other embodiments may be described or claimed.

Abstract: An embodiment of a communication circuit for communicating data across an isolation barrier may include an input circuit to receive a plurality of input data channels, a framing circuit to frame an input data packet from the plurality of input data channels, an encoding circuit to select a characteristic of a data symbol to represent a plurality of bits of the framed input data packet, and a driver circuit to drive one or more data symbols representing the framed input data packet onto an isolator configured to communicate data across the isolation barrier. The encoding circuit may select an amplitude, frequency or phase of the data symbol from a plurality of predetermined amplitudes, frequencies or phases, to encode the plurality of bits as the selected amplitude, frequency or phase.