Abstract: A duty cycled voltage reference circuit is turned on and off synchronously with the operation of a second, reference-consuming, duty-cycled circuit to which it supplies a reference. When the reference consuming circuit no longer has need of the reference, the voltage reference circuit itself is then also powered down. The reference circuit is then powered back up for the next duty cycle sufficiently in advance of the reference consuming circuit such that any auto-zeroing and noise filtering operations required by the reference circuit are complete and a stable reference voltage is output at least simultaneously with, or slightly before, the reference consuming circuit begins to make use of the voltage reference signal. In this manner, synchronous duty-cycled operation of the voltage reference circuit with the reference-consuming circuit is obtained, with the consequence that power consumption by the reference circuit is reduced.

Abstract: Random chopping is an effective technique for data converters. Random chopping can calibrate offset errors, calibrate offset mismatch in interleaved ADCs, and dither even order harmonics. However, the non-idealities of the (analog) chopper circuit can limit its effectiveness. If left uncorrected, these non-idealities cause severe degradation in the noise floor that defeats the purpose of chopping, and the non-idealities may be substantially worse than the non-idealities that chopping is meant to fix. To address the non-idealities of the random chopper, calibration techniques can be applied, using correlators and calibrations that may already be present for the data converter. Therefore, the cost and digital overhead are negligible. Calibrating the chopper circuit can make the chopping more effective, while relaxing the design constraints imposed on the analog circuitry.

Abstract: Low noise amplifiers (LNAs) with output limiting are provided herein. In certain implementations, a gallium nitride (GaN) LNA includes LNA amplification circuitry and an output limiter that is connected to an output of the LNA amplification circuitry and operable to limit an output power of the GaN LNA. By limiting the output signal power, a number of benefits are achieved, including protection of downstream circuitry receiving the GaN LNA's output signal. For example, such downstream circuitry can be fabricated using silicon or other fabrication technology associated with a lower signal power handling capability relative to that of the GaN LNA.

Abstract: A method of performing analog-to-digital conversion using a successive approximation (SAR) analog-to-digital converter (ADC). A previous digital output is compared to a range based on the first M bits of the previous digital output. If the previous digital output is within that range, a digital-to-analog converter (DAC) of the SAR ADC is preloaded with the first M bits of the previous digital output, prior to commencing bit trials. If the previous digital output is outside of that range, an offset is applied to the first M bits of the previous digital output and the DAC is preloaded based on the M bits and the offset, prior to performing bit trials. This method reduces the possibility of the next input being outside of a further range defined by the preload.

Abstract: Distributed switches to suppress transient electrical overstress-induced latch-up are provided. In certain configurations, an integrated circuit (IC) or semiconductor chip includes a transient electrical overstress detection circuit that activates a transient overstress detection signal in response to detecting a transient electrical overstress event between a pair of power rails. The IC further includes mixed-signal circuits and latch-up suppression switches distributed across the IC, and the latch-up suppression switches temporarily clamp the power rails to one another in response to activation of the transient overstress detection signal to inhibit latch-up of the mixed-signal circuits.

Abstract: Disclosed herein are systems and techniques for slave-to-slave communication in a multi-node, daisy-chained network. Slave nodes may provide or receive upstream or downstream data directly to/from other slave nodes, without the need for data slots first to route through the master node.

Abstract: Sense amplifiers for use in connection with microelectromechanical system (MEMS) gyroscopes are described. The sense amplifiers may be configured to change the level of a gyroscope signal, i.e., the signal produced by a gyroscope in response to angular motion, to a level suitable for processing circuitry arranged to infer the angular velocity. The sense amplifier may further provide a DC discharge path allowing for discharge of the DC component of the output signal. The DC discharge path may include an anti-aliasing filter and a resistive circuit. The anti-aliasing filter may filter the output signal to maintain the resistive circuit in the linear region. The anti-aliasing filter may be designed with a frequency response such that discrete frequency sub-bands are blocked or at least attenuated. The frequency sub-bands may be tuned to substantially match the gyroscope's resonant frequency and its integer multiples.

Abstract: Data isolators for providing isolation between two ports that enable dynamic communication are described. The dynamic communication may be achieved by varying a ratio of the data rate relative to a clock frequency of a clock signal. The data isolator may include a first circuit that transmits data across an isolation barrier when the clock signal is in a first state and a second circuit that transmits data across the isolation barrier when the clock signal is in a second state. The clock frequency may be variable and, as a result, change the duration of data transmissions in a given clock cycle. For example, the clock frequency may be reduced to increase the number of bits transmitted per clock cycle and, conversely, increased to reduce the number of bits transmitted per clock cycle. Thus, the number of bits transmitted per clock cycle may be adjusted to suit the situation.

Abstract: An interface circuit to an electromagnetic flow sensor is described. In an example, it can provide a DC coupled signal path from the electromagnetic flow sensor to an analog-to-digital converter (ADC) circuit. Examples with differential and pseudo-differential signal paths are described. Examples providing DC offset or low frequency noise compensation or cancellation are described. High input impedance examples are described. Coil excitation circuits are described, such as can provide on-chip inductive isolation between signal inputs and signal outputs. A switched mode power supply can be used to actively manage a bias voltage of an H-Bridge, such as to boost the current provided by the H-Bridge to the sensor coil during select time periods, such as during phase shift time periods of the coil, which can help reduce or minimize transient noise during such time periods.

Abstract: Subject matter herein can include identifying a biochemical test strip assembly electrically, such as using the same test circuitry as can be used to perform an electrochemical measurement, without requiring use of optical techniques. The identification can include using information about a measured susceptance of an identification feature included as a portion of the test strip assembly. The identification can be used by test circuitry to select test parameters or calibration values, or to select an appropriate test protocol for the type of test strip coupled to the test circuitry. The identification can be used by the test circuitry to validate or reject a test strip assembly, such as to inhibit use of test strips that fail meet one or more specified criteria.

Abstract: Techniques for duplex communication and power transfer across an isolator are provided. In an example, a first transceiver coupled to a first side of an isolator can include a transmit modulator configured to receive first data and timing signals, to provide control signals to oscillate an output of the transceiver to transmit power and to order each half-cycle of an oscillation cycle of the output to transmit the first data. A second transceiver coupled to a second side of the isolator can include a receive detection circuit configured to compare a received oscillation cycle with a plurality of thresholds and to provide a plurality of comparator outputs indicative of reception of the positive half-cycle and the negative half-cycle, and a receive decoder configured to identify the order of half-cycles and to provide an output indicative of logic level of the first data.

Abstract: A power amplifier circuit for broadband data communication over a path in a communication network can reduce or avoid gain compression, provide low distortion amplification performance, and can accommodate a wider input signal amplitude range. A dynamic variable bias current circuit can be coupled to a common emitter bias node of a differential pair of transistors to provide a dynamic variable bias current thereto as a function of an input signal amplitude of an input signal. Bias current is increased when input signal amplitude exceeds a threshold voltage established by an offset or level-shifting circuit. The frequency response of the bias current circuit can track the frequency content of the input signal. A delay in the signal path to the differential pair can phase-align the bias current to the amplification by the differential pair. A dynamic variable supply voltage can be based on an envelope of the input signal.

Abstract: A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively “holds” or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.

Abstract: A network authentication system with dynamic key generation that facilitates the establishment of both endpoint identity, as well as a secure communication channel using a dynamically-generated key between two end devices (potentially on separate local area networks). An interactive or non-interactive authentication protocol is used to establish the identity of the target end device, and dynamic key generation is used to establish a shared symmetric session key for creating an encrypted communication channel between the end devices.

Abstract: A power conversion apparatus or system can be configured to receive a high voltage alternating current (AC) signal at an input and to provide in dependence thereon a low voltage direct current (DC) signal from an output stage. The power conversion apparatus can include a main path comprising a high voltage capacitor in series with the input. In an example, the capacitor comprises a portion of an electric field energy harvesting system.

Abstract: A system and method of reducing data-rate requirements of fronthauls for wireless communication is disclosed. In one aspect, the system includes a baseband processing unit and a remote radio head remotely located from the baseband processing unit. The remote radio head is configured to transmit and receive communication signals with the baseband processing unit. The system can also include a fronthaul configured to provide a communication channel between the baseband processing unit and the remote radio head for the communication signals, and a matched filter configured to filter out redundant information from the communications signals before the communications signals are provided to the fronthaul.

Abstract: Analog circuits are often non-linear, and the non-linearities can hurt performance. Designers would trade off power consumption to achieve better linearity. An efficient and effective calibration technique can address the non-linearities and reduce the overall power consumption. A dither signal injected to the analog circuit can be used to expose the non-linear behavior in the digital domain. To detect the non-linearities, a counting approach is applied to isolate non-linearities independent of the input distribution. The approach is superior to and different from other approaches in many ways.

Abstract: One embodiment is an apparatus including a detector circuit electrically coupled between a signal source and a second circuit, the signal source generating a first signal, the detector circuit detecting a level of the first signal and generating a first control signal when the detected level of the first signal exceeds a first threshold value, and a clamping switch electrically coupled to receive the first control signal from the detector circuit, the clamping switch including a multi-terminal active device. The first control signal controls a state of the clamping switch such that the clamping switch clamps a level of a signal applied to the second circuit when the level of the first signal exceeds the first threshold value.

Abstract: The present disclosure addresses thermal issues in a multi gate finger field-effect transistor (FET) by providing a multi-gate finger FET arrangement where the respective distances between the multiple gate fingers are modulated along the device, such that the distances between the gate fingers in or towards the middle of the device are greater than the distances between the gate fingers at the or towards the edge of the device. By providing the greater distances between gate fingers located in or towards the middle of the device then improved thermal management properties are obtained, and the device as a whole is maintained cooler than would otherwise be the case, with associated improvements in device lifetimes.

Abstract: In a teeter-totter type MEMS accelerometer, the teeter-totter proof mass and the bottom set of electrodes (i.e., underlying the proof mass) are formed on a device wafer, while the top set of electrodes (i.e., overlying the teeter-totter proof mass) are formed on a circuit wafer that is bonded to the device wafer such that the top set of electrodes overlie the teeter-totter proof mass. The electrodes formed on the circuit wafer may be formed from an upper metallization layer on the circuit wafer, which also may be used to form various electrical connections and/or bond pads.