Abstract: Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.

Abstract: Various embodiments of a compact sensor module are disclosed herein. The sensor module can include a stiffener and a sensor substrate wrapped around a side of the stiffener. A sensor die may mounted on the sensor substrate. A processor substrate may be coupled to the sensor substrate. A processor die may be mounted on the processor substrate and may be in electrical communication with the sensor die.

Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring. An integrated circuit device includes a core circuit and a wear-out monitor device. The wear-out monitor device configured to adjust an indication of wear out of the core circuit regardless of whether the core circuit is activated The integrated circuit further includes a sensing circuit coupled to the wear-out monitor device and configured to detect an electrical property of the wear-out monitor device that is indicative of a wear-out level of the core-circuit.

Abstract: Techniques that allow application of noise-shaped dither without applying dither at sampling, resulting in the analog-to-digital converter (ADC) circuit advantageously being balanced during acquisition. Balancing the ADC circuit at acquisition can reduce the risk of sampling digital interferences that can couple in through the references or substrates.

Abstract: An analog front end (AFE) system for substantially eliminating quantization error or noise can combine an input of an integrator circuit in the AFE system with an input of the digital-to-analog converter (DAC) circuit in the feedback loop of the AFE system. By combining the input of the integrator with the input of the DAC circuit in the feedback loop, the in-band quantization noise of the filter can be substantially eliminated, thereby improving measurement accuracy.

Abstract: To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

Abstract: Device for optically detecting smoke and implementing thereof. Apparatus and methods for detecting the presence of smoke in a small, long-lasting smoke detector are disclosed. Specifically, the present disclosure shows how to build a very compact housing around the smoke detector while keeping the reflections from the housing structure to a very low value while satisfying all the other peripheral needs of fast response to smoke and preventing ambient light. This allows very small measurements of light scattering of the smoke particles to be reliable in a device resistant to the negative effects of dust. In particular, geometrical optical elements, e.g., cap and optical defection elements, are disclosed.

Abstract: Device for optically detecting smoke and implementing thereof. Apparatus and methods for detecting the presence of smoke in a small, long-lasting smoke detector are disclosed. Specifically, the present disclosure shows how to build a very compact housing around the smoke detector while keeping the reflections from the housing structure to a very low value while satisfying all the other peripheral needs of fast response to smoke and preventing ambient light. This allows very small measurements of light scattering of the smoke particles to be reliable in a device resistant to the negative effects of dust.

Abstract: A device comprising: a physical unclonable function (PUF) device configured to generate an output value based on hardware characteristics of the PUF device; and a processor connected to the PUF device, the processor configured to: execute a cryptographic operation in a sequence of ordered stages including a first stage and a second stage, the executing comprising: in the first stage: recovering a first secret value based on a first output value obtained from the PUF device; executing a first sub-operation using the first secret value; and removing unobscured values from memory prior to execution of a subsequent stage; in the second stage: recovering a second secret value based on a second output value obtained from the PUF device; and executing a second sub-operation using the second secret value to enable execution of a cryptographic operation encoded with at least the first secret value and the second secret value.

Abstract: Embodiments of the present disclosure provide ADCs particularly suitable for PDAF image sensors, which ADCs may have an increased speed and/or reduced design complexity and power consumption compared to conventional implementations. An example ADC for a PDAF image sensor is configured to implement modified SAR techniques which reduce the number of bit trials required for conversion, and enable increased number of samples in a row-conversion time period of the image sensor. The ADC may implement the modified SAR techniques in combination with CMS in pixel readout signal chain, which may reduce noise without a proportionate increase in ADC sample rate.

Abstract: A system having two or more sensing nodes coupled to a control node using a serial communication channel having separate transmit and receive circuits, where each sensing node includes an ADC circuit and a microcontroller, operation of the ADC circuit in each sensing node is concurrently synchronized by the control node using the transmit circuit (e.g., with respect to the control node) of the serial communication channel. The control node can synchronize operation of two or more ADC circuits in separate sensing nodes without using shared clocks or other control signals.

Abstract: An LC filter circuit reduces an output voltage ripple of a switching power supply using coupled inductors in combination with a capacitor to form a notch filter, and aligning the notch region of the notch filter with a ripple frequency of the switching power supply to attenuate the frequency region of the fundamental ripple frequency by a larger amount than other frequencies.

Abstract: Various examples are directed to a digital predistortion (DPD) circuit comprising a DPD actuator circuit, a DPD feedback frequency-shaping filter, a basis matrix generator circuit, a basis matrix frequency-shaping filter, and a DPD adaption circuit. The DPD actuator circuit may generate a predistorted signal based at least in part on an input signal and a set of frequency-shaped DPD parameters. The DPD feedback frequency-shaping filter may filter a DPD feedback signal to generate a frequency-shaped DPD feedback signal. A passband of the DPD feedback frequency-shaping filter may include substantially all of a bandwidth of the input signal and exclude a distortion term outside the bandwidth of the input signal. The basis matrix generator may generate a basis matrix based at least in part on a power amplifier feedback signal The basis matrix frequency-shaping filter may generate a frequency-shaped basis matrix based at least in part on the basis matrix.

Abstract: A multi-input analog-to-digital converter (ADC), i.e., a single ADC, can receive multiple analog input signals and generate multiple digital outputs. To combine multiple analog input signals into a single multi-input ADC, the multi-input ADC would typically include multiple track and hold (T/H) circuits and an adder, which can consume a significant amount of power and incur large cost overhead. An improved approach is to combine multiple inputs through a unique T/H circuit in the front-end of the ADC. The multiple analog input signals can be aggregated using code sequences, without requiring a significant amount of external circuits.

Abstract: An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.

Abstract: Various embodiments provide methods of determining the quality factor of a resonating body in ways that are advantageous over previously known methods. For example, embodiments allow the determination of the quality factors of a resonating body without preventing the simultaneous use of the resonating body. For micromachined (“MEMS”) devices, embodiments allow the determination of the quality factors of a resonating body in a manner that is not dependent on transduction parameters of the MEMS device.

Abstract: A difference amplifier circuit can be used to amplify a differential input signal representative of a current flowing through a current sensing element, such as a resistor. In certain applications, a common mode voltage established at an input of the difference amplifier circuit can be greater in magnitude than a supply voltage provided to the difference amplifier circuit. A component of the differential input signal, such as one polarity of the differential signal, can be used to power the difference amplifier circuit. Such powering of the difference amplifier by the component of the differential input signal can be performed selectively, such as when a magnitude of the common mode voltage exceeds the supply voltage or another specified threshold. In this manner, a common mode input voltage capability can be greater in magnitude than a magnitude of a supply input voltage provided to an integrated circuit including the difference amplifier circuit.

Abstract: Techniques are provided for compensating gain of a combined amplifier and analog-to-digital converter (ADC) circuit, for example, due to additional filtering added to an input of the circuit. In an example, an integrated circuit including an amplifier and ADC can include an amplifier circuit configured to receive an input signal and to amplify the input signal based on an input resistance and a feedback resistance, and to provide an amplified representation of the input signal, and an ADC circuit configured to receive an output of the amplifier, to determine a digital coefficient associated with an additional input resistance coupled to the amplifier, and to provide a compensated digital representation of the amplified representation of the input signal using the digital compensation coefficient.

Abstract: Apparatus and methods for rotary traveling wave oscillators (RTWOs) are provided herein. In certain configurations, an RTWO includes a differential transmission line connected in a ring and a plurality of segments distributed around the ring. The segments include metal stubs extending from the RTWO's differential transmission line. The metal stubs aid in providing access to additional layout resources for tuning capacitors and other circuitry of the RTWO's segments, while permitting the length of RTWO's ring to be relative short. Thus, the metal stubs do not inhibit the RTWO from operating with relatively high oscillation frequency, while providing connectivity to tuning capacitors that tune the RTWO's oscillation frequency over a wide tuning range and/or provide fine frequency step size.

Abstract: Shortening any of the operational phases of a noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC), including the acquisition phase, the bit trial phase, and the residue charge transfer phase, can result in higher power, and it can be difficult to achieve high speed at low power. Using various techniques described, the acquisition, bit-trial, and residue charge transfer phases of two or more digital-to-analog converter (DAC) circuits of an ADC circuit can be time-interleaved. The use of two or more DAC circuits can increase or maximize the time available for the acquisition, bit-trial, and residue charge transfer phases.