Abstract: Activity monitors and smart watches utilizing optical measurements are becoming widely popular, and users expect to get an increasingly accurate estimate of their heart rate (HR) from these devices. These devices are equipped with a light source and an optical sensor which enable estimation of HR using a technique called photoplethysmography (PPG). One of the main challenges of HR estimation using PPG is the coupling of motion into the optical PPG signal when the user is moving randomly or exercising. The present disclosure describes a computationally feasible and fast HR estimation algorithm to be executed at instances of little or no motion. Resulting HR readings may be useful on their own, or be provided to systems that monitor HR continuously to prevent the problem of such systems being locked on an incorrect HR for long periods of time. Implementing techniques described herein leads to more accurate HR measurements.

Abstract: An integrated ion-sensitive probe is provided. In an example, an ion-sensitive probe can include a semiconductor substrate and a first passive electrode attached to the semiconductor substrate. The first passive electrode can be configured to contact a solution and to provide a first electrical voltage as function of a concentration of an ion within the solution. In certain examples, a passive reference electrode can be co-located on the semiconductor substrate. In some examples, processing electronics can be integrated on the semiconductor substrate.

Abstract: Clock systems with phase noise compensation are provided herein. In certain implementations, a clock system includes a phase noise detector for detecting a phase noise of a clock signal, and an adjustable delay circuit for generating an adjusted clock signal based on delaying the clock signal with a controllable delay. Additionally, the phase noise detector generates an error signal indicated the phase noise of the clock signal, and controls the delay of the adjustable delay circuit with the error signal over time to thereby compensate the clock signal for phase noise. Thus, the adjusted clock signal has reduced phase noise compared to the clock signal.

Abstract: System and techniques for an occupancy sensor are described herein. Images from a camera can be received. Here, the camera has a certain a field of view. A proximity indicator from a proximity detector can be received when an object enters the field of view. The images from the camera are processed to provide an occupancy indication. A first technique is used for the occupancy indication in the absence of the proximity indicator and a second technique is used otherwise.

Abstract: Integrated digital isolators comprise a first transformer coil or capacitor plate mounted on an integrated circuit substrate, and separated from a second transformer coil or capacitor plate via an electrically insulating isolation layer. The electrical isolation that is achieved is dependent upon the material and thickness of the isolation layer. In order to reduce the amount of time required for fabrication while still allowing thick isolation layers to be deployed, in examples of the disclosure pre-formed sheets or tapes of dielectric material are applied to the substrate over the first transformer coil or capacitive plate, for example by being rolled onto the substrate using a heated roller. Such a technique results in a thick isolation layer that is formed using a simple process and much more quickly and reliably than conventional spin-coating or deposition techniques.

Abstract: An integrated device package is disclosed. The package can include a carrier, such as first integrated device die, and a second integrated device die stacked on the first integrated device die. The package can include a buffer layer which coats at least a portion of an exterior surface of the first integrated device die and which is disposed between the second integrated device die and the first integrated device die. The buffer layer can comprise a pattern to reduce transmission of stresses between the first integrated device die and the second integrated device die.

Abstract: As a PUF device ages, the response characteristics of the device change. Thus, mappings made on the original PUF outputs can drift and become invalid. Re-enrollment or re-mapping of hidden values to PUF response characteristics can resolve the changing nature of the PUF. Unfortunately, an adversary may tamper with the PUF during re-enrollment compromising security of the PUF. Accordingly, techniques of securely and remotely re-enrolling a PUF device are described. During an initial enrollment of the PUF device, multiple sets of enrollment values of the PUF device can be generated. For remote re-enrollment, a first initial set of enrollment values can be used to authenticate the PUF device. Upon authentication using the first initial set, the PUF device can re-enroll the PUF device and account for changes in PUF characteristics. A second set of initial enrollment values can then be used to verify that the PUF device is unaltered.

Abstract: In an example, a circuit for controlling at least two electronic switches in a parallel configuration between a power supply and a load. The circuit includes a control circuit to generate first and second control signals to control first and second electronic switches of the at least two electronic switches, and establish a conduction sequence of the first and second electronic switches using the first and second control signals. The circuit includes a detection circuit configured to detect a current flowing through a control terminal of the first electronic switch during a transition portion, wherein the circuit is configured to adjust the first control signal and establish the second portion of the conduction sequence in response to the detected current.

Abstract: A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.

Abstract: Some or all of a comparator circuit of an analog-to-digital converter (ADC) circuit can be efficiently repurposed or reused for residue amplification for efficient noise-shaping, e.g., in a noise-shaping feedback configuration. A preamplifier portion of a comparator circuit in an oversampling ADC can be re-purposed to provide an amplifier to amplify or otherwise modify a residue left after the bit trials of a conversion cycle. The amplified or modified residue can then be used elsewhere, for example, for noise-shaping by applying a noise transfer function (NTF), a result of which can then be fed back (e.g., summed with the next sampled input at an input of the comparator circuit for use in the N bit trials of the next ADC cycle).

Abstract: A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.

Abstract: A microelectronic circuit having at least one component adjacent a carrier that is not a semiconductor or sapphire. The circuit includes a component bearing stack of one or more layers having one or more passive components, which are adjacent or bonded to the carrier. In certain embodiments, the circuit also includes an etch stop layer of a material having a slower etch rate than silicon and a bond layer bonding the carrier and the component bearing one or more layers.

Abstract: Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC would reconstruct the input signal to the stage using a feedforward digital to analog converter (DAC). Non-linearities in the DAC can directly affect the overall performance of the multi-step ADC. To reduce power consumption and complexity of analog circuit design, digital background calibration schemes are implemented to address the non-linearities. The non-linearities that the calibration schemes address can include reference, DAC, and quantization non-linearities.

Abstract: Improved track and hold (T/H) circuits can help analog-to-digital converters (ADCs) achieve higher performance and lower power consumption. The improved T/H circuits can drive high speed and interleaved ADCs, and the design of the circuits enable additive and multiplicative pseudo-random dither signals to be injected in the T/H circuits. The dither signals can be used to calibrate (e.g., linearize) the T/H circuits and the ADC(s). In addition, the dither signal can be used to dither any remaining non-linearity, and to calibrate offset/gain mismatches in interleaved ADCs. The T/H circuit design also can integrate an amplifier in the T/H circuit, which can be used to improve the signal-to-noise ratio (SNR) of the ADC or to act as a variable gain amplifier (VGA) in front of the ADC.

Abstract: This disclosure relates to data communication networks. An example data communication apparatus includes physical (PHY) layer circuitry that includes transceiver circuitry, decoder circuitry, and a signal analysis unit. The transceiver circuitry receives encoded data symbols via a network link. The received encoded data symbols are encoded using trellis coded modulation (TCM). The decoder circuitry decodes the received encoded data symbols using maximum-likelihood (ML) decoding to map a received symbol sequence to an allowed symbol sequence using a trace-back depth. A trace-back depth value is a number of symbols in the received symbol sequence used by the ML decoding to identify the allowed symbol sequence from the received symbol sequence. The signal analysis unit determines one or more link statistics of the network link, and sets the trace-back depth value according to the one or more link statistics.

Abstract: A device for controlling an electronic switch between a power supply and a load includes a sensing circuit to measure a current to the load and a control circuit to control operation of the electronic switch if the current exceeds a current limit. The control circuit includes a normal current circuit to output a first switch control current to the electronic switch and a boost current circuit to output a second switch control current to the electronic switch, the first switch control current being higher than the second switch control current.

Abstract: An embodiment of a communication system for transmitting and receiving data across an isolation barrier may include a communication circuit connected to an isolator at a first side of the isolation barrier, the communication circuit having a transmit circuit to drive a first data signal onto the isolator based on input data received by the communication circuit, a receive circuit to receive a second data signal from the isolator and produce output data based on the received second data signal, and a control circuit to control the transmit and receive circuits to provide time division multiplexing of the first and second data signals.

Abstract: Apparatus and methods for frequency tuning of rotary traveling wave oscillators (RTWOs) are provided herein. In certain configurations, distributed quantized tuning is used to tune a frequency of the RTWO. The RTWO includes a plurality of segments distributed around the RTWO's ring, and the segments include tuning capacitors and other circuitry. The distributed quantized frequency tuning is used to control the tuning capacitors in the RTWO's segments using separately controllable code values, thereby enhancing the RTWO's frequency step size or resolution. Moreover, in configurations including multiple RTWO rings that are locked to one another to reduce phase noise, the distributed quantized frequency tuning can be used to separately set the tuning capacitors across multiple RTWO rings that are coupled to one another.

Abstract: A charge injection compensation circuit compensates for charge injection by a field-effect transistor (FET) switch regardless of a supply voltage. The charge injection compensation circuit includes a main switch that injects charge into an electronic circuit when switched off, and a charge storage device that stores the injected charge until it can be dissipated to a dissipating node. Upon the main switch being controlled to switch off, a pulse generator circuit controls a charge storage switch to switch on to transfer the charge injected from the main switch to the charge storage device and then switch off. A dissipation circuit dissipates the charge from the charge storage device to a dissipating node.

Abstract: A system comprises a plurality of power supplies, wherein a power supply provides a supply voltage rail to a voltage domain of the system; a plurality of power supply voltage sequencer devices electrically coupled to multiple power supplies of the plurality of power supplies, wherein a voltage sequencer device is configured to activate the multiple power supplies in a specified sequence; and a bus electrically coupled to the plurality of power supply voltage sequencer devices, wherein the bus is configured to communicate state information of the plurality of power supply voltage sequencer devices.