Patents Assigned to Ando Electric Co., Ltd.
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Patent number: 6388473Abstract: A logic product circuit having a plurality of transistors arranged in a matrix; a plurality of input terminals; and a single output terminal. The transistors in each column are connected in a line, forming a transistor array, the transistor arrays are connected in parallel between the output terminal and the ground, each of the input terminals is connected to the inputs to the transistors in all the columns, and the transistors to which each input terminal is connected are arranged in different rows.Type: GrantFiled: June 27, 2000Date of Patent: May 14, 2002Assignee: Ando Electric Co., Ltd.Inventor: Kazuo Nakaizumi
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Patent number: 6388454Abstract: An electro-optic sampling prober is used to measure a waveform of a measured signal applied to wiring of an IC wafer. Herein, a laser radiates laser beams, which are supplied to an optical module containing an optical isolator and photodiodes by way of an optical fiber. Then, the laser beams pass through an optical wavelength filter to propagate through a prober unit. The laser beams are incident on an electro-optical element, which is changed in polarization state in response to an electric field being caused by the measured signal. The laser beams are reflected by a surface mirror of the electro-optical element, so that reflected beams propagate back through the prober unit and are returned to the optical module by way of the optical wavelength filter. During the measurement, a human operator watches an image of a selected portion of the IC wafer presently placed beneath the prober unit to adjust a positional relationship between the prober unit and IC wafer.Type: GrantFiled: November 30, 1999Date of Patent: May 14, 2002Assignees: Ando Electric Co., Ltd., Nippon Telegraph and Telephone CorporationInventors: Fumio Akikuni, Katsushi Ohta, Mitsuru Shinagawa, Tadao Nagatsuma, Junzo Yamada
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Publication number: 20020053921Abstract: The present invention provides a semiconductor test apparatus that can reduce the number of internal transfers of pattern files to a minimum. In the semiconductor test apparatus 11, the control unit 10 produces a pattern file use frequency table in the pattern file use frequency table memory 18, and in a set of test in which a predetermined number of semiconductors to be tested are tested, the use frequency of the pattern files is obtained. In addition, the control unit 1 again reads out the pattern files based on the frequency of use that has been obtained, and rearrange the pattern files in the executive memory 17. In addition, the control unit 10 deletes the pattern files in ascending order of the frequency of use when the capacity of the memory becomes insufficient.Type: ApplicationFiled: October 11, 2001Publication date: May 9, 2002Applicant: Ando Electric Co., Ltd.Inventor: Hiroshi Koshiba
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Patent number: 6384590Abstract: In a light receiving circuit for use in electro-optic sampling oscilloscope which receives first and second optical, photodiodes 51 and 52 are connected in series between a positive bias power supply 50P and a negative bias power supply 50N. The photodiodes 51 and 52 receive optical signals whose polarization state correspond to the voltage of a signal to be measured and convert the thus-received optical signals into electric signals. An amplifier 53 amplifies an electric current appearing in a point of connection P between the photodiodes 51 and 52. A current monitor 54 detects the electric signal converted by the photodiode 51, and a current monitor 57 detects the electric signal converted by the photodiode 52. The electric signal detected by the current monitor 54 is subjected to analog-to-digital conversion by an analog-to-digital converter 55, and the electric signal detected by the current monitor 57 is subjected to analog-to-digital conversion by an analog-to-digital converter 58.Type: GrantFiled: November 10, 1999Date of Patent: May 7, 2002Assignees: Ando Electric Co., Ltd., Nippon Telegraph and Telephone CorporationInventors: Jun Kikuchi, Nobuaki Takeuchi, Yoshiki Yanagisawa, Nobukazu Banjo, Yoshio Endou, Mitsuru Shinagawa, Tadao Nagatsuma, Junzo Yamada
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Publication number: 20020053059Abstract: A CRC encoding circuit for generating a CRC code in accordance with initial parallel data having remainder portion data in a last column of the initial parallel data, comprises: a first parallel encoding unit for generating a first CRC code in accordance with the initial parallel data other than the remainder portion data; a CRC code selector for selecting a second CRC code having predetermined number of bytes, from the first CRC code generated by the first parallel encoding unit; a parallel data selector for selecting second parallel data having the same number of bytes as the second CRC code, from the remainder portion data; and a second parallel encoding unit for generating a third CRC code in accordance with the second CRC code and the second parallel data.Type: ApplicationFiled: October 24, 2001Publication date: May 2, 2002Applicant: Ando Electric Co., Ltd.Inventors: Kiyomi Hara, Takao Inoue
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Publication number: 20020052989Abstract: A data processing apparatus and a data processing method easily realizable of a transparent processing of a high-speed serial data. The data processing apparatus (1) comprises: a serial data conversion section for converting serial data to predetermined set of parallel data; a transparent data information detection section (10) for detecting information concerning transparent data, from the parallel data; an effective byte number operation section for operating an effective byte number of the parallel data; a transparent data conversion section (20) for converting transparent data of the parallel data, and moving predetermined data after the transparent data forward, in the parallel data; an address control section (304) for determining addresses at which the parallel data are rearranged; and a data array section (30) for moving predetermined data to one predetermined set of parallel data from another predetermined set of parallel data.Type: ApplicationFiled: October 25, 2001Publication date: May 2, 2002Applicant: ANDO ELECTRIC CO., LTD.Inventors: Takehiro Yamamoto, Takao Inoue
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Patent number: 6381195Abstract: A circuit and a method for generating an address, which can generate a plurality of types of address on the basis of a reference address, and an apparatus for generating an address, which can generate the different addresses from one another by using a plurality of circuits described above at a plurality of steps. The circuit (200) for generating an address, comprises: a multiplex counter (30) comprising a counter (31) for counting a pulse number of a clock signal to generate a count number represented by binary bit and a bit shift circuit (33) for shifting the count number, to generate an output count number; and an arithmetic circuit (20) for operating an address signal on the basis of the output count number and a reference address signal, to output the address signal to a semiconductor memory as an object of test.Type: GrantFiled: December 20, 2000Date of Patent: April 30, 2002Assignee: Ando Electric Co., Ltd.Inventor: Junichiro Yamaguchi
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Publication number: 20020049942Abstract: An analog/digital characteristics testing device comprises: a plurality of measurement circuits for measuring an analog/digital characteristic of one or more ICs to be tested in accordance with a test condition data; and a setting unit for setting a different test condition data to each measurement circuit.Type: ApplicationFiled: October 16, 2001Publication date: April 25, 2002Applicant: ANDO ELECTRIC CO., LTD.Inventor: Teruyoshi Kawai
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Publication number: 20020049945Abstract: An IC test system comprises: a test pattern signal applying section for applying a test pattern signal to an IC to be tested, in accordance with a test program; a simulation section for simulating an operation of the test pattern signal applying section in accordance with a simulation program; and a management device which is connected detachably with the test pattern signal applying section, for managing the operation of the test pattern signal applying section and an operation of the simulation section in accordance with a management program, for storing information about each operation of the test pattern signal applying section and the simulation section, and for managing one of the information about the operation of the simulation section and the information about the operation of the test pattern signal applying section in accordance with the other information.Type: ApplicationFiled: September 5, 2001Publication date: April 25, 2002Applicant: ANDO ELECTRIC CO., LTDInventor: Shintaro Mori
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Patent number: 6377036Abstract: The present invention relates to an electro-optic sampling oscilloscope. The delay circuit in the electro-optic sampling oscilloscope comprises a delay time detecting circuit, a regulation time determining circuit, a counter circuit and a delay regulating circuit. The delay time detecting circuit detects in the trigger signal a value corresponding to the delay time of a reference clock from a reference clock generating circuit. The regulation time determining circuit determines a regulation time based on the value detected by the delay time detecting circuit so that the regulation time is an integer multiple of the reference clock. The counter circuit is triggered by the trigger signal to count the reference clock through a specific value. The delay regulating circuit employs a signal related to the regulation time from the regulation time determining circuit, to delay the signal output from the counter circuit by the regulation time.Type: GrantFiled: October 6, 1998Date of Patent: April 23, 2002Assignees: Ando Electric Co., Ltd., Nippon Telegraph and Telephone CorporationInventors: Nobuaki Takeuchi, Yoshiki Yanagisawa, Jun Kikuchi, Yoshio Endou, Mitsuru Shinagawa, Tadao Nagatsuma, Kazuyoshi Matsuhiro
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Publication number: 20020043987Abstract: The present invention allows reducing the power consumption, reducing the amount of heat generation, improving the frequency characteristics, and reducing noise superposition. A control circuit 25 supplies to a control circuit 5 a control signal CS 1 that indicates the setting voltage of a DUT 9 as a control signal CS 8. In addition, the control circuit 25 controls switching power sources 21 and 22 and the polarity control circuits 23 and 24 depending on control signals CS 4 to CS 7 such that the voltage drop amount of the control elements 6 and 7 becomes a value sufficient to operate the control elements 6 and 7 based on a control signal CS 1 and a detected signal DS2 that is fed back from the DUT 9. The control circuit 5 controls the control elements 6 and 7 depending on the control signal CS 8.Type: ApplicationFiled: July 23, 2001Publication date: April 18, 2002Applicant: Ando Electric Co., Ltd.Inventor: Nobuaki Takeuchi
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Publication number: 20020043979Abstract: A semiconductor testing apparatus capable of displaying its measurement results in an easily understandable manner is provided. The apparatus comprises a display section for displaying a measurement result of a change in time of a voltage distribution on a measurement plane of a measured device and an input section for entering parameters for the display of the measurement result. When a measurement time is entered as a parameter, the display section displays the measurement result by means of a three-dimensional graph and a representation in numerals, letters or symbols of the measurement time. The graph shows along its three axes a first coordinate in a first direction on the measurement plane, a second coordinate in a second direction which is perpendicular to the first direction, and a voltage at the measurement time at a position on the measurement plane defined by the first and second coordinates.Type: ApplicationFiled: July 24, 2001Publication date: April 18, 2002Applicant: Ando Electric Co., Ltd.Inventor: Nobuaki Takeuchi
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Publication number: 20020044474Abstract: The invention provides a structure that does not employ complicated and large-scale control circuits or control memory, minimizes the circuits for real time processing, and allows the use of refresh memory. The invention provides a test clock 8-1 comprising a data processing apparatus 1-1 provided for each electrode pin of the measured device 11, a memory 2-1 that carries out reading and writing of the test pattern data and the like, a first-in-first-out element 4-1 that executes queue processing of the data read out from the memory, a delay circuit 5-1 that delays the output signal of the first-in-first-out element, and a measured device driver 6-1 that inputs into the electrode pin the output signal of the delay circuit, and in which the data processing apparatus 1-1 of adjacent test blocks are connected into a loop via the input-output circuit 3-1.Type: ApplicationFiled: July 26, 2001Publication date: April 18, 2002Applicant: Ando Electric Co., Ltd.Inventor: Nobuaki Takeuchi
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Patent number: 6369562Abstract: An electro-optical probe used for an oscilloscope (e.g., electro-optic sampling oscilloscope) is mainly constructed by a probe head and a probe unit. The probe head contains a metal pin and an electro-optical element having a reflector at its terminal surface. The probe unit contains a reduced number of optical parts, which are arranged such that an optical axis of incoming beams of the electro-optical element differs from a optical axis of outgoing beams of the electro-optical element. That is, laser beams output form a laser diode are subjected to convergence by a converging lens to produce converged beams, which are incident on the electro-optical element as its incoming beams. The incoming beams are subjected to reflection by the reflector to produce reflected beams, which are output from the electro-optical element as its outgoing beams. Then, the reflected beams are converted to parallel beams by a collimator lens, or they are converged by a converging lens.Type: GrantFiled: November 23, 1999Date of Patent: April 9, 2002Assignees: Ando Electric Co., Ltd., Nippon Telegraph and Telephone CorporationInventors: Akishige Ito, Katsushi Ohta, Toshiyuki Yagi, Mitsuru Shinagawa, Tadao Nagatsuma, Junzo Yamada
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Patent number: 6369852Abstract: An analytical system for moving picture regeneration is capable of ascertaining an appropriate method of improving the quality of a moving picture by executing satisfactory analysis of the state of moving picture regeneration. With the analytical system for moving picture regeneration, moving picture codes are decoded and regenerated by respective regeneration units. Thereupon, in each of the regeneration units, occurrence of picture freeze is detected by information subunits for picture freeze occurrence, a throughput is detected by throughput monitoring subunits, and delay in input time of the respective moving picture codes is detected by input-time information subunits and sent out to a display unit. Further, a SNR value is computed on the basis of a restored moving picture and a reference moving picture by respective SNR computation units, and a sum of the throughputs of the respective regeneration units is obtained by a total throughput monitoring unit, and sent out to the display unit.Type: GrantFiled: September 24, 1999Date of Patent: April 9, 2002Assignee: Ando Electric Co., Ltd.Inventor: Yoshizou Honda
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Publication number: 20020039022Abstract: A calibration device for a semiconductor testing apparatus, comprises: an inspection section comprising an inspector for detecting an inspection reference portion provided on a calibration board mounted on the semiconductor testing apparatus; a movement section for moving the inspector to an optional position of an upper surface of the calibration board, and for moving the inspector vertically in the optional position of the upper surface of the calibration board; and a control unit for setting an inspection line passing through the inspection reference portion, for controlling the inspector so as to move the inspector along the set inspection line to detect the inspection reference portion, for determining a center coordinate of the inspection reference portion in accordance with a middle coordinate of a range that the inspection reference portion is detected along the set inspection line, and for compensating a coordinate of a measurement position of the calibration board in accordance with the determined cType: ApplicationFiled: September 10, 2001Publication date: April 4, 2002Applicant: Ando Electric Co., Ltd.Inventor: Keiji Yamamoto
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Patent number: 6366348Abstract: The present invention provides an optical fiber distortion measuring apparatus and optical fiber distortion measuring method which make it possible to measure the amount of distortion of an optical fiber efficiently and in a short period of time. The time change waveform when a light pulse having a frequency of &ngr;1 is applied is compared with initial data (the time change waveform obtained in a case in which there is no distortion). Then, the light intensity L1 at a position Dx at which the light intensities do not agree is obtained. Next, the time change waveform is measured when a light pulse having a frequency of &ngr;2 is applied, and the light intensity L2 at position Dx is obtained. After this, the loss (resulting from distortion) in light intensities L1 and L2 is corrected, and light intensities LC1 and LC2 are obtained.Type: GrantFiled: April 18, 2000Date of Patent: April 2, 2002Assignees: Ando Electric Co., Ltd., Nippon Telegraph and Telephone CorporationInventors: Yasushi Sato, Haruyoshi Uchiyama, Toshio Kurashima
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Patent number: 6359620Abstract: A display controlling device comprises; a display for displaying a data to be displayed in a display field, an input part for scrolling the display field, and a display field shift control unit for shifting the display field in one direction so that when the display field is scrolled in another direction to display the data to be displayed, the whole data to be displayed is displayed in the display field.Type: GrantFiled: September 14, 1999Date of Patent: March 19, 2002Assignee: Ando Electric Co., Ltd.Inventor: Tatsuyuki Fujita
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Patent number: 6356220Abstract: An A/D converting device comprises; a plurality of A/D converters connected in parallel with each other, for carrying out a converting operation a plurality of numbers of times, in which an analog signal is converted into a digital data, a selecting circuit for selecting each A/D converter from the plurality of A/D converters at each sampling timing during the converting operation to sample the converted digital data, a selecting circuit controlling unit for controlling the selecting circuit so that when one A/D converter is selected at one sampling timing during the Nth converting operation, another A/D converter is selected at the one sampling timing during the (N+1)th converting operation, an adding circuit for integrating the digital data sampled at the one sampling timing during each converting operation, and a processing unit for processing the integrated digital data.Type: GrantFiled: September 28, 1999Date of Patent: March 12, 2002Assignee: Ando Electric Co., LTDInventor: Tatsuhiko Takatsu
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Publication number: 20020021137Abstract: The method for calibrating a semiconductor testing device, comprises the steps of: changing a beam emitted from a light source into a linear beam; sending the linear beam through an electro optic element provided above a target device onto a measuring line on the target device; detecting a variation in polarization of the beam reflected from the measuring line; calculating an electric field distribution or a voltage distribution on the measuring line of the target device based on the variation in polarization; and moving a calibrating device, which produces an electric field from a predetermined point, to specify a measurable point or range.Type: ApplicationFiled: June 25, 2001Publication date: February 21, 2002Applicant: Ando Electric Co., Ltd.Inventor: Nobuaki Takeuchi