Abstract: Metal stacks and methods of depositing a metal stack on a semiconductor substrate are disclosed. The metal stack is formed by depositing a tungsten (W) layer on the semiconductor substrate and depositing a molybdenum (Mo) layer on the tungsten (W) layer. The tungsten (W) layer has a thickness in a range of from 5 ? to 30 ? and the molybdenum (Mo) layer has a thickness in a range of from 80 ? to 200 ?. In some embodiments, the metal stack has a resistivity of less than or equal to 10 ??-cm prior to treatment and a resistivity of less than or equal to 11 ??-cm after treatment when the metal stack has a total thickness of 140 ?.

Abstract: The present technology includes vertical cell array transistor (VCAT) with improved gate induced leakage current. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where at least one word includes a first section adjacent to the source/drain region and a second section adjacent to the gate region, where the second section contains a high work function material and the first section contains a low work function material.

Abstract: Exemplary semiconductor structures may include a stack of layers overlying a substrate. The stack of layers may include a first portion of layers, a second portion of layers overlying the first portion of layers, and a third portion of layers overlying the second portion of layers. The first portion of layers, the second portion of layers, and the third portion of layers may include alternating layers of a silicon oxide material and a silicon nitride material. One or more apertures may be formed through the stack of layers. A lateral notch in each individual layer of silicon nitride material at an interface of the individual layer of silicon nitride material and an overlying layer of silicon oxide material may extend a distance less than or about 100% of a distance corresponding to a thickness of the individual layer of silicon nitride material.

Abstract: Provided herein are approaches for angle control of neutral reactive species ion beams. In one approach, a workpiece processing apparatus may include a plasma source operable to generate a plasma within a plasma chamber enclosed by a chamber housing, and an extraction plate coupled to the chamber housing. The extraction plate may include a recombination array having a plurality of channels operable to direct one or more radical beams to a workpiece at a non-zero angle relative to a perpendicular extending from a main surface of the workpiece.

Abstract: Methods of forming an oxide layer over a semiconductor substrate are provided. The method includes forming a first oxide containing portion of the oxide layer over a semiconductor substrate at a first growth rate by exposing the substrate to a first gas mixture having a first oxygen percentage at a first temperature. A second oxide containing portion is formed over the substrate at a second growth rate by exposing the substrate to a second gas mixture having a second oxygen percentage at a second temperature. A third oxide containing portion is formed over the substrate at a third growth rate by exposing the substrate to a third gas mixture having a third oxygen percentage at a third temperature. The first growth rate is slower than each subsequent growth rate and each growth rate subsequent to the second growth rate is within 50% of each other.

Abstract: Embodiments provided herein generally include apparatus, plasma processing systems and methods for generation of a waveform for plasma processing of a substrate in a processing chamber. One embodiment includes a waveform generator having a voltage source circuitry, a first switch coupled between the voltage source circuitry and a first output node of the waveform generator, the first output node being configured to be coupled to a chamber, and a second switch coupled between the first output node and electrical ground node. The waveform generator also includes a third switch coupled between the voltage source circuitry and a second output node of the waveform generator, the second output node being configured to be coupled to the chamber, and a fourth switch coupled between the second output node and the electrical ground node.

Abstract: Methods of depositing thin films of hafnium oxide possessing strong ferroelectric properties are described. A hafnium oxide monolayer is formed in a first process cycle comprising sequential exposure of a substrate to a hafnium precursor, purge gas, first oxidant and purge gas. A doped hafnium oxide monolayer is formed in a second process cycle comprising sequential exposure of the substrate to a hafnium precursor, purge gas, dopant precursor, purge gas, second oxidant and purge gas. Thin films of hafnium oxide are also described.

Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

Abstract: Described herein is a method for selectively cleaning and/or etching a sample. The method includes selectively forming a film in a trench of a substrate such that the trench may be selectively etched. A polymer film is deposited on the bottom surface of the trench without being deposited on the side wall. A second film is selectively formed in the trench without forming the second film on the polymer film. The polymer is then removed from the bottom surface of the trench and then etching is performed on the bottom surface of the trench using an etch chemistry, wherein the second film protects the side wall from being etched.

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

Abstract: During chemical mechanical polishing of a substrate, a signal value that depends on a thickness of a layer in a measurement spot on a substrate undergoing polishing is determined by a first in-situ monitoring system. An image of at least the measurement spot of the substrate is generated by a second in-situ imaging system. Machine vision processing, e.g., a convolutional neural network, is used to determine a characterizing value for the measurement spot based on the image. Then a measurement value is calculated based on both the characterizing value and the signal value.

Abstract: An electronic device manufacturing system configured to receive, by a processor, input data reflecting a feature related to a manufacturing process of a substrate. The manufacturing system is further configured to generate a characteristic sequence defining a relationship between at least two manufacturing parameters, and determine a relationship between one or more variables related to the feature and the characteristic sequence. The manufacturing system is further configured to determine a weight based on the determined relationship and apply the weight to the feature. The manufacturing system is further configured to train a machine-learning model in view of the weighted feature.

Abstract: A showerhead with an embedded nut is disclosed. The showerhead comprises an embedded nut within a cavity. The nut may be engaged by a bolt through an opening in the cavity to support the showerhead. The apparatus allows for the support of the showerhead without the potential for metal contamination.

Abstract: A polishing pad for a chemical mechanical polishing apparatus includes a polishing layer having a polishing surface and a backing layer formed of a fluid-permeable material. The backing layer includes a lower surface configured to be secured to a platen and an upper surface secured to the polishing layer, wherein the lower surface and upper surface are sealed. A first seal circumferentially seals an edge of the backing layer, and a second seal seals and separates the backing layer into a first region and a second region surrounded by the first region.

Abstract: A transistor device includes a channel region, a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region, a gate structure disposed on the channel region, the first source/drain region and the second source/drain region, and an interlayer dielectric (ILD) structure disposed on the gate structure. The ILD structure includes a first dielectric layer including a first set of sublayers. The first set of sublayers includes a first sublayer including a first dielectric material having a first hydrogen concentration and a second sublayer including the first dielectric material having a second hydrogen concentration lower than the first hydrogen concentration. The ILD structure further includes a second dielectric layer including a second set of sublayers. The second set of sublayers includes a third sublayer including a second dielectric material different from the first dielectric material.

Abstract: Embodiments of the present disclosure generally relate to apparatus and methods for semiconductor processing, more particularly, to a thermal process chamber. In one or more embodiments, a process chamber comprises a first window, a second window, a substrate support disposed between the first window and the second window, and a motorized rotatable radiant spot heating source disposed over the first window and configured to provide radiant energy through the first window.

Abstract: Variable orifice valves comprising a first fixed plate, a second fixed plate and a movable plate between are described. The movable plate is connected to the first fixed plate and the second fixed plate by sealing elements. The movable plate is moved closer to or further from the first fixed plate by rotation of an actuator ring that rotates at least two rotary elements connected to the movable plate. A needle on the movable plate engages an opening in the valve to seal or open the valve to allow fluid flow. Methods of controlling flow of fluid through the variable orifice valve are also described.

Abstract: An ion implanter, including an ion source generating an ion beam, a set of beamline components directing the ion beam to a substrate along a beam axis, normal to a reference plane, a process chamber housing the substrate to receive the ion beam, and a conoscopy system. The conoscopy system may include: an illumination source directing light to a substrate position, a first polarizer assembly, comprising a first polarizer element and first pair of lenses, disposed on opposite sides of the first polarizer element, and arranged to focus the light at the substrate position; a second polarizer assembly, disposed to receive the light after passing through the substrate position, including a second polarizer element and a second pair of lenses disposed on opposite sides of the second polarizer element, and arranged to focus the light at a sensor, disposed in a detector plane of a detector.

Abstract: The present technology includes vertical cell array transistor (VCAT) that include a bit line arranged in a first horizontal direction and a word line arranged in a second horizontal direction. The arrays include a channel extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit line intersects with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the channels have at least one source/drain region and a channel body disposed between the first end and the second end. Arrays include where the channel body has a thickness that is greater than or about 5% less than a thickness of at least a portion of the at least one source/drain region.

Abstract: Exemplary semiconductor processing methods may include providing a boron-and-halogen-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of metal-containing hardmask material may be disposed on the substrate. A layer of silicon-containing material may be disposed on the layer of metal-containing hardmask material. The methods may include forming plasma effluents of the boron-and-halogen-containing precursor and the oxygen-containing precursor. The methods may include contacting the substrate with the plasma effluents of the boron-and-halogen-containing precursor and the oxygen-containing precursor. The contacting may etch a feature in the layer of metal-containing hardmask material. The contacting may form a layer of passivation material on sidewalls of the feature in the layer of metal-containing hardmask material.