Abstract: Semiconductor components and systems having substrate contacting surfaces with a reduced hardness are provided. Systems and components include a ceramic, metallic, or non-metallic component for contacting a substrate. Systems and components include a layer of coating material on at least a portion of a substrate contacting surface of the component. Systems and components include where the component for contacting a substrate includes a component Vickers hardness value, and the layer of coating material exhibits a coating layer Vickers hardness value. Systems and components include where the coating layer Vickers hardness value is greater than or about 10% less than the component Vickers hardness value.

Abstract: A vibrating actuator adapted to be installed within a component of an ion implanter, the vibrating actuator including a housing defining an internal cavity, and a vibrating mechanism disposed within the internal cavity, the vibrating mechanism including an actuating element and a vibratory element coupled to the actuating element, wherein when an electrical signal is applied to the actuating element, the actuating element moves the vibratory element to vibrate the housing.

Abstract: Processing chambers, substrate supports, centering wafers and methods of center calibrating wafer hand-off are described. A centering wafer comprises a disc-shaped body having a top surface and a bottom surface defining a thickness, a center, an outer edge having an outer peripheral face, a first arc-shaped slit and a second arc-shaped slit. Embodiments of the disclosure advantageously provide the ability to use the centering wafer to monitor and control backside pressure and thereby determine the center of a substrate support prior to processing the centering wafer. The centering wafer may be centered at a plurality of different angles by rotating the centering wafer.

Abstract: Methods and apparatus for processing substrates are provided herein. In some embodiments, a process kit for a substrate support includes: an upper edge ring made of quartz and having an upper surface and a lower surface, wherein the upper surface is substantially planar and the lower surface includes a stepped lower surface to define a radially outermost portion and a radially innermost portion of the upper edge ring.

Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing the substrate surfaces to a blocking compound to selectively form a blocking layer on at least a portion of the first surface over the second surface. The substrate is sequentially exposed to a metal precursor with a kinetic diameter in excess of 21 angstroms and a reactant to selectively form a metal-containing layer on the second surface over the blocking layer or the first surface. The relatively larger metal precursors of some embodiments allow for the use of blocking layers with gaps or voids without the loss of selectivity.

Abstract: Embodiments described and discussed herein generally relate to flexible or foldable display devices, and more specifically to flexible cover lens assemblies. In one or more embodiments, a flexible cover lens assembly contains a glass layer, an adhesion promotion layer on the glass layer, an anti-reflectance layer disposed on the adhesion promotion layer, a dry hardcoat layer having a nano-indentation hardness in a range from about 1 GPa to about 5 GPa and disposed on the anti-reflectance layer, and an anti-fingerprint coating layer disposed on the dry hardcoat layer.

Abstract: Embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The device includes a plurality of sub-pixels, each sub-pixel of the plurality of sub-pixels defined by adjacent pixel-defining layer (PDL) structures with inorganic overhang structures disposed on the PDL structures, each sub-pixel having an anode, organic light-emitting diode (OLED) material disposed on the anode, and a cathode disposed on the OLED material. The device is made by a process including the steps of: depositing the OLED material and the cathode by evaporation deposition, and depositing an encapsulation layer disposed over the cathode.

Abstract: A chemical mechanical polishing apparatus includes a platen to hold a polishing pad, a carrier to hold a substrate against a polishing surface of the polishing pad during a polishing process, and a temperature control system including a source of a fluid medium and one or more openings positioned over the platen and separated from the polishing pad and configured for the fluid medium to flow onto the polishing pad to heat or cool the polishing pad.

Abstract: A chemical mechanical polishing assembly includes a chemical mechanical polishing system, a fluid source, and a fluid delivery conduit to carry a fluid from the fluid source into the chemical mechanical polishing system. The polishing system has a platen to support a polishing pad, a carrier head to support a substrate and bring the substrate into contact with the polishing pad, and a motor to cause relative motion between platen and the carrier head. The fluid delivery conduit includes a conductive wire extending through an interior of the conduit to flow electrostatic discharge to a ground, and a wire extraction fitting covering and sealing a location where the conductive wire passes through a wall of the fluid delivery conduit.

Abstract: Embodiments described herein provide substrate support assemblies for retaining a surface of a substrate having one or more devices disposed on one or more surfaces of the substrate without contacting the one or more devices and preventing changes in profile of the substrate. The substrate support assembly allows for control of the substrate. The substrate support assembly includes a gas nozzle disposed through a body of the substrate support assembly. The gas nozzle provides a gas to the substrate. The gas is operable to provide pressure to the substrate to reduce contact on the substrate and to control the profile of the substrate.

Abstract: In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.

Abstract: Embodiments described and discussed herein generally relate to flexible or foldable display devices, and more specifically to flexible cover lens assemblies. In one or more embodiments, a flexible cover lens assembly contains a glass layer, an adhesion promotion layer on the glass layer, an anti-reflectance layer disposed on the adhesion promotion layer, a dry hardcoat layer having a nano-indentation hardness in a range from about 1 GPa to about 5 GPa and disposed on the anti-reflectance layer, and an anti-fingerprint coating layer disposed on the dry hardcoat layer.

Abstract: A method and apparatus for spatially switching radio frequency (RF) power from a single RF power generator to a selected one of two or more impedance matching networks coupled to associated RF electrodes for forming plasma in a plasma chamber. Full RF power may be switched within microseconds to the selected one of the two or more impedance matching networks. The two or more impedance matching networks may be coupled to one or more plasma generating electrodes. The two or more impedance matching networks may be interleaved during plasma processing recipe operation. Impedance matching networks can alternate back and forth during operation of a plasma processing recipe. This interleaving in operation and impedance transformation capabilities may also be performed with more than two impedance matching networks, and may be beneficial in enabling the use of fixed tuned impedance matching networks instead of requiring variable impedance matching networks having variable tuning capabilities.

Abstract: Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to the formation of the plurality of features, and depositing a stress compensation film along the second main side of the substrate, wherein a stress and a thickness of the stress compensation film is determined based on the amount of distortion to the substrate. The method may further include directing ions to the stress compensation film in an ion implant procedure.

Abstract: Chemical deliver conduits, systems for substrate processing and methods for supplying a chemical to a substrate processing chamber are described. The conduit has a length and connects a vessel containing the chemical to the substrate processing chamber. The conduit comprises an outer channel surrounding an inner channel. The outer channel is in fluid communication with source of a heat transfer fluid, and the inner channel is in fluid communication with the vessel containing the chemical.

Abstract: Techniques to dynamically tune components of an ion implanter are described. A method includes generating a first histogram for a first setting parameter of an ion implanter and a second histogram for a second setting parameter of the ion implanter. The histograms comprise a graphical representation of a distribution of data points across a range of values for each setting parameter. The method includes presenting the histograms on a user interface, receiving a control directive to modify a first range of values for the first setting parameter, predicting a modification to a second range of values for the second setting parameter based on the modification to the first range of values by a machine learning model, and presenting the second histogram for the second setting parameter to indicate the modification to the second range of values for the second setting parameter. Other embodiments are described and claimed.

Abstract: A a method of stress management in a substrate. The method may include providing a stress compensation layer on a main surface of the substrate; and performing a chained implant procedure to implant a set of ions into the stress compensation layer. The chained implant procedure may include directing a first implant procedure to the substrate, the first implant procedure generating a first damage profile within the stress compensation layer; directing a second implant to the substrate, different from the first implant, wherein a composite damage profile is generated within the stress compensation layer after the second implant, the composite damage profile resulting in a higher stress response ratio than the first damage profile.

Abstract: Semiconductor processing chambers and systems, as well as methods of cleaning such chambers and systems are provided. Processing chambers and systems include a chamber body that defines a processing region, a liner positioned within the chamber body that defines a liner volume, a faceplate positioned atop the liner, a substrate support disposed within the chamber body, and a cleaning gas source coupled with the liner volume through a cleaning gas plenum and one or more inlet apertures. Systems and chambers include where at least one of the one or more inlet apertures is disposed in the processing region between the faceplate and a bottom wall of the chamber body.

Abstract: Metal stacks and methods of depositing a metal stack on a semiconductor substrate are disclosed. The metal stack is formed by depositing a tungsten (W) layer on the semiconductor substrate and depositing a molybdenum (Mo) layer on the tungsten (W) layer. In one method, a tungsten (W) capping layer is deposited on the molybdenum (Mo) layer, followed by formation of a nitride capping layer on the tungsten (W) capping layer). In a second method, a nitride capping layer is formed on the molybdenum (Mo) layer using an ammonia free process. Both processes result in the formation of a metal stack having low resistivity.

Abstract: Thicker hardmasks are typically needed for etching deeper capacitor holes in a DRAM structure. Instead of increasing the hardmask thickness, hardmasks may instead be formed with an increased etch selectivity relative to the underlying semiconductor structure. For example, boron-based hardmasks may be formed that include a relatively high percentage of boron (e.g., greater than 90%). The etch selectivity of the hardmask may be improved by performing an ion implant process using different types of ions. The ion implant may take place before or after opening the hardmask with the pattern for the DRAM capacitor holes. Some designs may also tilt the semiconductor substrate relative to the ion implant process and rotate the substrate to provide greater ion penetration throughout a depth of the openings in the hardmask.