Abstract: Organometallic precursors and methods of depositing high purity metal films are discussed. Some embodiments utilize a method comprising exposing a substrate surface to an organometallic precursor comprising one or more of molybdenum (Mo), tungsten (W), osmium (Os), technetium (Tc), manganese (Mn), rhenium (Re) or ruthenium (Ru), and an iodine-containing reactant comprising a species having a formula RIx, where R is one or more of a C1-C10 alkyl, C3-C10 cycloalkyl, C2-C10 alkenyl, or C2-C10 alkynyl group, I is an iodine group and x is in a range of 1 to 4 to form a carbon-less iodine-containing metal film. Some embodiments advantageously provide methods of forming metal films having low carbon content (e.g., having greater than or equal to 95% metal species on an atomic basis), without using an oxidizing agent or a reductant.

Abstract: A method of processing a semiconductor substrate, including performing a first ion implantation process on the substrate, wherein a first ion beam formed of an ionized first dopant species is directed at a top surface of the substrate and is blocked from a first portion of the substrate while being allowed to implant a second portion of the substrate, and performing a second ion implantation process on the substrate, wherein a second ion beam formed of an ionized second dopant species is directed at the top surface of the substrate and is blocked from the first portion of the substrate while being allowed to implant the second portion of the substrate, wherein an effect of the second ion implantation process on an oxidation rate of the second portion counteracts an effect of the first ion implantation process on the oxidation rate of the second portion.

Abstract: Actual physical locations of dies on a substrate package may be identified without using a full metrology scan of the substrate. Instead, one or more cameras may be used to efficiently locate the approximate location of any of the alignment features based on their expected positioning in the design file for the packages are substrate. The cameras may then be moved to locations where alignment features should be, and images may be captured to determine the actual location of the alignment feature. These actual locations of the alignment features may then be used to identify coordinates for the dies, as well as rotations and/or varying heights of the dies on the packages. A difference between the expected location from the design file and the actual physical location may be used to adjust instructions for the digital lithography system to compensate for the misalignment of the dies.

Abstract: Exemplary methods of semiconductor processing include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A flowrate ratio of the hydrogen-containing precursor to the carbon-containing precursor may be maintained greater than or about 2:1. The methods include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C.

Abstract: Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.

Abstract: Embodiments described herein provide for optical devices with methods of forming optical device substrates having at least one area of increased refractive index or scratch resistance. One method includes disposing an etch material on a discrete area of an optical device substrate or an optical device layer, disposing a diffusion material in the discrete area, and removing excess diffusion material to form an optical material in the optical device substrate or the optical device layer having a refractive index greater than or equal to 2.0 or a hardness greater than or equal to 5.5 Mohs.

Abstract: Embodiments disclosed herein include a method of calibrating a processing tool. In an embodiment, the method comprises providing a first substrate with a first emissivity, a second substrate with a second emissivity, and a third substrate with a third emissivity. In an embodiment, the method may include running a recipe on each of the first substrate, the second substrate, and the third substrate, where the recipe includes a set of calibration attributes. In an embodiment, the method may further comprise measuring a layer thickness on each of the first substrate, the second substrate, and the third substrate. In an embodiment, the method further comprises determining if the layer thicknesses are uniform.

Abstract: Embodiments of the present disclosure relate to measurement systems and methods of measuring efficiency of optical devices. In one example, the measurement systems include a light source, a mirror, an illumination source, and a sensor. The light source provides a light beam to the optical device to be diffracted into diffraction beams having diffraction orders. The diffractions beams form a diffraction pattern. The method includes positioning the optical device in the measurement system and directing the diffraction beams to the sensor. The sensor is operable to measure the efficiency of the optical device by measuring the diffraction pattern.

Abstract: A substrate process station includes a housing including a transport region and process region. The process station further includes a magnetic levitation assembly disposed in the transport region configured to levitate and propel a substrate carrier. The magnetic levitation assembly includes a first track segment including first rails disposed in the transport region and below the process region, wherein the first rails each include a first plurality of magnets. The process station further includes a pedestal assembly comprising a pedestal disposed within the housing. The pedestal is moveable between a pedestal transfer position and a process position, wherein the pedestal is disposed between the first rails in the pedestal transfer position to receive a substrate from the substrate carrier, and wherein the pedestal is moveable between the first rails to position the received substrate in the process region in the process position.

Abstract: The present disclosure provides a multi-substrate handling system having an alignment apparatus capable of positioning each of a set of substrates in predetermined orientations for transfer. A buffer chamber is configured to receive and condition the set of substrates which are disposed on a substrate carrier. A first transfer assembly is configured to transfer the set of substrates to and from the buffer chamber and is capable of transferring each of the set of substrates from the alignment apparatus to the carrier in the buffer chamber. The carrier includes a plurality of modules capable of securing the set of substrates. The system includes a second transfer assembly having at least two robots configured to transfer the carrier of the set of substrates between the buffer chamber and a process chamber. The process chamber is capable of processing the set of substrates using different process parameters for each substrate.

Abstract: The present disclosure generally relates to photolithography systems, and methods for correcting positional errors in photolithography systems. When a photolithography system is first started, the system enters a stabilization period. During the stabilization period, positional readings and data, such as temperature, pressure, and humidity data, are collected as the system prints or exposes a substrate. A model is created based on the collected data and the positional readings. The model is then used to estimate errors in subsequent stabilization periods, and the estimated errors are dynamically corrected during the subsequent stabilization periods.

Abstract: Methods of treating a plasma showerhead comprise placing a showerhead comprising a faceplate and a plurality of gas openings PECVD substrate processing chamber having a process volume between the substrate support and the faceplate, and then exposing the showerhead to a silicon-containing precursor and a reactant gas so that the process volume and the gas openings are filled with the silicon-containing precursor and the reactant gas. The method includes introducing a first plasma in the PECVD substrate processing chamber to form a silicon oxide thin film or a silicon nitride thin film on the lower surface of the faceplate and lining the gas openings. A precursor-removing purge gas is flowed and a second plasma is struck to densify the thin film.

Abstract: Disclosed herein are systems and methods for high throughput angled ion processing. In one approach, a processing apparatus may include a chamber operable to contain a plasma, the chamber defined by a plurality of sidewalls, a first end wall, and a second end wall opposite the first end wall, an extraction assembly coupled to the second end wall, the extraction assembly comprising a plurality of apertures, wherein ions are extracted through the plurality of apertures are delivered to a substrate at a non-zero angle relative to a perpendicular extending from the substrate, and wherein the substrate is positioned external to the chamber. The processing apparatus may further include an actuator operable to shift the substrate relative to the moveable plates as the ions are extracted through the plurality of apertures.

Abstract: Exemplary semiconductor processing methods may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include a layer of a silicon-containing material. The silicon-containing material may be a silicon-and-carbon-containing material, a silicon-carbon-and-nitrogen-containing material, a silicon-and-nitrogen-containing material, a silicon-and-oxygen-containing material, or silicon material. The methods may include forming plasma effluents of the etchant precursor. The methods may include contacting the substrate with the plasma effluents of the etchant precursor. The contacting may etch a portion of the layer of the silicon-containing material. The processing region may be maintained at a cryogenic temperature while contacting the substrate with the plasma effluents of the etchant precursor.

Abstract: A pedestal may be configured to support a substrate during a semiconductor process. An electrostatic chuck (ESC) may include electrodes embedded in the pedestal that are configured to deliver a chucking volage to the pedestal during the semiconductor process. A power source coupled to an electrode may be configured to provide a signal having a frequency range to the electrode during the semiconductor process. A controller may be configured to receive a measurement of an impedance when the frequency range is applied to the electrode. The impedance measurements my then be used to determine a chucking state of the substrate, such as whether an airgap is present between the substrate and the pedestal during the semiconductor process.

Abstract: Choke plates and semiconductor manufacturing processing chamber incorporating the choke plates are described. The choke plates include an opening extending through the body with a plurality of angled apertures extending from a gas plenum within the body to the inner face of the opening. The plurality of angled apertures are angled from the gas plenum toward the top surface of the body.

Abstract: Wafers that begin as flat surfaces during a semiconductor manufacturing process may become warped or bowed as layers and features are added to an underlying substrate. This warpage may be detected between manufacturing processes by rotating the wafer adjacent to a displacement sensor. The displacement sensor may generate displacement data relative to a baseline measurement to identify areas of the wafer that bow up or down. The displacement data may then be mapped to locations on the wafer relative to an alignment feature. This mapping may then be used to adjust parameters in subsequent semiconductor processes, including adjusting how a carrier head on a polishing process holds or applies pressure to the wafer as it is polished. A model may be trained to provide control signals for a polishing/cleaning process, or to generate metrology data.

Abstract: An equipment front end module (EFEM) having walls, a first wall including one or more load ports and an EFEM chamber formed between the walls. The EFEM further includes an upper plenum at a top of the EFEM and including an opening into the EFEM chamber. Ducts provide a return gas flow path enabling recirculation of gas from the EFEM chamber to the upper plenum, the ducts proximate the one or more load ports. The one or more ducts includes flow elements configured to cause a low pressure condition at a location of the one or more load ports.

Abstract: A method of operating a set of dispatchers for a manufacturing facility, wherein each dispatcher of the set of dispatchers is a software application that makes dispatch decisions for the manufacturing facility based on facility data related to the manufacturing facility, includes identifying a first dispatcher of the set of dispatchers, wherein the first dispatcher is a non-initialized dispatcher, selecting, as an initialization partner, a second dispatcher of the set of dispatchers, and causing the first dispatcher to initiate a data retrieval process with the second dispatcher to retrieve, from the second dispatcher, an initial set of facility data related to the manufacturing facility.

Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.