Abstract: Embodiments of the present disclosure generally relate to the fabrication of integrated circuits and to apparatus for use within a substrate processing chamber to improve film thickness uniformity. More specifically, the embodiments of the disclosure relate to an edge ring. The edge ring may include an overhang ring.

Abstract: Embodiments of the present disclosure relate to apparatus, systems and methods for substrate processing. A detachable substrate support is disposed within a processing volume of a processing chamber and the substrate support includes a substrate interfacing surface and a back surface. The pedestal hub has a supporting surface removably coupled to the substrate support. A hub volume of the pedestal hub includes temperature measuring assembly disposed therein positioned to receive electromagnetic energy emitted from the back surface of the substrate support. The temperature measuring assembly measures an intensity of the electromagnetic energy entering the assembly and generates intensity signals. An apparent temperature of the substrate is determined based on the intensity signals.

Abstract: Exemplary substrate processing systems may include a plurality of processing regions. The systems may include a transfer region housing defining a transfer region fluidly coupled with the plurality of processing regions. The systems may include a plurality of substrate supports. Each substrate support of the plurality of substrate supports may be vertically translatable between the transfer region and an associated processing region of the plurality of processing regions. The systems may include a transfer apparatus including a rotatable shaft extending through the transfer region housing. The transfer apparatus may also include an end effector coupled with the rotatable shaft. The systems may include an exhaust foreline including a plurality of foreline tails. Each foreline tail of the plurality of foreline tails may be fluidly coupled with a separate processing region of the plurality of processing regions. The systems may include a plurality of throttle valves.

Abstract: Embodiments of the disclosure include a method of processing a substrate in a plasma processing system, comprising delivering an RF signal, by an RF generator, through an RF match to an electrode assembly disposed within the plasma processing system, wherein while delivering the RF signal the RF match is set to a first matching point, and delivering a voltage waveform, by a waveform generator, to the electrode assembly disposed within the plasma processing system while the RF signal is delivered to the electrode assembly.

Abstract: An electronic device manufacturing system capable of obtaining metrology data associated with a deposition process performed on a substrate according to a process recipe, wherein the deposition process generates a plurality of layers on a surface of the substrate. The manufacturing system can further obtain an expected profile associate with the process recipe, wherein the expected profile comprises a plurality of values indicative of a desired thickness for a plurality of layers of the process recipe. The manufacturing system can further generate a correction profile based on the metrology data and the expected profile, wherein the correction profile comprises a deposition time offset value for at least one layer of the plurality of layers. The manufacturing system can further generate an updated process recipe by applying the correction profile to the process recipe and cause a deposition step to be performed on the substrate according to the updated process recipe.

Abstract: A method for selective barrier metal etching includes performing a hydrogen implantation process, in an inductively coupled plasma (ICP) etch chamber, to chemically reduce an oxidized portion of a barrier metal layer formed within a feature in a metal layer on the barrier metal layer, and performing an etch process, in the ICP etch chamber, to remove the hydrogen implanted portion of the barrier metal layer.

Abstract: A cool cluster comprises one or more transfer chambers; a plurality of process chambers connected to the one or more transfer chambers; and a computing device of the tool cluster. The computing device is to receive first measurements generated by sensors of a first process chamber during or after a process is performed within the first process chamber; determine that the first process chamber is due for maintenance based on processing the first measurements using a first trained machine learning model; after maintenance has been performed on the first process chamber, receive second measurements generated by the sensors during or after a seasoning process is performed within the first process chamber; and determine that the first process chamber is ready to be brought back into service based on processing the second measurements using a second trained machine learning model.

Abstract: A method includes identifying first parameters of a first processing chamber of a semiconductor fabrication facility. The first parameters include first input parameters and first output parameters. The method further includes identifying second parameters of a second processing chamber of the semiconductor fabrication facility. The second parameters include second input parameters and second output parameters. The method further includes generating, by a processing device based on the first parameters and the second parameters, composite parameters comprising composite input parameters and composite output parameters. Semiconductor fabrication is based on the composite parameters.

Abstract: Metal stacks and methods of depositing a metal stack on a semiconductor substrate are disclosed. The metal stack is formed by depositing a tungsten (W) layer on the semiconductor substrate and depositing a molybdenum (Mo) layer on the tungsten (W) layer. The tungsten (W) layer has a thickness in a range of from 5 ? to 30 ? and the molybdenum (Mo) layer has a thickness in a range of from 80 ? to 200 ?. In some embodiments, the metal stack has a resistivity of less than or equal to 10 ??-cm prior to treatment and a resistivity of less than or equal to 11 ??-cm after treatment when the metal stack has a total thickness of 140 ?.

Abstract: Exemplary semiconductor structures may include a stack of layers overlying a substrate. The stack of layers may include a first portion of layers, a second portion of layers overlying the first portion of layers, and a third portion of layers overlying the second portion of layers. The first portion of layers, the second portion of layers, and the third portion of layers may include alternating layers of a silicon oxide material and a silicon nitride material. One or more apertures may be formed through the stack of layers. A lateral notch in each individual layer of silicon nitride material at an interface of the individual layer of silicon nitride material and an overlying layer of silicon oxide material may extend a distance less than or about 100% of a distance corresponding to a thickness of the individual layer of silicon nitride material.

Abstract: The present technology includes vertical cell array transistor (VCAT) with improved gate induced leakage current. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where at least one word includes a first section adjacent to the source/drain region and a second section adjacent to the gate region, where the second section contains a high work function material and the first section contains a low work function material.

Abstract: Provided herein are approaches for angle control of neutral reactive species ion beams. In one approach, a workpiece processing apparatus may include a plasma source operable to generate a plasma within a plasma chamber enclosed by a chamber housing, and an extraction plate coupled to the chamber housing. The extraction plate may include a recombination array having a plurality of channels operable to direct one or more radical beams to a workpiece at a non-zero angle relative to a perpendicular extending from a main surface of the workpiece.

Abstract: During chemical mechanical polishing of a substrate, a signal value that depends on a thickness of a layer in a measurement spot on a substrate undergoing polishing is determined by a first in-situ monitoring system. An image of at least the measurement spot of the substrate is generated by a second in-situ imaging system. Machine vision processing, e.g., a convolutional neural network, is used to determine a characterizing value for the measurement spot based on the image. Then a measurement value is calculated based on both the characterizing value and the signal value.

Abstract: A showerhead with an embedded nut is disclosed. The showerhead comprises an embedded nut within a cavity. The nut may be engaged by a bolt through an opening in the cavity to support the showerhead. The apparatus allows for the support of the showerhead without the potential for metal contamination.

Abstract: Embodiments provided herein generally include apparatus, plasma processing systems and methods for generation of a waveform for plasma processing of a substrate in a processing chamber. One embodiment includes a waveform generator having a voltage source circuitry, a first switch coupled between the voltage source circuitry and a first output node of the waveform generator, the first output node being configured to be coupled to a chamber, and a second switch coupled between the first output node and electrical ground node. The waveform generator also includes a third switch coupled between the voltage source circuitry and a second output node of the waveform generator, the second output node being configured to be coupled to the chamber, and a fourth switch coupled between the second output node and the electrical ground node.

Abstract: A polishing pad for a chemical mechanical polishing apparatus includes a polishing layer having a polishing surface and a backing layer formed of a fluid-permeable material. The backing layer includes a lower surface configured to be secured to a platen and an upper surface secured to the polishing layer, wherein the lower surface and upper surface are sealed. A first seal circumferentially seals an edge of the backing layer, and a second seal seals and separates the backing layer into a first region and a second region surrounded by the first region.

Abstract: A transistor device includes a channel region, a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region, a gate structure disposed on the channel region, the first source/drain region and the second source/drain region, and an interlayer dielectric (ILD) structure disposed on the gate structure. The ILD structure includes a first dielectric layer including a first set of sublayers. The first set of sublayers includes a first sublayer including a first dielectric material having a first hydrogen concentration and a second sublayer including the first dielectric material having a second hydrogen concentration lower than the first hydrogen concentration. The ILD structure further includes a second dielectric layer including a second set of sublayers. The second set of sublayers includes a third sublayer including a second dielectric material different from the first dielectric material.

Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

Abstract: Methods of depositing thin films of hafnium oxide possessing strong ferroelectric properties are described. A hafnium oxide monolayer is formed in a first process cycle comprising sequential exposure of a substrate to a hafnium precursor, purge gas, first oxidant and purge gas. A doped hafnium oxide monolayer is formed in a second process cycle comprising sequential exposure of the substrate to a hafnium precursor, purge gas, dopant precursor, purge gas, second oxidant and purge gas. Thin films of hafnium oxide are also described.

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).