Abstract: A system and method for fabricating a plurality of gate all around (GAA) complementary field effect transistors (CFETs). The fabrication method includes: fabricating a plurality of adjacent epitaxy layers, each of the plurality of epitaxy layers separated by a source/drain (S/D) canyon, each canyon defined by a sidewall of a first GAA CFET, and a sidewall of a second GAA CFET; depositing a dummy fill based on a target depth height into the S/D canyon; depositing a spacer cover on the sidewall of the first GAA CFET, and on the sidewall of the second GAA CFET; etching away the dummy fill to create a void in the S/D canyon; and depositing an isolator in the void at the target depth height.

Abstract: A system and method for forming an isolator in a complementary field effect transistor (CFET) is disclosed. In one aspect the method includes: fabricating a plurality of CFET devices, each device including a first metal-oxide-semiconductor (MOS) device and a second MOS device, wherein the first MOS device and the second MOS device are complementary; removing a filler between the first MOS device and the second MOS device of a first CFET device; depositing a dielectric material between the first CFET device and a second CFET device to fill a void between the first MOS device and the second MOS device of the first CFET device; etching the dielectric material; repeating the depositing and etching steps to fill the void between the first MOS device and the second MOS device of the first CFET device; and performing a final etching to remove the dielectric material between the first and second CFET.

Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in an organic light-emitting diode (OLED) display are described herein. The overhang structures are permanent to the sub-pixel circuit. The overhang structures include a conductive oxide. A first configuration of the overhang structures includes a base portion and a top portion with the top portion disposed on the base portion. In a first sub-configuration, the base portion includes the conductive oxide of at least one of a TCO material or a TMO material. In a second sub-configuration, the base portion includes a metal alloy material and the conductive oxide of a metal oxide surface. A second configuration of the overhang structures includes the base portion and the top portion with a body portion disposed between the base portion and the top portion. The body portion includes the metal alloy body and the metal oxide surface.

Abstract: Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a substrate support disposed within the chamber body. The substrate support may define a substrate support surface. The chambers may include a showerhead positioned supported atop the chamber body. The substrate support and a bottom surface of the showerhead may at least partially define a processing region within the semiconductor processing chamber. The showerhead may define a plurality of apertures through the showerhead. The bottom surface of the showerhead may define an annular groove or ridge that is positioned directly above at least a portion of the substrate support.

Abstract: Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include an adapter coupled with the remote plasma unit. The adapter may include a first end and a second end opposite the first end. The adapter may define an opening to a central channel at the first end, and the central channel may be characterized by a first cross-sectional surface area. The adapter may define an exit from a second channel at the second end, and the adapter may define a transition between the central channel and the second channel within the adapter between the first end and the second end. The adapter may define a third channel between the transition and the second end of the adapter, and the third channel may be fluidly isolated from the central channel and the second channel.

Abstract: Techniques for adjusting the shape of an ion beam are described. Characteristics of a desired beam shape may be defined. The ion beam generator may include beam shaping elements associated with tunable parameters that can be set in combination with each other. A search space for the possible combinations is defined. A set of exploratory points in the search space are measured and used to interpolate a large number of interpolated points based on a regression model. Interpolated points that are associated with low confidence values may be measured. Based on the measured and interpolated points, clusters of tunable parameter combinations may be identified for evaluation. The clusters are evaluated for stability and sensitivity, and one of the clusters is selected based on the evaluation. The ion beam generator may be configured based on the selected cluster.

Abstract: Embodiments of the present disclosure provide a multiple disk pad conditioner and methods of using the multiple disk pad conditioner during a chemical mechanical polishing (CMP) process. The multiple disk pad conditioner has a plurality of conditioning heads having conditioning disks affixed thereto. The multiple disk pad conditioner can include a conditioning arm, and a plurality of conditioning heads attached to the conditioning arm. Each of the plurality of conditioning heads has a conditioning disk affixed thereto. In some embodiments, each of the conditioning heads include a rotational axis, wherein each of the rotational axes is disposed a distance apart in a first direction that extends along the length of the conditioning arm.

Abstract: Embodiments presented herein are directed to radio frequency (RF) grounding in process chambers. In one embodiment, a dielectric plate is disposed between a chamber body and a lid of a process chamber. The dielectric plate extends laterally into a volume defined by the chamber body and the lid. A substrate support is disposed in the volume opposite the lid. The substrate support includes a support body disposed on a stem. The support body includes a central region and a peripheral region. The peripheral region is radially outward of the central region. The central region has a thickness less than a thickness of the peripheral region. A flange is disposed adjacent to a bottom surface of the peripheral region. The flange extends radially outward from an outer edge of the peripheral region. A bellows is disposed on the flange and configured to sealingly couple to the dielectric plate.

Abstract: Plasma showerheads with improved gas uniformity, and a plasma showerhead with angled gas nozzles are disclosed. Also disclosed are gas nozzles having a vertical offset angle and/or a directional offset angle. None of the gas channels and/or the gas nozzles intersect with the plasma regions of the showerhead.

Abstract: Embodiments include a plasma processing tool that includes a processing chamber, and a plurality of modular microwave sources coupled to the processing chamber. In an embodiment, the plurality of modular microwave sources include an array of applicators that are positioned over a dielectric body that forms a portion of an outer wall of the processing chamber. The array of applicators may be coupled to the dielectric body. Additionally, the plurality of modular microwave sources may include an array of microwave amplification modules. In an embodiment, each microwave amplification module may be coupled to at least one of the applicators in the array of applicators. According to an embodiment, the dielectric body be planar, non-planar, symmetric, or non-symmetric. In yet another embodiment, the dielectric body may include a plurality of recesses. In such an embodiment, at least one applicator may be positioned in at least one of the recesses.

Abstract: A method and apparatus for improving film growth uniformity on a semiconductor substrate. The film growth uniformity is improved by adjusting the amount of power provided to the substrate by spot heaters as the substrate is rotated. Therefore, the amount of power provided to the substrate by the spot heaters changes as the portion of the substrate being heated by spot heater changes. The change in power provided by the spot heater is dependent on a temperature correction factor applied by the controller.

Abstract: Methods of depositing silicon-containing layers in the formation of semiconductor devices are described. The methods include a thermal chemical vapor deposition (CVD) process or a thermal atomic layer deposition (ALD) process without the use of plasma. Some methods include exposing a semiconductor substrate to a silicon-containing precursor, an oxygen-containing reactant, and an initiator compound to deposit a silicon oxide layer. Some methods include exposing a semiconductor substrate to a silicon-containing precursor, a nitrogen-containing reactant, and an initiator compound to deposit a silicon nitride layer. Some methods include exposing a semiconductor substrate to a silicon-containing precursor, an oxygen-containing reactant, a nitrogen-containing reactant, and an initiator compound to deposit a silicon oxynitride layer.

Abstract: Methods of manufacturing semiconductor devices, e.g., logic devices and/or memory devices, are described. Some embodiments relate to methods of depositing amorphous carbon hardmask layers that have high hardness, modulus, transparency, reduced stress, and low hydrogen content for use in logic devices and/or memory devices.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise an oxide layer and a semiconductor material layer between source regions and drain regions of the device. The method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer. An alternative method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by a surface treatment, and then radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer.

Abstract: Machine learning models to support tuning of an ion implanter are described. For example, a method may comprise receiving a set of control parameters and associated values for an ion implanter by a control model, the control model comprising an artificial neural network (ANN); predicting a set of process parameters and associated values for the ion implanter based on the set of control parameters and associated values by the control model; modifying at least one process parameter and associated value from the set of process parameters and associated values for the ion implanter; and analyzing modifications to the set of control parameters and associated values based on the modification of the at least one process parameter by a saliency model. Other embodiments are described and claimed.

Abstract: Techniques for guide star alignment of an ion implanter are described. A method includes receiving a first set of setting parameters for an ion implanter, the first set of setting parameters comprising a first set of control parameters and a corresponding first set of process parameters for guide star alignment of a series of beamline components of the ion implanter before a preventative maintenance (PM) phase; predicting a second set of setting parameters for the ion implanter by an alignment model, the second set of setting parameters comprising a second set of control parameters and a corresponding second set of process parameters for guide star alignment of the series of beamline components of the ion implanter after the PM phase of the ion implanter; and aligning the series of beamline components of the ion implanter based on the second set of setting parameters. Other embodiments are described and claimed.

Abstract: Provided are methods of manufacturing memory devices. The methods include exposing a film stack to an etching gas to remove alternating sacrificial layers of silicon nitride in the film stack. The memory devices have alternating layers of silicon oxide and silicon nitride and an opening formed therein. The etching gas comprises derivatives of phosphoric acid, phosphonic acid, and phosphonic acid. The silicon nitride layers are selectively etched relative to the silicon oxide layers with improved isotropicity and without compromising the integrity of the film stack.

Abstract: Implementations described herein provide a substrate support assembly which enables both lateral and azimuthal tuning of the heat transfer between an electrostatic chuck and a heating assembly. The substrate support assembly comprises a body having a substrate support surface and a lower surface, one or more main resistive heaters disposed in the body, a plurality of spatially tunable heaters disposed in the body, and a spatially tunable heater controller coupled to the plurality of spatially tunable heaters, the spatially tunable heater controller configured to independently control an output one of the plurality of spatially tunable heaters relative to another of the plurality of spatially tunable heaters.

Abstract: A simulation of an electronic device may use a distribution of atomistic defects to provide more accurate results. An input mesh may be received representing a physical structure of the electronic device. This input mesh may be transformed into a polyhedral mesh to facilitate the simulation. A distribution of defects may then be generated and distributed throughout the polyhedral mesh. When performing each time step of the simulation, the effects of these defects may be attributed to individual cells in the polyhedral mesh and incorporated into the simulation equations for each volume. For example, charge and power contributions from the defects may be incorporated into the simulation equations to more accurately model the performance of the device.