Abstract: Embodiments of the present disclosure generally relate to optical device fabrication. In particular, embodiments described herein relate to a method of forming a plurality of optical devices. In one embodiment, a method includes dicing a plurality of optical device lenses from a substrate, disposing the plurality of optical device lenses on a carrier, and performing at least one process on the plurality of optical device lenses to form a plurality of optical devices, each optical device having a plurality of optical device structures.

Abstract: A system may include a first semiconductor processing station configured to deposit a material on a first semiconductor wafer, a second semiconductor processing station configured perform measurements indicative of a thickness of the material after the material has been deposited on the first semiconductor wafer, and a controller. The controller may be configured to receive the measurements from the second station; provide an input based on the measurements to a trained model that is configured to generate an output that adjusts an operating parameter of the first station such that the thickness of the material is closer to a target thickness; and causing the first station to deposit the material on a second wafer using the operating parameter as adjusted by the output.

Abstract: A method of depositing nitride films is disclosed. Some embodiments of the disclosure provide a PEALD process for depositing nitride films which utilizes separate reaction and nitridation plasmas. In some embodiments, the nitride films have improved growth per cycle (GPC) relative to films deposited by thermal processes or plasma processes with only a single plasma exposure. In some embodiments, the nitride films have improved film quality relative to films deposited by thermal processes or plasma processes with only a single plasma exposure.

Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM has a general formula I to XIX, wherein R, R?, R1, R2, R3, R4, and R5 are independently selected from hydrogen (H), alkyl, alkene, alkyne, and aryl, n is from 1 to 20, m is from 1 to 20, x is from 1 to 2, and y is from 1 to 2. A barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

Abstract: Embodiments of the present disclosure are related to directed to a pressure seal for a process chamber. The pressure seal comprises a bottom portion, a compressible middle portion on the bottom portion, and a top portion on the compressible middle portion. The disclosed pressure seal is configured to reduce pumping time of a process region in an interior volume of a processing chamber compared to a process chamber that does not include a pressure seal. Processing chambers including the disclosed pressure seal are configured to process a semiconductor substrate at high temperatures, such as a temperature of greater than or equal to 350° C. Methods of sealing a processing chamber using the disclosed pressure seal are also described.

Abstract: An apparatus may include an electrodynamic mass analysis (EDMA) assembly disposed downstream from the convergent ion beam assembly. The EDMA assembly may include a first stage, comprising a first upper electrode, disposed above a beam axis, and a first lower electrode, disposed below the beam axis, opposite the first upper electrode. The EDMA assembly may also include a second stage, disposed downstream of the first stage and comprising a second upper electrode, disposed above the beam axis, and a second lower electrode, disposed below the beam axis. The EDMA assembly may further include a deflection assembly, disposed between the first stage and the second stage, the deflection assembly comprising a blocker, disposed along the beam axis, an upper deflection electrode, disposed on a first side of the blocker, and a lower deflection electrode, disposed on a second side of the blocker.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) array access transistors with improved hole distribution. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include a p-doped bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, where the first channel is spaced apart from the second channel in a row extending in the second horizontal direction.

Abstract: An apparatus, including an electrodynamic mass analysis (EDMA) assembly. The EDMA assembly may include a first upper electrode, disposed above a beam axis; and a first lower electrode, disposed below the beam axis, opposite the first upper electrode, the EDMA assembly arranged to receive a first RF voltage signal at a first frequency. The apparatus may include a deflection assembly, disposed downstream to the EDMA assembly, the deflection assembly comprising a blocker, disposed along the beam axis. The apparatus may include an energy spread reducer (ESR), disposed downstream to the deflection assembly, the energy spread reducer arranged to receive a second RF voltage signal at a second frequency, twice the first frequency. The ESR may include an upper ESR electrode, disposed above the beam axis; and a lower ESR electrode, disposed below the beam axis.

Abstract: The present technology includes methods and systems for improving substrate processing. Methods and systems include disposing a substrate on a pedestal that includes a plurality of heating zones each with an independent heater, processing the substrate according to an initial substrate processing recipe that includes an initial pedestal temperature, collecting initial substrate feedback of one or more substrate properties and providing the data as a first input to a substrate control algorithm. Methods include generating a substrate model based upon one or more modeling tests of the substrate, providing the generated substrate model as a second input to the substrate control algorithm, controlling the heater power or heater temperature to achieve a targeted substrate property in one or more substrate regions. Methods include where the correction is calculated and performed by a processor running the substrate control algorithm based upon the first input and the second input.

Abstract: The present technology includes monolithic electroplating seals, such as electroplating seals formed utilizing additive manufacturing. Seals include an external seal member and an internal seal member. The external seal member includes an inner annular radius, an outer annular radius, and an external seal member body defined between an exterior surface and an interior surface opposite the exterior surface. The exterior surface is formed from at least one polymer layer having a porosity of less than or about 10 vol. % and the external seal member body includes a filler. The internal seal member is formed integrally with and extends along at least a portion of the interior surface of the external seal member from the inner annular radius towards the outer annular radius. The internal seal member includes a deformable thermoplastic elastomer.

Abstract: Embodiments of substrate supports are provided herein. In some embodiments, a substrate support for use in a chemical vapor deposition (CVD) chamber includes: a pedestal to support a substrate, wherein the pedestal includes a dielectric plate coupled to a pedestal body; a rotary union coupled to the pedestal, wherein the rotary union includes a stationary housing disposed about a rotor; a drive assembly coupled to the rotary union; a coolant union coupled to the rotary union and having a coolant inlet fluidly coupled to coolant channels disposed in the pedestal via a coolant line; an RF rotary joint coupled to the coolant union and having an RF connector configured to couple the pedestal to an RF bias power source; and an RF conduit that extends from the RF connector to the pedestal through a central opening of the pedestal body to provide RF bias to the pedestal.

Abstract: Exemplary semiconductor processing methods include forming a via in a semiconductor structure. The via may be defined in part by a bottom surface and a sidewall surface formed in the semiconductor structure around the via. The methods may also include depositing a tantalum nitride (TaN) layer on the bottom surface of the via. In embodiments, the TaN layer may be deposited at a temperature less than or about 200° C. The methods may still further include depositing a titanium nitride (TiN) layer on the TaN layer. In embodiments, the TiN layer may be deposited at a temperature greater than or about 300° C. The methods may additionally include depositing a fill-metal on the TiN layer in the via. In embodiments, the metal may be deposited at a temperature greater than or about 300° C.

Abstract: Methods of forming memory devices are described. A molybdenum silicide nucleation layer is formed, and the substrate is soaked in a titanium precursor prior to a bulk molybdenum gap fill process. In other embodiments, a molybdenum silicide film is formed in a first process cycle and a second process cycle is performed where the substrate is exposed to a titanium precursor. In further embodiments, a substrate having at least one feature thereon is exposed to a first titanium precursor and a nitrogen-containing reactant. The substrate is then soaked in a second titanium precursor, and then is exposed to a first molybdenum precursor followed by exposure to a silane to form a molybdenum silicide layer on a surface of the substrate.

Abstract: Exemplary support assemblies may include a top puck characterized by a first surface and a second surface opposite the first surface. The top puck may define a recessed ledge at an outer edge of the first surface of the top puck. The assemblies may include a cooling plate coupled with the top puck adjacent the second surface of the top puck. The assemblies may include a back plate coupled with the top puck about an exterior of the top puck. The back plate may at least partially define a volume with the top puck. The cooling plate may be housed within the volume. The assemblies may include a heater disposed on the recessed ledge of the top puck. The assemblies may include an edge ring seated on the heater and extending about the top puck. The edge ring may be maintained free of contact with the top puck.

Abstract: The present disclosure generally relates to a method and apparatus for forming a substrate having a graduated refractive index. A method of forming a waveguide structure includes expelling plasma from an applicator having a head toward a plurality of grating structures formed on a substrate. The plasma is formed in the head at atmospheric pressure. The method further includes changing a depth of the plurality of grating structures with the plasma by removing grating material from the plurality of grating structures.

Abstract: Embodiments of exhaust liner systems are provided herein. In some embodiments, an exhaust liner system for use in a process chamber includes a lower exhaust liner having an annular body with a central opening; an upper flange, a central flange, and a lower flange extending outward from the annular body, wherein the lower flange and the central flange partially define a first plenum, and wherein the central flange and the upper flange partially define a second plenum; a plurality of exhaust holes from the central opening to the first plenum; and at least one cutout in the central flange to provide a flow path from the first plenum to the second plenum, wherein the lower exhaust liner defines a gas flow path from the central opening to the first plenum via the plurality of exhaust holes and from the first plenum to the second plenum via the least one cutout.

Abstract: Lithium ion batteries, methods of making the same, and equipment for making the same are provided. In one or more embodiments, an integrated processing system operable to form a pre-lithiated electrode includes a reel-to-reel system operable to transport a continuous sheet of material through processing chambers and a pre-lithiation module defining a processing region and is adapted to process the continuous sheet of material. The pre-lithiation module contains a lithium metal target operable to contact and supplying lithium to the continuous sheet of material, a press coupled with the lithium metal target and operable to move the lithium metal target into contact with the continuous sheet of material, one or more ultrasonic transducers positioned in the processing region and operable to apply ultrasonic energy to the lithium metal target, and one or more heat sources positioned in the processing region and operable to heat the lithium metal target.

Abstract: A method of imprinting a pattern on a substrate is provided. The method includes forming a first pattern on a plurality of masters using a method other than imprinting, the first pattern including a plurality of patterned features of varying sizes; measuring the patterned features at a plurality of locations on each of the masters; selecting a first master of the plurality of masters based on the measurements of the patterned features on each of the masters; using the first master to form a second pattern on an imprint template; and imprinting the first pattern on a first device with the imprint template.

Abstract: Methods and techniques for deposition of amorphous carbon films on a substrate are provided. In one example, the method includes depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further includes implanting a dopant or the inert species into the amorphous carbon film in a second processing region. The implant species, energy, dose & temperature in some combination may be used to enhance the hardmask hardness. The method further includes patterning the doped amorphous carbon film. The method further includes etching the underlayer.