Abstract: An apparatus includes a substrate holder, a first actuator to rotate the substrate holder, a second actuator to move the substrate holder linearly, a first sensor to generate one or more first measurements or images of the substrate, a second sensor to generate one or more second measurements of target positions on the substrate, and a processing device. The processing device estimates a position of the substrate on the substrate holder and causes the first actuator to rotate the substrate holder about a first axis. The rotation causes an offset between a field of view of the second sensor and a target position on the substrate due to the substrate not being centered on the substrate holder. The processing device causes the second actuator to move the substrate holder linearly along a second axis to correct the offset. The processing device determines a profile across a surface of the substrate based on the one or more second measurements of the target positions.

Abstract: Describes are shutter disks comprising one or more of titanium (Ti), barium (Ba), or cerium (Ce) for physical vapor deposition (PVD) that allows pasting to minimize outgassing and control defects during etching of a substrate. The shutter disks incorporate getter materials that are highly selective to reactive gas molecules, including O2, CO, CO2, and water.

Abstract: Apparatus and methods for calibrating a height-adjustable edge ring are described herein. In one example, a calibration jig for positioning an edge ring relative to a reference surface is provided that includes a transparent plate, a plurality of sensors coupled to a first side of the transparent plate, and a plurality of contact pads coupled to an opposing second side of the transparent plate.

Abstract: Disclosed herein are approaches for reducing EUV dose during formation of a patterned metal oxide photoresist. In one approach, a method may include providing a stack of layers atop a substrate, the stack of layers comprising a film layer, and implanting the film layer with ions. The method may further include depositing a metal oxide photoresist atop the film layer, and patterning the metal oxide photoresist.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes combining selective recess of a sacrificial layer and isotropic etching of a silicon layer in order to form a protective cap that will allow the silicon layer of the substrate to be etched without affecting the sacrificial layer.

Abstract: Embodiments of the disclosure relate to methods for reducing or eliminating the first wafer effect after chamber cleans for plasma etch processes. In some embodiments, the wafer support is maintained at an elevated temperature relative to the etch process. In some embodiments, the etch process is a NF3+NH3 plasma etch to remove native oxides from a silicon substrate.

Abstract: Exemplary deposition methods may include introducing hydrogen into a processing chamber, a powder disposed within a processing region of the processing chamber. The method may include striking a first plasma in the processing region, the first plasma including energetic hydrogen species. The method may include exposing the powder to the energetic hydrogen species in the processing region. The method may include chemically reducing the powder through a reaction of the powder with the energetic hydrogen species. The method may include removing process effluents including unreacted hydrogen from the processing region. The method may also include forming a layer of material on grains of the powder within the processing region.

Abstract: A polishing apparatus includes a support configured to receive and hold a substrate in a plane, a polishing pad affixed to a cylindrical surface of a rotary drum, a first actuator to rotate the drum about a first axis parallel to the plane, a second actuator to bring the polishing pad on the rotary drum into contact with the substrate, and a port for dispensing a polishing liquid to an interface between the polishing pad and the substrate.

Abstract: A crested barrier memory device may include a first electrode, a first self-rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately ?0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.

Abstract: A mask frame support unit includes a case, a protruding body extending below the case, and a station having a flat head disposed above the case. The protruding body includes a tapered region and a cylindrical region. The tapered region includes a first end having a first diameter coupled to the case and comprising a second end having a second diameter opposite the first end. The second diameter is less than the first diameter, and the tapered region is coupled to the cylindrical region at the second end. The case houses a number of components including an upper receiving plate in contact with the station, a lower receiving plate disposed underneath the upper receiving plate, a flat head unit movement support mechanism disposed between the lower receiving plate and the body, and a centering component.

Abstract: Embodiments of the present disclosure generally provide apparatus for collecting and reuse polishing fluids and methods related thereto. In particular, the apparatus and methods provided herein feature a polishing fluid collection system used to collect and reuse polishing fluids dispensed during the chemical mechanical polishing (CMP) of a substrate in an electronic device manufacturing process. In one embodiment, a polishing fluid catch basin assembly includes a catch basin sized to surround at least a portion of a polishing platen and to be spaced apart therefrom. The catch basin features an outer wall, an inner wall disposed radially inward of the outer wall, and a base portion connecting the inner wall to the outer wall. The outer wall, the inner wall, and the base portion collectively define a trough. A radially inward facing surface of the inner wall is defined by an arc radius which is greater than a radius of the polishing platen the catch basin is sized to surround.

Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.

Abstract: Plasma source assemblies comprising a housing with an RF hot electrode having a body and a plurality of source electrodes extending vertically from the RF hot electrode toward the opening in a front face of the housing are described. Processing chambers incorporating the plasma source assemblies and methods of using the plasma source assemblies are also described.

Abstract: The subject matter of this specification can be implemented in, among other things, a method, system, and/or device to receive current metrology data for an operation on a current sample in a fabrication process. The metrology data includes a current value for a parameter at each of one or more locations on the current sample. The method further includes determining a current rate of change of the parameter value for each of the one or more locations. The current rate of change is associated with the current sample. The method further includes identifying one or more violating locations each having an associated current rate of change of the parameter value that is greater than an associated reference rate of change of the parameter value, and identifying an instance of abnormality of the fabrication process based on the one or more violating locations.

Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 ?/min.

Abstract: Disclosed herein are systems and methods for reducing startup time of an equipment front end module (EFEM). The EFEM may include an EFEM chamber formed between a plurality of walls, an upper plenum above the EFEM chamber, the upper plenum in fluid communication with the EFEM chamber, a plurality of ducts that provide a return gas flow path enabling recirculation of gas from the EFEM chamber to the upper plenum, one or more filters that separate the upper plenum from the EFEM chamber, an isolation gate configured to block the return gas flow path responsive to the isolation gate being actuated to a closed position to isolate the one or more filters from an ambient environment responsive to a gas being flowed through the upper plenum when the EFEM chamber is opened to the ambient environment.

Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in an organic light-emitting diode (OLED) display are described herein. The overhang structures are permanent to the sub-pixel circuit. The overhang structures include a conductive oxide. A first configuration of the overhang structures includes a base portion and a top portion with the top portion disposed on the base portion. In a first sub-configuration, the base portion includes the conductive oxide of at least one of a TCO material or a TMO material. In a second sub-configuration, the base portion includes a metal alloy material and the conductive oxide of a metal oxide surface. A second configuration of the overhang structures includes the base portion and the top portion with a body portion disposed between the base portion and the top portion. The body portion includes the metal alloy body and the metal oxide surface.

Abstract: Embodiments of the present disclosure generally relate to pattern replication, imprint lithography, and more particularly to methods and apparatuses for creating a large area imprint without a seam. Methods disclosed herein generally include filling seams between pairs of masters with a filler material such that the seams are flush with a surface of the masters having a plurality of features disposed thereon.

Abstract: Chalcogen silane precursors are described. Methods for depositing a silicon nitride (SixNy) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (SixNy) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).

Abstract: Embodiments herein include carrier loading stations and methods related thereto which may be used to beneficially remove nano-scale and/or micron-scale particles adhered to a bevel edge of a substrate before polishing of the substrate. By removing such contaminates, e.g., loosely adhered particles of dielectric material, from the bevel edge, contamination of the polishing interface can be avoided thus preventing and/or substantially reducing scratch related defectivity associated therewith.