Abstract: Methods of semiconductor processing may include providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A feature may extend through one or more layers of material disposed on the substrate. The methods may include forming plasma effluents of the silicon-containing precursor and the oxygen-containing precursor. The methods may include contacting the substrate with the plasma effluents of the silicon-containing precursor and the oxygen-containing precursor. The contacting may form a silicon-and-oxygen-containing material on at least a bottom portion of the feature. A temperature in the processing region may be maintained at less than or about 0° C.

Abstract: Exemplary seal cleaning apparatuses may include at least one support that is configured to receive a seal. The apparatuses may include a tool arm that is positionable within an interior of the seal. The apparatuses may include a pad holder that is rotatably coupled with the tool arm. The pad holder may include a body having a first end and a second end. The first end may define a channel that is configured to receive a cleaning pad. The body may define an aperture that extends from the second end through the channel. The pad holder may include a fluid fitting coupled with the aperture at the second end of the body. The apparatuses may include a cleaning fluid source that is fluidly coupled with the fluid fitting.

Abstract: Electrochemical deposition systems and methods are described that have enhanced crystallization prevention features. The systems may include a bath vessel operable to hold an electrochemical deposition fluid having a metal salt dissolved in water. The systems may also include sensors including a thermometer and concentration sensor operable to measure characteristics of the electrochemical deposition fluid. The systems further include a computer configured to perform operations that include receiving system data from the electrochemical system and generating a control signal to change a characteristic of the electrochemical deposition fluid to prevent crystallization of a metal salt in the fluid. The computer generates the control signal based on processing that may include comparing an actual metal salt concentration in the electrochemical deposition fluid to a theoretical solubility limit for the metal salt in the fluid.

Abstract: An ion implanter may include an ion source to generate an ion beam. The ion implanter may include a set of beamline components to direct the ion beam to a substrate along a beam axis, as well as a process chamber to house the substrate to receive the ion beam. The ion implanter may include a conoscopy system, comprising: an illumination source to direct light to a substrate position; a first polarizer, having a first polarization axis, disposed between the illumination source and the substrate position; a second polarizer, the second polarizer being disposed to receive the light after passing through the substrate position. The conoscopy system may include a lens, to receive the light after passing through the substrate position, and a detector, to detect the light after passing through the lens.

Abstract: Exemplary methods for a coating a component of a semiconductor processing system may include forming a nickel-containing alloy on an exposed surface the component of the semiconductor processing system. The methods may include forming plasma effluents of a fluorine-containing precursor. The methods may include contacting the nickel-containing alloy with the plasma effluents of the fluorine-containing precursor. The contacting may fluorinate a portion of the nickel-containing alloy to form a nickel-and-fluorine-containing material overlying the nickel-containing alloy.

Abstract: The disclosure describes devices, systems and methods relating to a transfer chamber for an electronic device processing system. For example, a method includes causing a robot arm to pick up a substrate. The robot arm is caused to pick up the substrate by causing a first mover to rotate or to change a first distance to a second mover. Rotation of the first mover or the change in the first distance causes the first robot arm to rotate about a shoulder axis. The robot arm is further caused to pick up the substrate by causing one of a) a second mover to rotate or b) a third mover to change a second distance to the second mover. Rotation of the second mover or the change in the second distance causes the robot arm to raise or lower.

Abstract: A polishing system includes a carriage arm having an actuator disposed on a lower surface thereof. The actuator includes a piston and a roller coupled to a distal end of the piston. The polishing system includes a polishing pad and a substrate carrier suspended from the carriage arm and configured to apply a pressure between a substrate and the polishing pad. The substrate carrier includes a housing, a retaining ring, and a membrane. The substrate carrier includes an upper load ring disposed in the housing. The roller of the actuator is configured to contact the upper load ring during relative rotation between the substrate carrier and the carriage arm. The actuator is configured to apply a load to a portion of the upper load ring thereby altering the pressure applied between the substrate and the polishing pad.

Abstract: Exemplary semiconductor processing chambers include a chamber body defining a processing region. The chambers may include a substrate support disposed within the processing region. The substrate support may have an upper surface that defines a recessed substrate seat. The chambers may include a shadow ring disposed above the substrate seat and the upper surface. The shadow ring may extend about a peripheral edge of the substrate seat. The chambers may include bevel purge openings defined within the substrate support proximate the peripheral edge. A bottom surface of the shadow ring may be spaced apart from a top surface of the upper surface to form a purge gas flow path that extends from the bevel purge openings along the shadow ring. A space formed between the shadow ring and the substrate seat may define a process gas flow path. The gas flow paths may be in fluid communication with one another.

Abstract: Methods and systems for RF pulse monitoring and RF pulsing parameter optimization at a manufacturing system are provided. Sensor data is received from one or more sensors that indicates an RF pulse waveform detected within the processing chamber. One or more RF signal characteristics are identified in the detected RF pulse waveform. Each identified RF signal characteristic corresponds to at least one RF signal pulse of the RF signal pulsing within the processing chamber. A determination is made, based on the identified one or more RF signal characteristics, whether the detected RF pulse waveform corresponds to the target RF pulse waveform. An indication of whether the detected RF pulse waveform corresponds to the target RF pulse waveform is provided to a client device.

Abstract: A method for removing etchant byproduct from an etch reactor and discharging a substrate from an electrostatic chuck of the etch reactor is provided. One or more layers on a substrate electrostatically secured to an electrostatic chuck within a chamber of the etch reactor is etched using a first plasma, causing an etchant byproduct to be generated. A portion of the one or more layers are covered by a photoresist. After the etching is complete, a second plasma is provided into the chamber for a time period sufficient to trim the photoresist and remove a portion of the etchant byproduct. A second time period sufficient to electrostatically discharge the substrate using the second plasma is determined. Responsive to deactivating one or more chucking electrodes of the electrostatic chuck, the second plasma is provided into the chamber for the second time period and the substrate is removed from the chamber.

Abstract: Methods for monitoring process chambers using a controllable plasma oxidation process followed by a controlled reduction process and metrology are described. In some embodiments, the metrology comprises measuring the reflectivity of the metal oxide film formed by the controllable plasma oxidation process and the reduced metal film or surface modified film formed by reducing the metal oxide film.

Abstract: Disclosed are approaches for forming semiconductor device layers. One method may include forming a plurality of openings in a semiconductor structure, and forming a film layer atop the semiconductor structure by delivering a material at a non-zero angle relative to a normal extending perpendicular from an upper surface of the semiconductor structure. The film layer may be formed along the upper surface of the semiconductor structure without being formed along a sidewall of each opening of the plurality of openings, wherein an opening though the film layer remains above each opening of the plurality of openings.

Abstract: Embodiments of the disclosure provided herein include a method for processing a substrate in a plasma processing system. The method includes receiving a first synchronization waveform signal from a controller, delivering a first burst of first voltage pulses to an electrode assembly after receiving a first portion of the first synchronization waveform signal, wherein at least one first parameter of the first voltage pulses is set to a first value based on a first waveform parameter within the first portion of the first synchronization waveform signal, and delivering a second burst of second voltage pulses to the electrode assembly after receiving a second portion of the first synchronization waveform signal, wherein the at least one first parameter of the first voltage pulses is set to a second value based on a difference in the first waveform parameter within the second portion of the first synchronization waveform signal.

Abstract: The present disclosure is directed towards polishing modules for performing chemical mechanical polishing of a substrate. The substrate may be a semiconductor substrate. The polishing modules described have a plurality of pads, such as polishing pads, disposed within a single polishing station. The pads are configured to remain stationary during processing, such as during polishing or buff operations. Either an x-y gantry assembly or a head actuation assembly is coupled to a system body of a polishing module and is configured to move a carrier head over the pads. Between process operations the polishing pads may be indexed to expose a new polishing pad to the carrier head.

Abstract: Electronic device manufacturing systems, robot apparatus and associated methods are described. The robot apparatus includes an arm having an inboard end and an outboard end, the inboard end is configured to rotate about a shoulder axis; a first forearm is configured for independent rotation relative to the arm about an elbow axis at the outboard end of the arm; a first wrist member is configured for independent rotation relative the first forearm about a first wrist axis at a distal end of the first forearm opposite the elbow axis, wherein the first wrist member includes a first end effector and a second end effector. The robot apparatus further includes a second forearm configured for independent rotation relative to the arm about the elbow axis; a second wrist member configured for independent rotation relative the second forearm about a second wrist axis, wherein the second wrist member comprises a third end effector and a fourth end effector.

Abstract: Exemplary semiconductor processing systems may include a pumping system, a chamber body that defines a processing region, and a pumping liner disposed within the processing region. The pumping liner may define an annular member characterized by a wall that defines an exhaust aperture coupled to the pumping system. The annular member may be characterized by an inner wall that defines a plurality of apertures distributed circumferentially along the inner wall. A plenum may be defined in the annular member between interior surfaces of the walls. A divider may be disposed within the plenum, where the divider separates the plenum into a first plenum chamber and a second plenum chamber, wherein the first plenum chamber is fluidly accessible from the apertures defined through the inner wall, and wherein the divider defines at least one aperture providing fluid access between the first plenum chamber and the second plenum chamber.

Abstract: The interconnect resistances in a hybrid bonded structure can be controlled and designed. The resistance of each interconnect can be controlled by the width of the vias, the number of vias, and the thickness of liners within the vias. A first interconnect and a second interconnect of a hybrid bonded structure can have different interconnect resistances despite being on the same wafer or chip. The techniques described herein include designing interconnects and forming interconnects with particular resistances.

Abstract: Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. Some embodiments of the methods include conventional dipole engineering techniques such as dipole first processes and/or dipole last processes without the need for repairing the interfacial layer after treatment (in dipole first processes) or repairing the high-? dielectric layer after the annealing process (in dipole last processes).

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular, and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers that are protected from material loss during removal of a middle sacrificial layer. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a middle sacrificial layer on a top surface of the first hGAA structure, the middle sacrificial layer comprising silicon germanium (SiGe); and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise silicon germanium (SiGe).

Abstract: Exemplary semiconductor processing methods may include flowing an etchant precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may define an exposed region of a metal-containing hardmask material and an exposed region of a material characterized by a dielectric constant of less than or about 4.0. The methods may include contacting the substrate with the etchant precursor. The methods may include removing at least a portion of the metal-containing hardmask material.