Abstract: Exemplary semiconductor structures may include a substrate. The structures may include a first layer of silicon-and-oxygen-containing material overlying the substrate. The structures may include a second layer of silicon-and-oxygen-containing material. The structures may include a first layer of metal-and-oxygen-containing material between the first layer of silicon-and-oxygen-containing material and the second layer of silicon-and-oxygen-containing material. The first layer of metal-and-oxygen-containing material may include a first metal. The structures may include a second layer of metal-and-oxygen-containing material disposed within the first layer of metal-and-oxygen-containing material. The second layer of metal-and-oxygen-containing material may include a second metal. The structures may include a gate disposed within the second layer of metal-and-oxygen-containing material.

Abstract: Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a depth of the array of contact opening pairs varies in the first direction. The method may further include forming a second lithography mask over the film stack, and performing a second series of alternating lithography and etch processes, wherein an opening through the second lithography mask is expanded in a second direction following each etch process, and wherein the depth of the array of contact opening pairs varies in the second direction.

Abstract: Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a depth of the array of contact opening pairs varies in the first direction. The method may further include forming a second lithography mask over the film stack, and performing a second series of alternating lithography and etch processes, wherein an opening through the second lithography mask is expanded in a second direction following each etch process, and wherein the depth of the array of contact opening pairs varies in the second direction.

Abstract: Methods for depositing an amorphous carbon layer on a substrate and for filling a substrate feature with an amorphous carbon gap fill are described. The method comprises performing a deposition cycle comprising: introducing a hydrocarbon source into a processing chamber; introducing a plasma initiating gas into the processing chamber; generating a plasma in the processing chamber at a temperature of greater than 600° C.; forming an amorphous carbon layer on a substrate with a deposition rate of greater than 200 nm/hr; and purging the processing chamber.

Abstract: Embodiments of the present technology may include semiconductor processing methods. The methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-containing precursor and a nitrogen-containing precursor. A substrate including one or more materials may be disposed within the processing region. The substrate may be characterized by a first bowing of the substrate. The methods may include generating plasma effluents of the deposition precursors. The methods may include forming a layer of silicon-and-nitrogen-containing material on the substrate. The layer of silicon-and-nitrogen-containing material may be characterized by a tensile stress. Subsequent forming the layer of silicon-and-nitrogen-containing material, the substrate may be characterized by a second bowing of the substrate that is less than the first bowing of the substrate.

Abstract: Semiconductor processing methods are described for forming low-? dielectric materials. The methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-hydrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant of less than or about 4.0.

Abstract: Embodiments of the present disclosure generally relate to a method for forming an electrically conductive feature on a substrate. In one embodiment, the method includes forming a first conductive layer via physical vapor deposition (PVD) in an opening of a substrate. The first conductive layer has a thickness of less than 20 angstroms. The method further includes forming a second conductive layer via PVD on the first conductive layer. The first conductive layer and the second conductive layer are formed at a temperature of less than 50° C. The method further includes annealing at least a portion of the first conductive layer and the second conductive layer.

Abstract: A method for manufacturing a memory device includes depositing a seed layer in a memory hole extending through a memory stack. The seed layer includes particles, such as silicon particles. The seed layer is etched to produce etched particles. The etched particles act as nuclei for the growth of a crystalline channel material in the memory hole.

Abstract: Methods and apparatus for cleaning a dielectric tube are described. The dielectric tube is exposed to a cleaning gas comprising a fluorine-containing compound and a microwave plasma is generated. The dielectric tube is cleaned to restore transparency and increase electronic coupling between the microwave waveguide and the plasma through the dielectric tube.

Abstract: A method of cleaning a substrate in a megasonic cleaning chamber, comprises: flowing a cleaning fluid through a supply tube in a megasonic cleaning chamber toward a substrate; using a megasonic transducer to generate megasonic waves through the cleaning fluid and create cavities in the cleaning fluid; and using one or more sensors to determine properties of the cavities in-situ based on emissions received from the cavities. A non-transitory computer readable medium has instructions stored thereon that, when executed, causes the method to be performed.

Abstract: Aspects generally relate to methods, systems, and apparatus for processing substrates using one or more amorphous carbon hardmask layers. In one aspect, film stress is altered while facilitating enhanced etch selectivity. In one implementation, a method of processing a substrate includes depositing one or more amorphous carbon hardmask layers onto the substrate, and conducting a rapid thermal anneal operation on the substrate after depositing the one or more amorphous carbon hardmask layers. The rapid thermal anneal operation lasts for an anneal time that is 60 seconds or less. The rapid thermal anneal operation includes heating the substrate to an anneal temperature that is within a range of 600 degrees Celsius to 1,000 degrees Celsius. The method includes etching the substrate after conducting the rapid thermal anneal operation.

Abstract: A method includes measuring a subset of property values within a manufacturing chamber during a process performed on a substrate within the manufacturing chamber. The method further includes determining property values in the manufacturing chamber at locations removed from the locations the measurements are taken. The method further includes performing a corrective action based on the determined properties.

Abstract: An apparatus with a grating structure and a method for forming the same are disclosed. The grating structure includes forming a recess in a grating layer. A plurality of channels is formed in the grating layer to define slanted grating structures therein. The recess and the slanted grating structures are formed using a selective etch process.

Abstract: A method includes receiving historical time-series data and generating training data comprising a plurality of randomized data points associated with the historical time-series data. The historical time-series data was generated by one or more sensors during one or more processes. The method further includes training a logistic regression classifier based on the training data to generate a trained logistic regression classifier. The trained logistic regression classifier is associated with a logistic regression that indicates a location of a transition pattern from a first data point to a second data point. The transition pattern reflects about a reflection point located on the transition pattern. The trained logistic regression classifier is capable of indicating a probability that new time-series data generated during a new execution of the one or more processes matches the historical time-series data.

Abstract: Apparatus for processing substrates can include a gas distribution plate that includes an upper plate and a lower plate and a solid disk between the upper plate and the lower plate. Each of the upper plate and the lower plate has a central region and an outer region surrounding the central region, the central region being solid and the outer region having a plurality of through holes. The upper plate and the lower plate are coaxially aligned along a central axis extending through a center of the central region of the upper plate and a center of the central region of the lower plate. The solid disk is coaxially aligned with the upper plate and the lower plate. The solid disk is configured to block transmission of ultraviolet radiation through the solid disk.

Abstract: A membrane for a CMP carrier head includes a circular lower portion that provides a substrate mounting surface for a central region of a substrate, a first plurality of flaps that extend upward from the circular lower portion to form a plurality of inner chambers, an annular upper portion that provides a lower surface for applying pressure to an annular outer region of the substrate, and a second plurality of flaps that extend upward from the annular upper portion to form a plurality of independently pressurizable outer chambers. The annular upper portion surrounds the circular lower portion and is vertically offset from the circular lower portion such that the lower surface is positioned above a plane defined by the circular lower portion, and the annular upper portion is coupled to an outermost flap of the first plurality of flaps.

Abstract: Disclosed herein are a substrate sorter, an inspection and sorting system having the substrate sorter, and a method for the inspection and sorting system. The substrate sorter includes an annular gripper comprising a rotator and a plurality of vacuum applicators concyclically disposed around an axis, a carrier operable to move a substrate towards the rotator and into a loading region below the rotator, and an actuator coupled with the annular gripper and operable to rotate the rotator about the axis relative to the plurality of vacuum applicators while one or more of the plurality of vacuum applicators hold the substrate against the rotator.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract: A method includes receiving first sensor data associated with a first iteration of a first recipe operation of a substrate processing recipe. The method further includes determining disturbance data, the disturbance data being a difference between the first sensor data and first setpoint data of the first recipe operation. The method further includes determining, based at least in part on the disturbance data, a first actuation value associated with one or more components of a processing chamber. Actuation of the one or more components according to the first actuation value compensates for the disturbance data. The method further includes causing the actuation of the one or more components based on the first actuation value during a subsequent iteration of the first recipe operation of the substrate processing recipe to compensate for the disturbance data.