Abstract: The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a flow guide applicable for use in semiconductor manufacturing, includes a plate having a first face and a second face opposing the first face. The flow guide includes a first fin set extending from the second face, and a second fin set extending from the second face. The second fin set is spaced from the first fin set to define a flow path between the first fin set and the second fin set. The flow path has a serpentine pattern between the first fin set and the second fin set.

Abstract: Disclosed herein are approaches for treating a film layer of a semiconductor device to modify an etch resistance of the film later. In one approach, a method may include forming a first film over a substrate base, depositing a second film over the first film, and introducing an inert species into the second film while the second film is deposited over the first film, wherein the inert species increases an etch-resistance of a first portion of the first film. The method may further include removing the second film by stopping deposition of the second film while continuing to introduce the inert species into the second film.

Abstract: Methods of depositing a metal film are discussed. A metal film is formed on the bottom of feature having a metal bottom and dielectric sidewalls. Formation of the metal film comprises exposure to a metal precursor and an alkyl halide catalyst while the substrate is maintained at a deposition temperature. The metal precursor has a decomposition temperature above the deposition temperature. The alkyl halide comprises carbon and halogen, and the halogen comprises bromine or iodine.

Abstract: A method, a system and computer program product for controlling exposure of a substrate positioned on a platen in an ion implantation system to an ion beam. A first current value determined based on a powering potential powering an ion source is received. A second current value determined based on an accelerating potential or a decelerating potential supplied to the ion implantation apparatus and affecting generation of the ion beam by the ion source for application to a substrate positioned on a platen is received. One or more energy filter supply current values are determined based on one or more energy filter supply potentials supplied to an energy filter positioned in the path of the ion beam. Platen position values are generated based on the first and second current values and energy filter supply current values. A position of the platen is adjusted using platen position values.

Abstract: A method may include providing a stress the substrate having a main surface, and forming a patterned stress compensation layer on the main surface, wherein the patterned stress compensation layer is formed by exposing the main surface to a processing beam while a movement of the ion beam with respect to the main surface takes place.

Abstract: A method may include providing a stress compensation stack on a main surface of the substrate, wherein the stress compensation stack comprises a patterned resist layer and a stress compensation layer, disposed subjacent the patterned resist layer. The patterned resist layer may be determined according to a surface map of the main surface of the substrate. The method may further include directing processing species to the stress compensation stack, wherein the stress compensation layer is selectively altered as a function of position across the substrate.

Abstract: Provided are methods of forming a semiconductor device. The method includes exposing a top surface of a substrate to a reactant and a metal precursor to selectively deposit a capping layer on the top surface of the substrate, the substrate comprising at least one feature formed in a dielectric layer, the dielectric layer defining a filled gap including sidewalls and a bottom, a barrier layer on the sidewalls of the filled gap, and a metal liner on the barrier layer, the capping layer depositing on one or more of the filled gap, the barrier layer, and the metal liner.

Abstract: Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The processing region may be at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated. A bias power may be applied to the substrate support from a bias power source. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.

Abstract: Embodiments of the present disclosure generally relate to augmented reality waveguide combiners. The waveguides includes a waveguide substrate, having a substrate refractive index (RI) nsub, a slab waveguide layer disposed over the waveguide substrate, the slab waveguide layer having a slab RI nswg and a slab depth dswg, the slab depth dswg from a lower surface to an upper surface of the slab waveguide layer, at least one grating defined by a plurality of grating structures, the grating structures are disposed in, on, or over the slab waveguide layer, and a superstrate between and over the grating structures, the superstrate having a superstrate RI nsuperstrate and an interface with the slab waveguide layer. The slab RI nswg is greater than the substrate RI nsub and the slab RI nswg is greater than the superstrate RI nsuperstrate.

Abstract: The present disclosure provides systems and methods for processing channel structures of substrates that include positioning the substrate in a first processing chamber having a first processing volume. The substrate includes a channel structure with high aspect ratio features having aspect ratios greater than about 20:1. The method includes forming a silicon-containing layer over the channel structure to a hydrogen-or-deuterium plasma in the first processing volume at a flow rate of about 10 sccm to about 5000 sccm. The substrate is maintained at a temperature of about 100° C. to about 1100° C. during the exposing, the exposing forming a nucleated substrate. Subsequent to the exposing a thermal anneal operation is performed on the substrate.

Abstract: Exemplary methods of forming a coating of material on a substrate may include forming a plasma of a first precursor and an oxygen-containing precursor. The first precursor and the oxygen-containing precursor may be provided in a first flow rate ratio. The methods may include depositing a first layer of material on the substrate. While maintaining the plasma, the methods may include adjusting the first flow rate ratio to a second flow rate ratio. The methods may include depositing a second layer of material on the substrate.

Abstract: Embodiments of the present disclosure generally relate to an electrostatic chuck assembly suitable for use in cryogenic applications. In one or more embodiments, an electrostatic chuck assembly is provided and includes an electrostatic chuck having a substrate supporting surface opposite a bottom surface, a cooling plate having a top surface, where the cooling plate contains an aluminum alloy having a coefficient of thermal expansion (CTE) of less than 22 ppm/° C., and a bonding layer securing the bottom surface of the electrostatic chuck and the top surface of the cooling plate.

Abstract: A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.

Abstract: Exemplary semiconductor processing systems may include an output manifold that defines at least one plasma outlet. The systems may include a gasbox disposed beneath the output manifold. The gasbox may include an inlet side facing the output manifold and an outlet side opposite the inlet side. The gasbox may include an inner wall that defines a central fluid lumen. The inner wall may taper outward from the inlet side to the outlet side. The systems may include an annular spacer disposed below the gasbox. An inner diameter of the annular spacer may be greater than a largest inner diameter of the central fluid lumen. The systems may include a faceplate disposed beneath the annular spacer. The faceplate may define a plurality of apertures extending through a thickness of the faceplate.

Abstract: Embodiments provided herein generally include apparatus, plasma processing systems and methods for generation of a waveform for plasma processing of a substrate in a processing chamber. One embodiment includes a waveform generator having a voltage source selectively coupled to an output node, where the output node is configured to be coupled to an electrode disposed within a processing chamber, and where the output node is selectively coupled to a ground node. The waveform generator may also include a radio frequency (RF) signal generator, and a first filter coupled between the RF signal generator and the output node.

Abstract: Embodiments described herein also relate to electronic and photonic integrated circuits and methods for fabricating integrated interconnect between electrical, opto-electrical and photonic devices. One or more optical silicon photonic devices described herein may be used in connection with one or more opto-electrical integrated circuits (opto-electrical chip) on a single package substrate to from a co-packaged optical and electrical device. The methods described herein enable high volume manufacturing of electrical, opto-electrical and the optical silicon photonic devices having a plurality of optical structures, such as waveguides, formed on or integral with a photonic glass layer substrate.

Abstract: Methods and apparatus for forming organic light emitting diode (OLED) structures disposed on a substrate are provided.

Abstract: Generating a recipe for a polishing process includes receiving a target removal profile that includes a target thickness to remove for a plurality of locations spaced angularly around a center of a substrate, storing a first function providing substrate orientation relative to the carrier head over time, storing a second function defining a polishing rate below a zone of the zone as a function of one or more pressures of one or more zones from a plurality of pressurizable zones of the carrier head that are spaced angularly around the center of the substrate, and for each particular zone of the plurality of zones, calculating a recipe defining a pressure for the particular zone over time.

Abstract: A system and method for providing analysis of at least some of a plurality of un-patterned and patterned metrology targets during a fabrication process. A sample is arranged within a chamber of a semiconductor processing tool. The sample has the plurality of un-patterned and patterned metrology targets. A metrology tool integrated with the semiconductor processing tool can provide the analysis of at least some of the plurality of un-patterned and patterned metrology targets. One or more parameters associated with the plurality of patterned metrology targets are determined using optical metrology signals from the plurality of un-patterned metrology targets.

Abstract: A system and method for fabricating a gate all-around (GAA) field effect transistor (FET) is disclosed. The method includes: forming a plurality of epitaxy layers on a substrate, wherein a formed epitaxy layer includes a plurality of doped channels, a plurality of metal channels, and a dummy gate; depositing a spacer in a source/drain cavity, wherein at least a portion of the spacer is deposited on a dummy gate of a formed epitaxy layer; partially etching the plurality of metal channels of to create a plurality of voids; depositing an inner spacer in each void of the plurality of voids; and depositing a stressed metal filler in the source/drain cavity.