Abstract: The interconnect resistances in a hybrid bonded structure can be controlled and designed. The resistance of each interconnect can be controlled by the width of the vias, the number of vias, and the thickness of liners within the vias. A first interconnect and a second interconnect of a hybrid bonded structure can have different interconnect resistances despite being on the same wafer or chip. The techniques described herein include designing interconnects and forming interconnects with particular resistances.

Abstract: Exemplary semiconductor processing systems may include a pumping system, a chamber body that defines a processing region, and a pumping liner disposed within the processing region. The pumping liner may define an annular member characterized by a wall that defines an exhaust aperture coupled to the pumping system. The annular member may be characterized by an inner wall that defines a plurality of apertures distributed circumferentially along the inner wall. A plenum may be defined in the annular member between interior surfaces of the walls. A divider may be disposed within the plenum, where the divider separates the plenum into a first plenum chamber and a second plenum chamber, wherein the first plenum chamber is fluidly accessible from the apertures defined through the inner wall, and wherein the divider defines at least one aperture providing fluid access between the first plenum chamber and the second plenum chamber.

Abstract: Methods of depositing improved quality silicon nitride (SixNy) films are disclosed. Exemplary methods include exposing a semiconductor substrate in a semiconductor processing chamber to a silicon-containing precursor, to a first plasma produced from a first gas mixture comprising helium (He) and nitrogen (N2), the first gas mixture comprising a ratio of helium:nitrogen in a range of from 20:1 to 1000:1, and exposing the semiconductor substrate to a second plasma produced from a second gas mixture comprising helium (He), nitrogen (N2), and ammonia (NH3).

Abstract: Embodiments of the present disclosure relate to a system, a software application, and a method of a lithography process to update one or more of a mask pattern, maskless lithography device parameters, lithography process parameters utilizing a file readable by each of the components of a lithography environment. The file readable by each of the components of a lithography environment stores and shares textual data and facilitates communication between of the components of a lithography environment such that the mask pattern corresponds to a pattern to be written is updated, the maskless lithography device of the lithography environment is calibrated, and process parameters of the lithography process are corrected for accurate writing of the mask pattern on successive substrates.

Abstract: Systems, methods, and computer-readable mediums for monitoring temperature of a substrate are described. Spectroscopic measurements are performed on a surface of the substrate using a metrology tool integrated with a processing tool. The measurements may be used to determine that the substrate has cooled below a threshold temperature using the spectroscopic measurements.

Abstract: Embodiments of the present disclosure generally relate to methods of forming a substrate having a target thickness distribution at one or more eyepiece areas across a substrate. The substrate includes eyepiece areas corresponding to areas where optical device eyepieces are to be formed on the substrate. Each eyepiece area includes a target thickness distribution. A base substrate thickness distribution of a base substrate is measured such that a target thickness change can be determined. The methods described herein are utilized along with the target thickness change to form a substrate with the target thickness distribution.

Abstract: Embodiments of the present disclosure relate to methods for forming a source/drain extension. In one embodiment, a method for forming an nMOS device includes forming a gate electrode and a gate spacer over a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to expose a side wall and a bottom, forming a silicon arsenide (Si:As) layer on the side wall and the bottom, and forming a source/drain region on the Si:As layer. During the deposition of the Si:As layer and the formation of the source/drain region, the arsenic dopant diffuses from the Si:As layer into a third portion of the semiconductor fin located below the gate spacer, and the third portion becomes a doped source/drain extension region. By utilizing the Si:As layer, the doping of the source/drain extension region is controlled, leading to reduced contact resistance while reducing dopants diffusing into the channel region.

Abstract: A method of processing an optical device is provided, including: positioning an optical device on a substrate support in an interior volume of a process chamber, the optical device including an optical device substrate and a plurality of optical device structures formed over the optical device substrate, each optical device structure including a bulk region formed of silicon carbide and one or more surface regions formed of silicon oxycarbide. The method further includes providing one or more process gases to the interior volume of the process chamber, and generating a plasma of the one or more process gases in the interior volume for a first time period when the optical device is on the substrate support, and stopping the plasma after the first time period. A carbon content of the one or more surface regions of each optical device structure is reduced by at least 50% by the plasma.

Abstract: A method of forming a semiconductor structure includes annealing a surface of a substrate in an ambient of hydrogen to smooth the surface, pre-cleaning the surface of the substrate, depositing a high-? dielectric layer on the pre-cleaned surface of the substrate, performing a re-oxidation process to thermally oxidize the surface of the substrate; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-? dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-? dielectric layer.

Abstract: Provided herein are approaches for providing a more uniform ion flux and ion angular distribution across a wafer to minimize etch yield loss resulting from etch profile variations. In some embodiments, a system may include a plasma source operable to generate a plasma within a plasma chamber enclosed by a chamber housing, wherein the plasma source comprises a plasma shaper extending into the plasma chamber from a wall of the chamber housing. The plasma shaper may include a shaper wall coupled to the wall of the chamber housing, and a shaper end wall connected to the shaper wall, the shaper end wall defining an indentation extending towards the wall of the chamber housing.

Abstract: A method of cleaning a chamber for an electronics manufacturing system includes flowing a gas mixture comprising oxygen and a carrier gas into a remote plasma generator. The method further includes generating a plasma from the gas mixture by the remote plasma generator and performing a remote plasma cleaning of the chamber by flowing the plasma into an interior of the chamber, wherein the plasma removes a plurality of organic contaminants from the chamber.

Abstract: A method for etching a hardmask layer includes forming a photoresist layer comprising an organometallic material on a hardmask layer comprising a metal-containing material, exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern, removing un-irradiated areas of the photoresist layer to pattern the photoresist layer, forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, and etching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon.

Abstract: Apparatus and methods to process one or more wafers are described. The apparatus comprises a chamber defining an upper interior region and a lower interior region. A heater assembly is on the bottom of the chamber body in the lower interior region and defines a process region. A wafer cassette assembly is inside the heater assembly and a motor is configured to move the wafer cassette assembly from the lower process region inside the heater assembly to the upper interior region.

Abstract: A method of operating a beamline ion implanter may include performing, in an ion implanter, a first implant procedure to implant a dopant of a first polarity into a given semiconductor substrate, and generating an estimated implant dose of the dopant of the first polarity based upon a set of filtered information, generated by the first implant procedure. The method may also include calculating an actual implant dose of the dopant of the first polarity using a predictive model based upon the estimated implant dose, and performing, in the ion implanter, an adjusted second implant procedure to implant a dopant of a second polarity into a select semiconductor substrate, based upon the actual implant dose.

Abstract: Exemplary methods of packaging a substrate may include rotationally aligning a substrate to a predetermined angular position. The methods may include transferring the substrate to a metrology station. The methods may include measuring a topology of the substrate at the metrology station. The methods may include applying a first chucking force to the substrate to flatten the substrate. The methods may include generating a mapping of a die pattern on an exposed surface of the substrate. The methods may include transferring the substrate to a printing station. The methods may include applying a second chucking force to the substrate to flatten the substrate against a surface of the printing station. The methods may include adjusting a printing pattern based on the mapping of the die pattern. The methods may include printing the printing pattern on the exposed surface of the substrate.

Abstract: Devices and methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.

Abstract: A method of modifying an opening in a mask to achieve desired critical dimensions, the method including performing a pre-implant on the mask to implant the mask with a dopant material, wherein a material of the mask is densified and the opening is enlarged, directing a first radical beam at a first lateral side of the opening to deposit a layer of material on the first lateral side, and directing a second radical beam at a second lateral side of the opening opposite the first lateral side to deposit a layer of material on the second lateral side.

Abstract: A chiplet-based system may include a first chiplet mounted to an interposer that is designated as being from one or more trusted sources, a second chiplet mounted to the interposer that is designated as not being from the one or more trusted sources, and an artificial intelligence (AI) accelerator. The AI accelerator may be programmed to monitor a state of the first chiplet, where the state may indicate an anomaly associated with the second chiplet. The AI accelerator may then select an action from a plurality of actions based at least in part on the state of the first chiplet, cause the action to be performed by the chiplet-based system, and execute a reinforcement learning algorithm update the plurality of actions based on a result of the action being performed.