Abstract: Embodiments of the present disclosure generally relate to inductively coupled plasma sources and plasma processing apparatus. In at least one embodiment, plasma source includes a first sidewall and a gas injection insert defining a plasma source interior volume. The gas injection insert includes a peripheral gas injection port, a second sidewall disposed concentric with the first sidewall, and a center gas injection port. The plasma source includes a first induction coil disposed proximate the first sidewall and disposed around the first sidewall. The plasma source includes a first radio frequency power generator coupled with the first induction coil. The plasma source includes a second induction coil disposed proximate the second sidewall and disposed around the second sidewall. The plasma source includes a second radio frequency power generator coupled with the second induction coil.

Abstract: A method and apparatus for determining a growth rate on a semiconductor substrate is described herein. The apparatus is an optical sensor, such as an optical growth rate sensor. The optical sensor is positioned in an exhaust of a deposition chamber. The optical sensor is self-heated using one or more internal heating elements, such as a resistive heating element. The internal heating elements are configured to heat a sensor coupon. A film is formed on the sensor coupon by exhaust gases flowed through the exhaust and is correlated to film growth on a substrate within a process volume of the deposition chamber.

Abstract: An advanced temperature control system and method are described for a wafer carrier in a plasma processing chamber. In one example a heat exchanger provides a temperature controlled thermal fluid to a fluid channel of a workpiece carrier and receives the thermal fluid from the fluid channel. A proportional valve is between the heat exchanger and the fluid channel to control the rate of flow of thermal fluid from the heat exchanger to the fluid channel. A pneumatic valve is also between the heat exchanger and the fluid channel also to control the rate of flow of thermal fluid from the heat exchanger and the fluid channel. A temperature controller receives a measured temperature from a thermal sensor of the carrier and controls the proportional valve and the pneumatic valve in response to the measured temperature to adjust the rate of flow of the thermal fluid.

Abstract: Exemplary semiconductor processing methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-nitrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of silicon-carbon-and-nitrogen-containing material on the substrate. The layer of silicon-carbon-and-nitrogen-containing material may be characterized by a dielectric constant of less than or about 4.0. The layer of silicon-carbon-and-nitrogen-containing material may be characterized by a leakage current at 2 MV/cm of less than or about 3E-08 A/cm2.

Abstract: Exemplary methods of semiconductor processing may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A structure may be disposed within the processing region. The structure may include a first silicon-containing material. The structure may include a second silicon-containing material, an oxygen-containing material, or both. The methods may include contacting the structure with the etchant precursor. The contacting with the etchant precursor may etch at least a portion of the second silicon-containing material or the oxygen-containing material from the structure. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the structure with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the first silicon-containing material.

Abstract: Exemplary semiconductor processing methods may include a substrate housed in the processing region. A layer of silicon-containing material may be disposed on the substrate, a patterned resist material may be disposed on the layer of silicon-containing material, and a layer of carbon-containing material may be disposed on the patterned resist material and the layer of silicon-containing material. The methods may include providing a hydrogen-containing precursor, a nitrogen-containing precursor, or both to a processing region of a semiconductor processing chamber, forming plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor, and contacting the substrate with the plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor. The contacting may remove a portion of the layer of carbon-containing material.

Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

Abstract: Embodiments of the present disclosure generally relate to a lift pin guide. The lift pin guide includes a cylindrical main section, a flange, a cylindrical recess, a cylindrical extension, and a bore. The flange is disposed at a first end of the cylindrical main section and has a diameter greater than a diameter of the cylindrical main section. The cylindrical recess is formed in a first surface of the flange, the first surface of the flange being opposite the cylindrical main section, and the cylindrical recess having an outer diameter less than the diameter of the cylindrical main section. The cylindrical extension protrudes beyond the first surface of the flange, the cylindrical extension being concentric with the cylindrical main section. The bore is formed through the cylindrical main section and the cylindrical extension.

Abstract: Disclosed herein are methods for passivating SiC substrate defects using a low-energy treatment. In some embodiments, a method may include providing a silicon carbide (SIC) substrate, treating the SiC substrate using an ion implant or a plasma doping process, forming a first epitaxial layer over an upper surface of the SiC substrate after the SiC substrate is treated, and forming a second epitaxial layer over the first epitaxial layer.

Abstract: A Chemical Mechanical Polishing (CMP) process may generally apply more pressure around a periphery of the polishing pad than at the center of the polishing pad. This may cause uneven material removal as the substrate moves along the surface of the polishing pad. Therefore, the polishing pad may include one or more recesses around a periphery of the polishing pad to relieve pressure on the substrate. The one or more recesses may be connected to channels that extend radially outward from the recesses to the edge of the polishing pad. The recesses may collect polishing slurry during the CMP process and direct the slurry into the channels. The channels may then expel the collected polishing slurry off of the polishing pad to clear the recesses.

Abstract: Disclosed herein are methods for forming opening ends within semiconductor structures. In some embodiments, a method may include providing an opening formed in a layer of a semiconductor device, wherein the opening comprises a set of sidewalls opposite one another, and first and second end walls connected to the sidewalls, wherein each of the first and second end walls defines a tip end and a set of curved sections extending between the tip end and the set of sidewall. The method may further include performing an ion etch to the opening by delivering an ion beam at a non-zero angle relative to a plane defined by the layer of the semiconductor device, wherein the ion etch comprises a lean-gas chemistry, and wherein the ion etch causes the layer of the semiconductor device to be removed faster along the set of curved sections than along the set of sidewalls.

Abstract: Exemplary semiconductor processing methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber. The methods may include flowing a boron-containing precursor into the substrate processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-silicon-containing layer on a substrate in the substrate processing region of the semiconductor processing chamber. The boron-and-silicon-containing layer may be characterized by an increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer opposite the first surface. A flow rate of the boron-containing precursor may be increased during the deposition of the boron-and-silicon-containing layer.

Abstract: Techniques for inverting implanter process model for parameter generation are described. A method comprises receiving a set of process parameters and associated values for an ion implanter by an inverted control model, the inverted control model comprising an artificial neural network (ANN), predicting a set of control parameters and associated values for the ion implanter based on the set of process parameters and associated values by the inverted control model, and presenting the set of control parameters and associated values on a graphical user interface (GUI) of an electronic display. Other embodiments are described and claimed.

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices, fin field effect transistors (FinFETs) in particular, and methods of manufacturing such devices having improved effective capacitance (Ceff). The FinFETs include a gate structure in which airgaps are provided by recessing a high-k material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high-k dielectric layer and improving effective capacitance (Ceff) of the device.

Abstract: Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A first layer of silicon-and-germanium-containing material, a second layer of silicon-and-germanium-containing material, and a layer of silicon-containing material may be disposed on the substrate. The methods may include contacting the substrate with the oxygen-containing precursor. The contacting may oxidize at least a portion of the second layer of silicon-and-germanium-containing material. The methods may include providing a first etchant precursor to the processing region and contacting the substrate with the first etchant precursor. The contacting may selectively etch the first layer of silicon-and-germanium-containing material. The methods may include providing a second etchant precursor to the processing region.

Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate including one or more features may be housed within the processing region. The methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming plasma effluents of the silicon-containing precursor and the hydrogen-containing precursor. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend into the one or more features.

Abstract: A method for selective barrier metal etching includes performing a hydrogen implantation process, in an inductively coupled plasma (ICP) etch chamber, to chemically reduce an oxidized portion of a barrier metal layer formed within a feature in a metal layer on the barrier metal layer, and performing an etch process, in the ICP etch chamber, to remove the hydrogen implanted portion of the barrier metal layer.

Abstract: Embodiments of the disclosure include a method of processing a substrate in a plasma processing system, comprising delivering an RF signal, by an RF generator, through an RF match to an electrode assembly disposed within the plasma processing system, wherein while delivering the RF signal the RF match is set to a first matching point, and delivering a voltage waveform, by a waveform generator, to the electrode assembly disposed within the plasma processing system while the RF signal is delivered to the electrode assembly.

Abstract: Exemplary substrate processing systems may include a plurality of processing regions. The systems may include a transfer region housing defining a transfer region fluidly coupled with the plurality of processing regions. The systems may include a plurality of substrate supports. Each substrate support of the plurality of substrate supports may be vertically translatable between the transfer region and an associated processing region of the plurality of processing regions. The systems may include a transfer apparatus including a rotatable shaft extending through the transfer region housing. The transfer apparatus may also include an end effector coupled with the rotatable shaft. The systems may include an exhaust foreline including a plurality of foreline tails. Each foreline tail of the plurality of foreline tails may be fluidly coupled with a separate processing region of the plurality of processing regions. The systems may include a plurality of throttle valves.

Abstract: An electronic device manufacturing system capable of obtaining metrology data associated with a deposition process performed on a substrate according to a process recipe, wherein the deposition process generates a plurality of layers on a surface of the substrate. The manufacturing system can further obtain an expected profile associate with the process recipe, wherein the expected profile comprises a plurality of values indicative of a desired thickness for a plurality of layers of the process recipe. The manufacturing system can further generate a correction profile based on the metrology data and the expected profile, wherein the correction profile comprises a deposition time offset value for at least one layer of the plurality of layers. The manufacturing system can further generate an updated process recipe by applying the correction profile to the process recipe and cause a deposition step to be performed on the substrate according to the updated process recipe.