Abstract: Semiconductor processing systems and methods for increased etch selectivity and rate are provided. Methods include etching a target material of a semiconductor substrate by flowing one or more plasma precursors through a microwave applicator into a remote plasma region of a semiconductor processing chamber. Generating a remote plasma within the remote plasma region at a microwave frequency, where the generated remote plasma comprises a density of greater than 1×1010 per cm3, an ion energy of less than or about 50 eV, or a combination thereof. Flowing the plasma effluents into a processing region of the semiconductor processing chamber. The microwave applicator includes a resonator body and a plate, where the resonator body is formed from or coated with a first dielectric material and the plate is formed from or coated with a second dielectric material.

Abstract: Exemplary semiconductor processing systems may include a chamber body having a bottom plate. The systems may include a substrate support disposed within the chamber body. The substrate support may include a support plate and a shaft. The shaft may include a cooling hub that extends through the bottom plate. The shaft may include a ground shaft that is seated atop the cooling hub. The ground shaft may include a ceramic material. The systems may include an inner isolator coupled with a bottom of the support plate. The inner isolator may define an aperture therethrough that receives the shaft. The systems may include an outer isolator that is seated atop the inner isolator. Each of the inner isolator and the outer isolator may include a ceramic material.

Abstract: Exemplary chemical mechanical cleaning systems may include a carrier head. The systems may include a motor that is coupled with the carrier head. The motor may be operable to rotate the carrier head about a central axis of the carrier head. The systems may include a two-stage downforce actuator that is operable to vertically translate the carrier head and the motor between a raised position and a cleaning position. The downforce actuator may include a first stage that includes a linear actuator that is operable to vertically translate the carrier head between the raised position and at least an upper 50% of a vertical travel distance between the raised and cleaning positions. The downforce actuator may include a second stage that includes an expandable flexure that is operable to vertically translate the carrier head between the cleaning position and no greater than a lower 50% of the vertical distance.

Abstract: Exemplary substrate support assemblies may include a support plate that comprises a substrate support surface. The assemblies may include a support stem coupled with the support plate. A channel may be defined through at least a portion of a length of the support stem and extends through the substrate support surface. A temperature sensor assembly may be disposed within the channel. The temperature sensor assembly may include a light pipe disposed within the channel such that a top end of the light pipe extending through at least a portion of the support plate. The temperature sensor assembly may include a sensor that is coupled with a bottom end of the light pipe.

Abstract: Embodiments of the present technology may include semiconductor processing methods and systems. Methods and systems may include providing a substrate to a processing region of a semiconductor processing chamber, where the substrate includes one or more alternating pairs of a semiconductor material layer and a sacrificial material layer. Methods include forming one or more vertically extending features through the one or more alternating pairs of semiconductor material layer and sacrificial material layer, forming one or more sidewalls having alternating exposed lateral ends of the semiconductor material and the sacrificial material. Methods include forming a protective material layer over the exposed lateral ends of the semiconductor material layer. Methods include laterally recessing at least a portion of the sacrificial material layer from the one or more vertically extending features and trimming a portion of the semiconductor material layer adjacent to the one or more vertically extending features.

Abstract: Exemplary anneal chambers may include a base that defines a chamber interior. The base may include a cooling plate within the chamber interior. The base and the cooling plate may be integral with one another. The chambers may include a lid that is coupled with the base. The chambers may include a heater plate mounted in the chamber interior alongside the cooling plate. The chambers may include a transfer hoop movably coupled within the chamber interior. The base may define a first transfer hoop recess about at least a portion of the heater plate. The base may define a second transfer hoop recess about at least a portion of the cooling plate.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

Abstract: Exemplary semiconductor processing systems may include a chamber body having sidewalls and a base. The semiconductor processing systems may include a substrate support extending through the base of the chamber body. The substrate support may include a support plate. The substrates support may include a shaft coupled with the support plate. The semiconductor processing systems may include a liner positioned within the chamber body and positioned radially outward of a peripheral edge of the support plate. An inner surface of the liner may include an emissivity texture.

Abstract: Printable resin precursor compositions and polishing articles including printable resin precursors are provided. Printable resin precursors include a curable precursor formulation having a viscosity of less than or about 15 cP at 70° which include at least one urethane acrylate oligomer, at least one reactive monomer, and a photoinitiator. The curable precursor formulation exhibits an ultimate tensile strength measured in mPa and an elongation at break (%), where a product of the ultimate tensile strength and the elongation at break is greater than or about 2,000.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

Abstract: An electronic device manufacturing system includes a mainframe including a transfer chamber and facets defining side walls of the transfer chamber. The facets include first facet, second facet, third facet, and fourth facet that form the transfer chamber. The first facet has a first number of substrate access ports. The second facet has a second number of substrate access ports. A first substrate access port of the first facet has a first side dimension and a second substrate access port of the second facet has a second side dimension that is different from the first side dimension. The second facet is adjacent to the first facet. The third facet is adjacent to the second facet. The fourth facet has the second number of substrate access ports. The second number of substrate access ports is different than the first number of substrate access ports.

Abstract: The enclosed disclosure relates to a method and apparatus for depositing functionalized nanoparticles within a semiconductor structure in order to create a nano-layer capable of enhancing imaging and contrast, The semiconductor structure can include any type of VNAND structure or 3D structure, The nanoparticles are formed in high-aspect ratio trenches of the structure and form a nano-layer. The functionalized nanoparticles comprise synthesized nanoparticles as well as organic molecules. The organic molecules are chosen to selectively bind to certain nanoparticles and surface materials.

Abstract: A neural network is trained for use in a substrate residue classification system by obtaining ground truth residue level measurements of a top layer of a calibration substrate at a plurality of locations, each location at a defined position for a die being fabricated on the substrate. A plurality of color images of the calibration substrate are obtained, each color image corresponding to a region for a die being fabricated on the substrate. A neural network is trained to convert color images of die regions from an in-line substrate imager to residue level measurements for the top layer in the die region.

Abstract: A method and apparatus for growing an oxide layer within a feature of a substrate is described herein. The method is suitable for use in semiconductor manufacturing. The oxide layer is formed by exposing a substrate to both a high pressure oxidant exposure and a lower pressure oxygen containing plasma exposure. The high pressure oxidant exposure is performed at a pressure of greater than 10 Torr, while the lower pressure oxygen containing plasma exposure is performed at a pressure of less than about 10 Torr. The features are high-aspect ratio trenches or holes within a stack of silicon oxide and silicon nitride layers.

Abstract: Exemplary etching methods may include modifying an exposed surface of a layer of metal oxide on a substrate housed in a processing region of a semiconductor processing chamber to produce a modified portion of metal oxide. The methods may include contacting the modified portion of metal oxide with a fluorine-containing precursor. The contacting may produce a metal oxy-fluoride material. The methods may include flowing an etchant precursor into the processing region. The methods may include contacting the metal oxy-fluoride material with the etchant precursor. The methods may include removing the metal oxy-fluoride material.

Abstract: Embodiments of the disclosure relate to methods for selectively removing metal material from the top surface and sidewalls of a feature. The metal material which is covered by a flowable polymer material remains unaffected. In some embodiments, the metal material is formed by physical vapor deposition resulting in a relatively thin sidewall thickness. Any metal material remaining on the sidewall after removal of the metal material from the top surface may be etched by an additional etch process. The resulting metal layer at the bottom of the feature facilitates selective metal gapfill of the feature.

Abstract: A wideband variable impedance load for high volume manufacturing qualification and diagnostic testing of a radio frequency power source, an impedance matching network and RF sensors for generating plasma in a semiconductor plasma chamber for semiconductor fabrication processes. The wideband variable impedance load may comprise a fixed value resistance operable at a plurality of frequencies and coupled with a variable impedance network capable of transforming the fixed value resistance into a wide range of complex impedances at the plurality of frequencies. Response times and match tuning element position repeatability may be verified. Automatic testing, verification and qualification of production and field installed radio frequency power sources for plasma generation are easily performed.

Abstract: A method and apparatus for patterning semiconductor materials using tin-based materials as mandrels, hardmasks, and liner materials are provided. One or more implementations of the present disclosure use tin-oxide and/or tin-carbide materials as hardmask materials, mandrel materials, and/or liner material during various patterning applications. Tin-oxide or tin-carbide materials are easy to strip relative to other high selectivity materials like metal oxides (e.g., TiO2, ZrO2, HfO2, Al2O3) to avoid influencing critical dimensions and generate defects. In addition, tin-oxide and tin-carbide have low refractive index, k-value, and are transparent under 663-nm for lithography overlay.

Abstract: An apparatus for contactless transportation of a carrier is provided. The apparatus includes the carrier, being a substrate carrier or a mask carrier. The apparatus includes a linear reluctance motor for providing both a contactless levitation and a contactless drive of the carrier. The linear reluctance motor includes one or more linear stators defining a transportation track for the carrier. The linear reluctance motor includes a mover attached to the carrier. The linear reluctance motor includes a set of electromagnets and a first magnetic material. The one or more linear stators include the set of electromagnets and the mover includes the first magnetic material, or the mover includes the set of electromagnets and the one or more linear stators include the first magnetic material. The apparatus includes a controller connected to the set of electromagnets.

Abstract: An apparatus for contactless transportation of a carrier is provided. The apparatus includes the carrier, being a substrate carrier or a mask carrier. The apparatus includes a linear reluctance motor for providing both a contactless levitation and a contactless drive of the carrier. The linear reluctance motor includes one or more linear stators defining a transportation track for the carrier. The linear reluctance motor includes a mover attached to the carrier. The linear reluctance motor includes a set of electromagnets and a first magnetic material. The one or more linear stators include the set of electromagnets and the mover includes the first magnetic material, or the mover includes the set of electromagnets and the one or more linear stators include the first magnetic material. The apparatus includes a controller connected to the set of electromagnets.