Abstract: Exemplary methods of semiconductor processing may include delivering a deposition precursor into a processing region of a semiconductor processing chamber. The methods may include depositing a layer of material on a substrate housed in the processing region of the semiconductor processing chamber. The processing region may be maintained at a first pressure during the deposition. The methods may include extending a baffle within the processing region. The baffle may modify a flow path within the processing region. The methods may include forming a plasma of a treatment or etch precursor within the processing region of the semiconductor processing chamber. The processing region may be maintained at a second pressure during the forming. The methods may include treating the layer of material deposited on the substrate with plasma effluents of the treatment precursor. The processes may be cycled any number of times.

Abstract: Exemplary methods of semiconductor processing may include delivering a deposition precursor into a processing region of a semiconductor processing chamber. The methods may include depositing a layer of material on a substrate housed in the processing region of the semiconductor processing chamber. The processing region may be maintained at a first pressure during the deposition. The methods may include extending a baffle within the processing region. The baffle may modify a flow path within the processing region. The methods may include forming a plasma of a treatment or etch precursor within the processing region of the semiconductor processing chamber. The processing region may be maintained at a second pressure during the forming. The methods may include treating the layer of material deposited on the substrate with plasma effluents of the treatment precursor. The processes may be cycled any number of times.

Abstract: Susceptor assemblies comprising a susceptor base and a plurality of pie-shaped skins thereon are described. A pie anchor can be positioned in the center of the susceptor base to hold the pie-shaped skins in place during processing.

Abstract: Substrate supports comprising a plurality of bonded plates forming a single component support body and methods of forming the substrate supports are described. The single component support body has an outer peripheral edge, a top surface and a bottom surface. A pocket is formed in the top surface and has a bottom surface, a depth and an outer peripheral edge. A purge ring is spaced a distance from the outer peripheral edge and comprises at least one opening in the top surface in fluid communication with a purge gas line within the body thickness.

Abstract: Processing methods described herein comprise forming a metal gate film on a narrow feature and a wide feature and depositing a hard mask on the metal gate film. The hard mask forms on the metal gate film at a top, bottom and sidewalls of the wide feature and on a top of the narrow feature to cover the metal gate film. Some processing methods comprise oxidizing the metal gate film on the narrow feature to convert a portion of the metal gate film to a metal oxide film. Some processing methods comprise etching the metal oxide film from the narrow feature to leave a gradient etch profile. Some processing methods comprise filling the narrow feature and the wide feature with a gap fill material comprising one or more of a metal nitride, titanium nitride (TiN) or titanium oxynitride (TiON), the gap fill material substantially free of seams and voids.

Abstract: Systems and methods may be used to produce coated components. Exemplary semiconductor chamber components may include an aluminum alloy comprising nickel and may be characterized by a surface. The surface may include a corrosion resistant coating. The corrosion resistant coating may include a conformal layer and a non-metal layer. The conformal layer may extend about the semiconductor chamber component. The non-metal oxide layer may extend over a surface of the conformal layer. The non-metal oxide layer may be characterized by an amorphous microstructure having a hardness of from about 300 HV to about 10,000 HV. The non-metal oxide layer may also be characterized by an sp2 to sp3 hybridization ratio of from about 0.01 to about 0.5 and a hydrogen content of from about 1 wt. % to about 35 wt. %.

Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may include a nitrogen-containing nucleation layer deposited on the substrate. The methods may include forming a silicon-containing material on at least a first portion of the nitrogen-containing nucleation layer. The methods may include forming a second layer of material on at least a second portion of the nitrogen-containing nucleation layer. The methods may include forming a masking layer on a portion of the second layer of material. The masking layer may cover less than or about 90% of the second layer of material. The methods may include growing the second layer of material through the masking layer. The methods may include coalescing the second layer of material above the masking layer.

Abstract: Embodiments of the disclosure relate to methods for enlarging the opening width of substrate features by reducing the overhang of deposited films. Some embodiments of the disclosure utilize a high power bias pulse to etch the deposited film near the opening of the substrate feature. Some embodiments of the disclosure etch the deposited film without damaging the underlying substrate.

Abstract: Embodiments of the present disclosure generally relate to chemical mechanical polishing (CMP) systems used in the manufacturing of semiconductor devices. In one embodiment, the apparatus includes a polishing module, a retaining ring, wherein the retaining ring includes a protrusion on a radially outward edge, and a plurality of load pins disposed through the retaining ring.

Abstract: A method, a non-transitory computer readable medium, and a system for evaluating an inspection algorithm for inspecting a semiconductor specimen.

Abstract: An apparatus comprises a mounting panel including a top plate having multiple vias and multiple orifices. An internal face of the top plate includes a first cut-out region and channels through which to flow a process fluid. The first cut-out region can be a reservoir in which to contain the process fluid. The multiple vias are adapted for passing the process fluid through the top plate. The multiple orifices are adapted for attaching a plurality of process fluid control components to the mounting panel. An inner plate also has multiple additional vias. The apparatus includes a bottom plate, where the inner plate is compacted between the top plate and the bottom plate to form an integral metallic body in which to contain and flow the process fluid.

Abstract: A carrier head for chemical mechanical polishing includes a housing for attachment to a drive shaft, a membrane assembly beneath the housing with a space between the housing and the membrane assembly defining a pressurizable chamber, and a sensor in the housing configured to measure a distance from the sensor to the membrane assembly.

Abstract: An organic light-emitting diode (OLED) device includes a substrate, a well structure on the substrate with the well structure having a recess with side walls and a floor, a lower metal layer covering the floor and side-walls of the well, an upper conductive layer on the lower metal layer covering the floor of the well and contacting the lower metal layer, the upper conductive layer having outer edges at about an intersection of the side walls and the floor, a dielectric layer formed of an oxide of the lower metal layer covering the side walls of the well without covering the upper conductive layer, a stack of OLED layers covering at least the floor of the well, the upper conductive layer providing an electrode for the stack of OLED layers, and a light extraction layer (LEL) in the well over the stack of OLED layers and the dielectric layer.

Abstract: A robotic object handling system comprises a robot arm, a non-contact sensor, a first station, and a computing device. The computing device is to cause the robot arm to pick up an object on an end effector, cause the robot arm to position the object within a detection area of the non-contact sensor, cause the non-contact sensor to generate sensor data of the object, determine at least one of a rotational error of the object relative to a target orientation or a positional error of the object relative to a target position based on the sensor data, cause an adjustment to the robot arm to approximately remove at least one of the rotational error or the positional error from the object, and cause the robot arm to place the object at the first station, wherein the placed object lacks at least one of the rotational error or the positional error.

Abstract: Embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The sub-pixel circuit includes a plurality of contact overhangs. The plurality of contact overhangs are disposed between adjacent sub-pixels of a sub-pixel circuit to be formed. The contact overhangs are formed over a metal grid exposed through a PDL structure. A cathode is deposited via evaporation deposition to be in contact with the contact overhang. The metal grid is perpendicular to a plurality of metal layers disposed on the substrate.

Abstract: A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting. As such, the amorphous layer may form a doped crystalline layer.

Abstract: Exemplary methods of semiconductor processing may include providing a boron-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. The methods may include thermally reacting the boron-containing precursor and the carbon-containing precursor at a temperature below about 650° C. The methods may include forming a boron-and-carbon-containing layer on the substrate.

Abstract: A fluorescent in-situ hybridization imaging and analysis system includes a flow cell to contain a sample to be exposed to fluorescent probes in a reagent, a fluorescence microscope to obtain sequentially collect a plurality of images of the sample at a plurality of different combinations of imaging parameters, and a data processing system. The data processing system includes an online pre-processing system configured to sequentially receive the images from the fluorescence microscope as the images are collected and perform on-the-fly image pre-processing to remove experimental artifacts of the image and to provide RNA image spot sharpening, and an offline processing system configured to, after the plurality of images are collected, perform registration of images having a same field of view and to decode intensity values in the plurality of images to identify expressed genes.

Abstract: Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a first lid plate seated on the chamber body along a first surface of the first lid plate. The first lid plate may define a plurality of apertures through the first lid plate. The systems may include a plurality of lid stacks equal to a number of apertures of the plurality of apertures. The plurality of lid stacks may at least partially define a plurality of processing regions vertically offset from the transfer region. The systems may include a second lid plate coupled with the plurality of lid stacks. The plurality of lid stacks may be positioned between the first lid plate and the second lid plate. A component of each lid stack of the plurality of lid stacks may be coupled with the second lid plate.

Abstract: A power supply circuit includes a switchable match, including a high voltage bus connectable to a load, a low voltage bus connectable to the load such that the load is in series between the high voltage bus and the low voltage bus, at least two capacitors having a fixed value of capacitance selectively connectable between the high voltage bus and the low voltage bus and a plurality of solid state switches equal in number to the number of capacitors having a fixed value of capacitance connectable between the high voltage bus and the low voltage bus, each switch configured and arranged to selectively connect or disconnect one of the capacitors having a fixed value of capacitance selectively connectable between the high voltage bus and the low voltage bus into electrical communication between the high voltage bus and the low voltage bus, and a variable frequency power supply including a high voltage output connection, the high voltage connection connected to the high voltage bus.