Patents Assigned to Applied Material
  • Patent number: 11094573
    Abstract: Disclosed herein is an electrostatic chuck (ESC) carrier. The ESC carrier may comprise a carrier substrate having a first surface and a second surface opposite the first surface. A first through substrate opening and a second through substrate opening may pass through the carrier substrate from the first surface to the second surface. A first conductor is in the first through substrate opening, and a second conductor is in the second through substrate opening. The ESC carrier may further comprise a first electrode over the first surface of the carrier substrate and electrically coupled to the first conductor, and a second electrode over the first surface of the carrier substrate and electrically coupled to the second conductor. An oxide layer may be formed over the first electrode and the second electrode.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: August 17, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Jingyu Qiao, Qiwei Liang, Viachslav Babayan, Seshadri Ramaswami, Srinivas D. Nemani
  • Patent number: 11094589
    Abstract: Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: August 17, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Yung-Chen Lin, Qingjun Zhou, Ying Zhang, Ho-yung David Hwang
  • Patent number: 11094588
    Abstract: Embodiments of the present disclosure generally relate an interconnect structure formed on a substrate and a method of forming the interconnect structure thereon. In one embodiment, a method of forming an interconnect structure includes forming an opening comprising a via and a trench in an insulating structure formed on a substrate, forming a first passivation layer in the opening, removing a portion of the first passivation layer from the opening, and selectively depositing a first metal containing material in the via.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 17, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Shi You, He Ren, Mehul B. Naik
  • Patent number: 11094511
    Abstract: Embodiments of the present disclosure generally provide an apparatus and methods for processing a substrate. More particularly, embodiments of the present disclosure provide a processing chamber having an enhanced processing efficiency at an edge of a substrate disposed in the processing chamber. In one embodiment, a processing chamber comprises a chamber body defining an interior processing region in a processing chamber, a showerhead assembly disposed in the processing chamber, wherein the showerhead assembly has multiple zones with an aperture density higher at an edge zone than at a center zone of the showerhead assembly, a substrate support assembly disposed in the interior processing region of the processing chamber, and a focus ring disposed on an edge of the substrate support assembly and circumscribing the substrate support assembly, wherein the focus ring has a step having a sidewall height substantially similar to a bottom width.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 17, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Changhun Lee, Michael D. Willwerth, Valentin N. Todorow, Hean Cheal Lee, Hun Sang Kim
  • Patent number: 11090683
    Abstract: Embodiments described herein provide a method of forming a silicon-and-oxygen-containing layer having covalent Si—O—Si bonds by cross-linking terminal silanol groups. The method includes positioning a substrate in a chamber. The substrate has one or more trenches including a width of 10 nanometers (nm) or less, and an aspect ratio of 2:1 or greater. The aspect ratio is defined by a ratio of a depth to the width of the one or more trenches. A silicon-and-oxygen-containing layer is disposed over the one or more trenches. The silicon-and-oxygen-containing layer has terminal silanol groups. The substrate is heated, and the silicon-and-oxygen-containing layer is exposed to an ammonia or amine group-containing precursor distributed across a process volume.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 17, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Martin Jay Seamons, Byung Kook Ahn, Jingmei Liang
  • Patent number: 11094544
    Abstract: Processing methods comprising selectively orthogonally growing a first material through a mask to provide an expanded first material are described. The mask can be removed leaving the expanded first material extending orthogonally from the surface of the first material. Further processing can create a self-aligned via.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: August 17, 2021
    Assignee: Applied Materials, Inc.
    Inventors: David Thompson, Benjamin Schmiege, Jeffrey W. Anthis, Abhijit Basu Mallick, Susmit Singha Roy, Ziqing Duan, Yihong Chen, Kelvin Chan, Srinivas Gandikota
  • Publication number: 20210249415
    Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.
    Type: Application
    Filed: January 27, 2021
    Publication date: August 12, 2021
    Applicant: Applied Materials, Inc.
    Inventors: CHANG SEOK KANG, Tomohiko Kitajima, Nitin K. Ingle, Sung-Kwan Kang
  • Patent number: 11088005
    Abstract: A substrate support assembly includes a ceramic puck and a thermally conductive base having an upper surface that is bonded to the ceramic puck. The thermally conductive base includes a plurality of thermal zones and a thermally managed material embedded in the thermally conductive base at the upper surface of the thermally conductive base in one or more of the plurality of thermal zones. The thermally managed material has different thermal conductive properties along a first direction and a second direction. The thermally conductive base further includes a plurality of thermal isolators that extend from the upper surface of the thermally conductive base towards a lower surface of the thermally conductive base between two or more of the plurality of thermal zones without contacting the lower surface of the thermally conductive base. Each of the plurality of thermal isolators provides a degree of thermal isolation.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: August 10, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Vijay D. Parkhe, Konstantin Makhratchev, Jason Della Rosa, Hamid Noobakhsh, Brad L. Mays, Douglas A. Buchberger, Jr.
  • Patent number: 11084143
    Abstract: A method of fabricating a polishing pad using an additive manufacturing system includes depositing successive layers by droplet ejection to form the polishing pad. The polishing pad includes a polishing surface having one or more partitions separated by one or more grooves. Depositing a layer of the successive layers includes dispensing first regions corresponding to edges of the one or more partitions by a first droplet ejection process. After curing the first regions, a second region corresponding to interior of the one or more partitions is dispensed between the edges by a different second droplet ejection process.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: August 10, 2021
    Assignee: Applied Materials, Inc.
    Inventor: Daniel Redfield
  • Patent number: 11088000
    Abstract: Embodiments may also include a residual chemical reaction diagnostic device. The residual chemical reaction diagnostic device may include a substrate and a residual chemical reaction sensor formed on the substrate. In an embodiment, the residual chemical reaction sensor provides electrical outputs in response to the presence of residual chemical reactions. In an embodiment, the substrate is a device substrate, and the sensor is formed in a scribe line of the device substrate. In an alternative embodiment, the substrate is a process development substrate. In some embodiments, the residual chemical reaction sensor includes, a first probe pad, wherein a plurality of first arms extend out from the first probe pad, and a second probe pad, wherein a plurality of second arms extend out from the second probe pad and are interdigitated with the first arms.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: August 10, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Leonard Tedeschi, Benjamin Schwarz, Changhun Lee, Ping Han Hsieh, Adauto Diaz, Jr., Daniel T. McCormick
  • Patent number: 11087998
    Abstract: A transfer chamber configured to be used during semiconductor device manufacturing is described. Transfer chamber includes at least one first side of a first width configured to couple to one or more substrate transfer units (e.g., one or more load locks or one or more pass-through units), and at least a second set of sides of a second width that is different than the first width, the second set of sides configured to couple to one or more processing chambers. A total number of sides of the transfer chamber is at least seven. Transfers within the transfer chamber are serviceable by a single robot. Process tools and methods for processing substrates are described, as are numerous other aspects.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: August 10, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Michael Robert Rice, Michael Meyers, John J. Mazzocco, Dean C. Hruzek, Michael Kuchar, Sushant S. Koshti, Penchala N. Kankanala, Eric A. Englhardt
  • Patent number: 11087979
    Abstract: Implementations of the present disclosure generally relate to methods and apparatuses for epitaxial deposition on substrate surfaces. More particularly, implementations of the present disclosure generally relate to methods and apparatuses for surface preparation prior to epitaxial deposition. In one implementation, a method of processing a substrate is provided. The method comprises etching a surface of a silicon-containing substrate by use of a plasma etch process, where at least one etching process gas comprising chlorine gas and an inert gas is used during the plasma etch process and forming an epitaxial layer on the surface of the silicon-containing substrate.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 10, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Christopher S. Olsen, Peter Stone, Teng-fang Kuo, Ping Han Hsieh, Manoj Vellaikal
  • Patent number: 11088039
    Abstract: Implementations described herein generally relate to improving silicon wafer manufacturing. In one implementation, a method includes receiving information describing a defect. The method further includes identifying a critical area of a silicon wafer and determining the probability of the defect occurring in the critical area. The method further includes determining, based on the probability, the likelihood of an open or a short occurring as a result of the defect occurring in the critical area. The method further includes providing, based on the likelihood, predictive information to a manufacturing system. In some embodiments, corrective action may be taken based on the predictive information in order to improve silicon wafer manufacturing.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 10, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Raman K. Nurani, Anantha R. Sethuraman, Koushik Ragavan, Karanpreet Aujla
  • Patent number: 11087989
    Abstract: A method for etching silicon at cryogenic temperatures is provided. The method includes forming an inert layer from condensation of a noble gas at cryogenic temperatures on exposed surfaces such as the sidewalls of a feature to passivate the sidewalls prior to the etching process. The method further includes flowing a fluorine-containing precursor gas into the chamber to form a fluorine-containing layer on the inert layer. The method further includes exposing the fluorine-containing layer and the inert layer to an energy source to form a passivation layer on the exposed portions of the substrate and exposing the substrate to ions to etch the substrate.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: August 10, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Alvaro Garcia De Gorordo, Zhonghua Yao, Sunil Srinivasan, Sang Wook Park
  • Patent number: 11084097
    Abstract: A method of additive manufacturing includes storing a plurality of predetermined cell processing recipes, dispensing a layer of a plurality of successive layers of feed material on a platform, receiving data describing an area of the layer of the feed material to fuse, determining a combination of a plurality of non-overlapping cells that substantially cover the area, and sequentially processing the plurality of cells. Each cell processing recipe includes scan path data indicating a path for an energy beam to follow, and different cell processing recipes having different paths for the energy beam. Each cell of the plurality of cells gets an associated cell processing recipe selected from the plurality of predetermined cell processing recipes. Each cell is processed by causing an energy beam to follow the first path for the cell processing recipe associated with the cell.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 10, 2021
    Assignee: Applied Materials, Inc.
    Inventors: David Masayuki Ishikawa, Paul J. Steffas, Ajey M. Joshi
  • Publication number: 20210242016
    Abstract: Exemplary deposition methods may include forming a plasma of a silicon-containing precursor and at least one additional precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include depositing material on the semiconductor substrate to a target thickness. The methods may include halting delivery of the silicon-containing precursor while maintaining the plasma with the one or more precursors. The methods may include purging the processing region of the semiconductor processing chamber.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 5, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Madhu Santosh Kumar Mutyala, Sanjay Kamath, Deenesh Padhi
  • Publication number: 20210240896
    Abstract: A complete, unified material-to-systems simulation, design, and verification method for semiconductor design and manufacturing may include evaluating effects of semiconductor material or process changes on software algorithms. The method may include translating the material or process change into a database of characteristics; generating primitive circuit structures using the database of characteristics; performing an electrical characterization of the primitive circuit structures; providing an output of the electrical characterization to a script to generate compact models; generating a lite version of standard cells; generating a digital system based on the lite version of the standard cells; and evaluating a performance of a software algorithm on the digital system to determine an effect of the material or process change for the semiconductor manufacturing process.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 5, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Bhuvaneshwari Ayyagari, Angada Bangalore Sachid
  • Patent number: 11078568
    Abstract: The present disclosure relates to pumping devices, components thereof, and methods associated therewith for substrate processing chambers. In one example, a pumping ring for substrate processing chambers includes a body. The body includes an upper wall, a lower wall, an inner radial wall, and an outer radial wall. The pumping ring also includes an annulus defined by the upper wall, the lower wall, the inner radial wall, and the outer radial wall. The pumping ring also includes a first exhaust port in the body that is fluidly coupled to the annulus, and a second exhaust port in the body that is fluidly coupled to the annulus. The pumping ring also includes a first baffle disposed in the annulus adjacent to the first exhaust port, and a second baffle disposed in the annulus adjacent to the second exhaust port.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: August 3, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Kalyanjit Ghosh, David Blahnik, Amit Kumar Bansal, Tuan Anh Nguyen
  • Patent number: 11077536
    Abstract: An apparatus for chemical mechanical polishing includes a rotatable platen having a surface to support a polishing pad, a carrier head to hold a substrate in contact with the polishing pad, and a polishing liquid distribution system. The polishing liquid distribution system includes a dispenser positioned to deliver a polishing liquid to a portion of a polishing surface of the polishing pad, and a first barrier positioned before the portion of the polishing surface and configured to block used polishing liquid from reaching the portion of the polishing surface. The first barrier includes a solid first body having a first flat bottom surface and having a first leading surface configured to contact the used polishing liquid.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: August 3, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Yen-Chu Yang, Stephen Jew, Jianshe Tang, Haosheng Wu, Shou-Sung Chang, Paul D. Butterfield, Alexander John Fisher, Bum Jick Kim
  • Patent number: 11081379
    Abstract: An electronic device manufacturing system may include a factory interface having a controlled environment. The electronic device manufacturing system may also include a load port coupled to the factory interface. The load port may be configured to receive a substrate carrier thereon and may include purge apparatus and a controller. The controller may be configured to operate the load port such that any air located around and between a substrate carrier door and the load port is at least partially or entirely purged, thus reducing or preventing contamination of the controlled environment upon the opening of the substrate carrier door by the load port. Methods of operating a factory interface load port are also provided, as are other aspects.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: August 3, 2021
    Assignee: Applied Materials, Inc.
    Inventor: Paul B. Reuter