Patents Assigned to Applied Material
  • Patent number: 11049740
    Abstract: A mainframe of a device fabrication system includes a base, a plurality of facets on the base, an a lid over the plurality of facets. A first facet of the plurality of facets includes a frame. The base, the lid and the plurality of facets together define an interior volume that includes a robot arm. A first replaceable interface plate is attached to the first frame of the first facet. The first replaceable interface plate includes a plurality of substrate access ports. A first substrate access port of the plurality of substrate access ports is configured to provide access for the robot arm to a first process chamber. A second substrate access port of the plurality of substrate access ports is configured to provide access for the robot arm to a second process chamber.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventor: Michael R. Rice
  • Patent number: 11049529
    Abstract: A memory circuit may include a memory array, and the memory array may include a plurality of data columns. The plurality of data columns may be configured to store data bits and provide data signals when selected by a read operation. The memory array may also include one or more reference columns distributed in the memory array and configured to provide a reference signal. The reference signal may track with process, voltage, and temperature variations that are specific to the memory array, and may be used to remove a common signal component and adjust the signal level to distinguish between logic 0 and logic 1 data signals.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Frank Tzen-Wen Guo, Bhuvaneshwari Ayyagari-Sangamalli, Angada B. Sachid, Blessy Alexander
  • Patent number: 11049887
    Abstract: Embodiments of the present disclosure generally relate to a layer stack including a high K dielectric layer formed over a first dielectric layer and a metal electrode. The high K dielectric layer has a K value of 20 or higher and may be formed as a part of a capacitor, a gate insulating layer, or any suitable insulating layer in electronic devices, such as display devices. The layer stack includes a second dielectric layer disposed on the first dielectric layer and the metal layer, and the high K dielectric layer disposed on the second dielectric layer. The second dielectric layer provides a homogenous surface on which the high K dielectric layer is formed. The homogeneous surface enables the high K dielectric material to be deposited uniformly thereover, resulting in a uniform thickness profile.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Xiangxin Rui, Soo Young Choi, Shinichi Kurita, Yujia Zhai, Lai Zhao
  • Patent number: 11049699
    Abstract: Embodiments of the present disclosure relate to apparatus for improving quality of films deposited on a substrate by a CVD process. More specifically, a branched gas feed assembly uniformly distributes a process gas entering an annular plenum. Each conduit of a first plurality of conduits having substantially equal flow conductance is in fluid communication with one or more conduits of a second plurality of conduits having substantially equal flow conductance. Each conduit of the second plurality of conduits terminates at one of a plurality of outlets. Each outlet of the plurality of outlets is in fluid communication with one or more inlet ports of a plurality of inlet ports formed in the annular plenum. Each inlet port of the plurality of inlet ports is spaced equidistant about a central axis of the annular plenum.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Tejas Ulavi, Amit Kumar Bansal, Nitin Pathak, Ajit Balakrishna
  • Patent number: 11049722
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Patent number: 11049537
    Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: John O. Dukovic, Srinivas D. Nemani, Ellie Y. Yieh, Praburam Gopalraja, Steven Hiloong Welch, Bhargav S. Citla
  • Patent number: 11049696
    Abstract: Embodiments of the present disclosure generally relate to a processing chamber for conformal oxidation of high aspect ratio structures. The processing chamber includes a chamber body with a first side and a second side opposite the first side, and a flow assembly disposed in the first side. The flow assembly includes a flow divider to direct fluid flow away from a center of a substrate disposed in a processing region of the processing chamber. The flow divider includes a crescent shaped first side, a top, and a bottom. The processing chamber also includes a distributed pumping structure located adjacent to the second side. The flow assembly is designed to reduce flow constriction of the radicals, leading to increased radical concentration and flux.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Vishwas Kumar Pandey, Kartik Shah, Christopher S. Olsen, Agus Sofian Tjandra, Hansel Lo, Eric Kihara Shono, Hemantha Raju
  • Patent number: 11047035
    Abstract: Disclosed herein is a poly-crystalline protective coating on a surface of a chamber component. The poly-crystalline protective coating may be deposited by thermal spraying and may comprise cubic yttria and monoclinic yttria. At least one of: (1) the ratio of the cubic yttria to monoclinic yttria, (2) the crystallite size of at least one of the cubic yttria or the monoclinic yttria, (3) the atomic ratio of oxygen (O) to yttria (Y), and/or (4) the dielectric properties of the poly-crystalline protective coating may be controlled to obtain consistent chamber performance when switching coated chamber components within a chamber of interest.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Ramesh Gopalan, Yixing Lin, Tasnuva Tabassum, Siamak Salimian, Yikai Chen, Kevin Papke
  • Patent number: 11047043
    Abstract: Embodiments disclosed herein generally relate to a chamber liner for the high temperature processing of substrates in a processing chamber. The processing chamber utilizes an inert bottom purge flow to shield the substrate support from halogen reactants such that the substrate support may be heated to temperatures greater than about 650 degrees Celsius. The chamber liner controls a flow profile such that during deposition the bottom purge flow restricts reactants and by-products from depositing below the substrate support. During a clean process, the bottom purge flow restricts halogen reactants from contacting the substrate support. As such, the chamber liner includes a conical inner surface angled inwardly to direct purge gases around an edge of the substrate support and to reduce deposition under the substrate support and the on the edge.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Sanjeev Baluja, Ren-Guan Duan, Kalyanjit Ghosh
  • Publication number: 20210189555
    Abstract: Methods for plasma enhanced chemical vapor deposition (PECVD) of silicon carbonitride films are described. A flowable silicon carbonitride film is formed on a substrate surface by exposing the substrate surface to a precursor and a reactant, the precursor having a structure of general formula (I) or general formula (II) wherein R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, and R12 are independently selected from hydrogen (H), substituted or unsubstituted alkyl, substituted or unsubstituted alkoxy, substituted or unsubstituted vinyl, silane, substituted or unsubstituted amine, or halide; purging the processing chamber of the silicon precursor, and then exposing the substrate to an ammonia plasma.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 24, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Mei-Yee Shek, Bhargav S. Citla, Joshua Rubnitz, Jethro Tannos, Chentsau Chris Ying, Srinivas D. Nemani, Ellie Y. Yieh
  • Publication number: 20210189562
    Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing the substrate surfaces to a blocking compound to selectively form a blocking layer on at least a portion of the first surface over the second surface. The substrate is sequentially exposed to a metal precursor with a kinetic diameter in excess of 21 angstroms and a reactant to selectively form a metal-containing layer on the second surface over the blocking layer or the first surface. The relatively larger metal precursors of some embodiments allow for the use of blocking layers with gaps or voids without the loss of selectivity.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 24, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Bhaskar Jyoti Bhuyan, Mark Saly, David Thompson, Tobin Kaufman-Osborn, Kurt Fredrickson, Thomas Knisley, Liqi Wu
  • Publication number: 20210193468
    Abstract: A method of forming a semiconductor structure includes annealing a surface of a substrate in an ambient of hydrogen to smooth the surface, pre-cleaning the surface of the substrate, depositing a high-? dielectric layer on the pre-cleaned surface of the substrate, performing a re-oxidation process to thermally oxidize the surface of the substrate; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-? dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-? dielectric layer.
    Type: Application
    Filed: March 4, 2021
    Publication date: June 24, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Steven C.H. Hung, Lin Dong, Benjamin Colombeau, Johanes F. Swenberg, Linlin Wang
  • Publication number: 20210189564
    Abstract: Exemplary semiconductor processing chamber showerheads may include a dielectric plate characterized by a first surface and a second surface opposite the first surface. The dielectric plate may define a plurality of apertures through the dielectric plate. The dielectric plate may define a first annular channel in the first surface of the dielectric plate, and the first annular channel may extend about the plurality of apertures. The dielectric plate may define a second annular channel in the first surface of the dielectric plate. The second annular channel may be formed radially outward from the first annular channel. The showerheads may also include a conductive material embedded within the dielectric plate and extending about the plurality of apertures without being exposed by the apertures. The conductive material may be exposed at the second annular channel.
    Type: Application
    Filed: February 16, 2021
    Publication date: June 24, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Laksheswar Kalita, Soonam Park, Dmitry Lubomirsky, Tien Fak Tan, LokKee Loh, Saravjeet Singh, Tae Won Kim
  • Patent number: 11043372
    Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of high-density films for patterning applications. In one implementation, a method of processing a substrate is provided. The method includes flowing a hydrocarbon-containing gas mixture into a processing volume of a process chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.5 mTorr and about 10 Torr. The method further includes generating a plasma at the substrate level by applying a first RF bias to the electrostatic chuck to deposit a diamond-like carbon film on the substrate. The diamond-like carbon film has a density greater than 1.8 g/cc and a stress less than ?500 MPa.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 22, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Eswaranand Venkatasubramanian, Samuel E. Gottheim, Yang Yang, Pramit Manna, Kartik Ramaswamy, Takehito Koshizawa, Abhijit Basu Mallick, Srinivas Gandikota
  • Patent number: 11043415
    Abstract: In one implementation, a method of forming a cobalt layer on a substrate is provided. The method comprises forming a barrier and/or liner layer on a substrate having a feature definition formed in a first surface of the substrate, wherein the barrier and/or liner layer is formed on a sidewall and bottom surface of the feature definition. The method further comprises exposing the substrate to a ruthenium precursor to form a ruthenium-containing layer on the barrier and/or liner layer. The method further comprises exposing the substrate to a cobalt precursor to form a cobalt seed layer atop the ruthenium-containing layer. The method further comprises forming a bulk cobalt layer on the cobalt seed layer to fill the feature definition.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: June 22, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Zhiyuan Wu, Nikolaos Bekiaris, Mehul B. Naik, Jin Hee Park, Mark Hyun Lee
  • Patent number: 11043375
    Abstract: A method of forming a transparent carbon layer on a substrate is provided. The method comprises generating an electron beam plasma above a surface of a substrate positioned over a first electrode and disposed in a processing chamber having a second electrode positioned above the first electrode. The method further comprises flowing a hydrocarbon-containing gas mixture into the processing chamber, wherein the second electrode has a surface containing a secondary electron emission material selected from a silicon-containing material and a carbon-containing material. The method further comprises applying a first RF power to at least one of the first electrode and the second electrode and forming a transparent carbon layer on the surface of the substrate.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 22, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Yang Yang, Eswaranand Venkatasubramanian, Kartik Ramaswamy, Kenneth S. Collins, Steven Lane, Gonzalo Monroy, Lucy Zhiping Chen, Yue Guo
  • Patent number: 11043379
    Abstract: Methods for depositing an amorphous carbon layer on a substrate are described. A substrate is exposed to a carbon precursor having a structure of Formula (I). Also described are methods of etching a substrate, including forming an amorphous carbon hard mask on a substrate by exposing the substrate to a carbon precursor having the structure of Formula (I).
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: June 22, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Pramit Manna, Abhijit Basu Mallick
  • Patent number: 11043361
    Abstract: The disclosure pertains to a capacitively coupled plasma source in which VHF power is applied through an impedance-matching coaxial resonator having a symmetrical power distribution.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 22, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Igor Markovsky, Zhigang Chen, James D. Carducci, Kenneth S. Collins, Shahid Rauf, Nipun Misra, Leonid Dorf, Zheng John Ye
  • Patent number: 11043357
    Abstract: A supply unit for driving an electrode of a charged particle beam column, the supply unit includes a first amplifier and a second amplifier that are configured to receive an input signal, an output of the first amplifier is coupled, via the first resistor, to a signal line of the coaxial cable, an output of the second amplifier is coupled, via the second resistor, to a main shield of the coaxial cable, one port of the first amplifier and one port of the second amplifier are coupled to a power supply return port. The signal line is configured to provide a first driving signal to an that is coupled between the signal line and the power supply return port.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: June 22, 2021
    Assignee: Applied Materials Israel Ltd.
    Inventor: Pavel Margulis
  • Patent number: 11043360
    Abstract: A gas distribution plate assembly for a processing chamber is provided that in one embodiment includes a body made of a metallic material, a base plate comprising a silicon infiltrated metal matrix composite coupled to the body, and a perforated faceplate comprising a silicon disk coupled to the base plate by a bond layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 22, 2021
    Assignee: Applied Materials, Inc.
    Inventors: James D. Carducci, Kenneth S. Collins, Kartik Ramaswamy, Michael R. Rice, Richard Charles Fovell, Vijay D. Parkhe