Abstract: The polishing pad for a chemical mechanical polishing apparatus, and a method of making the same. The polishing pad has a covering layer with a polishing surface and a backing layer which is adjacent to the platen. A first opening in the covering layer with a first cross-sectional area and a second opening in the backing layer with a second, different cross-sectional area form an aperture through the polishing pad. A substantially transparent polyurethane plug is positioned in the aperture, and an adhesive material fixes the plug in the aperture.

Abstract: A polishing method usable in an apparatus including a rotatable member rotatable about a first axis, at least one substrate head assembly supported on said rotatable member, and at least two polishing surfaces arranged below said rotatable member at respective angular positions about said first axis is described. In one implementation, a substrate can be mounted onto a first one of said at least one substrate head assembly. The rotatable member can be rotated to a position so that the substrate overlies a selected one of the polishing surfaces. The substrate can be engaged with said selected polishing surface and relative linear movement imparted between the selected polishing surface and the first substrate head assembly, while the substrate is engaged with the selected polishing surface.

Abstract: The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 ?/min.

Abstract: The present invention provides a method of electron beam testing of liquid crystal displays comprising non-uniform electrodes having a conductive portion and a dielectric portion. In accordance with methods of the present invention, the diameter of the electron beam is increased so that the beam is less focused, i.e., enlarged or “blurred,” over a non-uniform electrode area. The diameter of the beam is increased so that the beam generates secondary electrons from the conductive portion of the non-uniform electrode area. The configured test beam may be circular, elliptical, or other suitable shapes.

Abstract: A carrier head for chemical mechanical polishing of a substrate includes a base and a flexible membrane extending beneath the base. The flexible membrane includes a central portion with an outer surface providing a substrate receiving surface, a perimeter portion connecting the central portion to the base, and at least one flap extending from an inner surface of the central portion. The flap divides a volume between the flexible membrane and the base into a plurality of chambers, and the flap includes a laterally extending first section and an angled second section extending beneath the first section and connecting the laterally extending first section to the central portion.

Abstract: A carrier head for chemical mechanical polishing that has a base having at least a portion formed of a polymer, a mounting assembly connected to the base having a surface for contacting a substrate, a retainer secured to the portion of the base to prevent the substrate from moving along the surface, and a dampening material secured between the retainer and the base.

Abstract: One embodiment of the present invention is a method for fabricating a low-k dielectric film that included steps of: (a) chemical vapor depositing a lower-k dielectric film; and (b) e-beam treating the lower-k dielectric film.

Abstract: A semiconductor substrate centering mechanism includes a plurality of substrate support pins, each pin having a top surface. The top surfaces of the pins define a plane in which the substrate is supported. Each pin has a tab mounted eccentrically at the top surface of the pin. The tabs extend upwardly relative to the top surfaces of the pins. The centering mechanism further includes a pin rotation mechanism adapted to rotate each pin. The pin rotation mechanism rotates the pins between a first position in which the tabs define an envelope that is larger than a circumference of the substrate and a second position in which the tabs define a centered position for the substrate. A telescoping arrangement of nesting shield segments may also be provided for each pin to prevent processing fluid from reaching a shaft of the pin.

Abstract: Embodiments of the present invention relate to an apparatus and method of annealing substrates in a thermal anneal chamber and/or a plasma anneal chamber before electroless deposition thereover. In one embodiment, annealing in a thermal anneal chamber includes heating the substrate in a vacuum environment while providing a gas, such as noble gases, hydrogen gas, other reducing gases, nitrogen gas, other non-reactive gases, and combinations thereof. In another embodiment, annealing in a plasma chamber comprises plasma annealing the substrate in a plasma, such as a plasma from an argon gas, helium gas, hydrogen gas, and combinations thereof.

Abstract: A method for igniting a plasma in a semiconductor process chamber is provided herein. In one embodiment, a method for igniting a plasma in a semiconductor substrate process chamber having an electrically isolated anode, wherein the plasma has failed to ignite upon applying a plasma ignition voltage to a cathode of the process chamber, includes the steps of reducing the magnitude of the voltage applied to the cathode; reapplying the plasma ignition voltage to the cathode; and monitoring the process chamber to determine if the plasma has ignited. The step of monitoring the process chamber may have a duration of a first period of time. The step of reducing the magnitude of the voltage applied to the cathode may have a duration of a second period of time. The steps of reducing the cathode voltage magnitude and reapplying the plasma ignition voltage may be repeated until a plasma ignites.

Abstract: A method for forming sidewall spacers on a gate stack by depositing one or more layers of silicon containing materials using PECVD process(es) on a gate structure to produce a spacer having an overall k value of about 3.0 to about 5.0. The silicon containing materials may be silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, carbon doped silicon nitride, nitrogen doped silicon oxycarbide, or combinations thereof. The deposition is performed in a plasma enhanced chemical vapor deposition chamber and the deposition temperature is less than 450° C. The sidewall spacers so produced provide good capacity resistance, as well as excellent structural stability and hermeticity.

Abstract: An implanter provides two-dimensional scanning of a substrate relative to an implant beam so that the beam draws a raster of scan lines on the substrate. The beam current is measured at turnaround points off the substrate and the current value is used to control the subsequent fast scan speed so as to compensate for the effect of any variation in beam current on dose uniformity in the slow scan direction. The scanning may produce a raster of non-intersecting uniformly spaced parallel scan lines and the spacing between the lines is selected to ensure appropriate dose uniformity.

Abstract: Generally, a substrate support member for supporting a substrate is provided. In one embodiment, a substrate support member for supporting a substrate includes a body coupled to a lower shield. The body has an upper surface adapted to support the substrate and a lower surface. The lower shield has a center portion and a lip. The lip is disposed radially outward of the body and projects towards a plane defined by the first surface. The lip is disposed in a spaced-apart relation from the body. The lower shield is adapted to interface with an upper shield disposed in a processing chamber to define a labyrinth gap that substantially prevents plasma from migrating below the member. The lower shield, in another embodiment, provides the plasma with a short RF ground return path.

Abstract: We have discovered a method of providing a thin, approximately from about 2 ? to about 100 ? thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the TaN seed layer exhibits low resistivity, in the range of 30 ??cm and can be used as a low resistivity barrier layer in the absence of an alpha tantalum layer. In one embodiment of the method, a TaN film is altered on its surface to form the TaN seed layer. In another embodiment of the method, a Ta film is altered on its surface to form the TaN seed layer.

Abstract: A method of detecting defects in a patterned substrate includes positioning a charged-particle-beam optical column relative to a patterned substrate, the charged-particle-beam optical column having a field of view (FOV) with a substantially uniform resolution over the FOV; operating the charged-particle-beam optical column to acquire images of a region of the patterned substrate lying within the FOV by scanning the charged-particle beam over the patterned substrate; and comparing the acquired images to a reference to identify defects in the patterned substrate.

Abstract: A method and apparatus for cleaning, rinsing and Marangoni drying substrates is provided. A line of fluid is sprayed along a substrate surface forming an air/fluid interface line, and a line of drying vapor is supplied to the interface line to achieve Marangoni drying. Thus, a large portion of the substrate is simultaneously dried. A preferred apparatus employs a tank of cleaning and/or rinsing fluid. Above the tank fluid a source of rinsing fluid directs rinsing fluid to the surface of a substrate forming a meniscus on the substrate surface as the substrate is lifted from the cleaning fluid, and a drying vapor source directs drying vapor to the meniscus. The drying vapor lowers the surface tension of the meniscus, inducing a Marangoni flow of rinsing fluid from the substrate's surface, and thereby drying the substrate. The cleaning fluid tank has a substrate receiving and cleaning portion and a substrate rinsing portion.

Abstract: A dual damascene trench etching process includes a two-step BARC etching process, a first BARC etch step using a fluorocarbon-based plasma, and a second BARC etch step using an O2/N2-based plasma. The first BARC etch step removes a first portion of the BARC covering a dielectric stack using a fluorocarbon-based plasma. The second BARC etch step removes a second portion of the BARC covering the dielectric stack using a O2/N2 based plasma. The dual damascene trench etching process may further include a BARC etch back process to remove a further portion of the BARC not covering the dielectric stack. The dual damascene trench etching process further includes a low-k dielectric etching process that etches trenches in a low-k dielectric layer in the dielectric stack and that avoids the use of argon in order to prevent facet formation.

Abstract: A method of fabricating quantum features on a substrate from a layer of material selected from materials identified in the III-V periodic groups (e.g., silicon (Si), InP, Si—Ge, and the like) uses sequentially two patterned masks, each mask includes an elongated mask pattern disposed substantially orthogonal to the elongated pattern of the other mask. In one embodiment, the method forms on a semiconductor wafer a plurality of quantum dots having topographic dimensions of about 30 nm or less. In another embodiment, the invention may be halted after a first etch process to form quantum lines.

Abstract: Methods and apparatus for controlling the critical dimensions and monitoring the phase shift angles of photomasks. Critical dimensions measurement data before wafer processing and after wafer processing are collected by an integrated metrology tool to adjust the process recipe, to determine if the critical dimensions are in specification and to determine if additional etching is required. Phase shift angle and uniformity across substrate measurement after wafer processing are collected by an integrated metrology tool to determine if the phase shift angle and its uniformity are in specification. The real time process recipe adjustment and determination if additional etching is requires allow tightening of the process control. The phase shift angle and uniformity monitoring allows in-line screening of phase shift photomasks.

Abstract: A method and apparatus for etching material layers with high uniformity of a lateral etch rate across a substrate using a gas mixture that includes a passivation gas. The passivation gas is provided to a peripheral region of the substrate to passivate sidewalls of the structures being etched.