Abstract: One or more embodiments of the disclosure are directed to methods of forming structures that are useful for FEOL and BEOL processes. Embodiments of the present disclosure advantageously provide methods of depositing a gapfill material, such as titanium nitride (TiN), in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide seam-free high-quality TiN films to fill high AR trenches with small dimensions. Embodiments of the present disclosure advantageously provide methods of filling 3D structures, such as FinFETs, GAAs, and the like, with a gapfill material without creating a seam. One or more embodiments include selective deposition processes using a carbon (C) layer in order to provide seam-free TiN gapfill in 3D structures, such as GAA devices.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

Abstract: Methods of semiconductor processing may include forming plasma effluents of a hydrogen-and-fluorine-containing precursor. The plasma effluents may then contact a silicon-containing hardmask material and a photoresist material. The silicon-containing hardmask material can overlay an organic material overlaying a substrate in a processing region of a semiconductor processing chamber. Etching the silicon-containing hardmask material with the plasma effluents while the photoresist material with the plasma effluents. The silicon-containing hardmask material can be etched at a selectivity greater than or about 10 relative to the photoresist material. A temperature in the processing region can be maintained at about ?20° C. or less.

Abstract: A system may include a gimbal defining a plurality of pockets, where each pocket may include a first portion and a second portion that extends between the first portion and a base of the pocket. The second portion may have a greater diameter than the first portion. The system may include a plurality of conditioning disks, where each conditioning disk is seated within the first portion of a respective pocket. The system may include a plurality of gaskets, where each gasket is seated within the second portion of a respective pocket. The system may include a plurality o-rings, each o-ring disposed between a peripheral edge of one of the plurality of conditioning disks and a lateral wall of one of the plurality of pockets. The system may include a plurality of shoulder screws for coupling the gimbal with one of the plurality of gaskets and a conditioning disk.

Abstract: A semiconductor device may include a substrate. The semiconductor device may also include a dielectric material characterized, at least in part, by a dielectric constant. The semiconductor device may include a metallic pathway formed in the dielectric material. The semiconductor device may include a region about the metallic pathway of the semiconductor device may include a plurality of air gaps within the dielectric material and arranged three-dimensionally throughout the region, where the region may include a lower dielectric constant than the dielectric constant of the dielectric material.

Abstract: Embodiments of the present technology may include semiconductor processing methods and systems. Methods and systems may include providing a substrate to a processing region of a semiconductor processing chamber, where the substrate includes one or more alternating pairs of a semiconductor material layer and a sacrificial material layer. Methods include forming one or more vertically extending features through the one or more alternating pairs of semiconductor material layer and sacrificial material layer, forming one or more sidewalls having alternating exposed lateral ends of the semiconductor material and the sacrificial material. Methods include forming a protective material layer over the exposed lateral ends of the semiconductor material layer. Methods include laterally recessing at least a portion of the sacrificial material layer from the one or more vertically extending features and trimming a portion of the semiconductor material layer adjacent to the one or more vertically extending features.

Abstract: Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a bottom plate coupled with a bottom surface of the chamber body. The chambers may include a substrate support assembly disposed within the chamber body. The substrate support assembly may include a support plate and a support stem coupled with the support plate. The chambers may include a mounting bracket that couples the support stem with a lower surface of the bottom plate. The chambers may include a plurality of tilt actuators. Each of the tilt actuators may couple the mounting bracket with the lower surface of the bottom plate. Each of the tilt actuators may be operable to adjust a vertical distance between the lower surface of the bottom plate and the mounting bracket at a mounting site of the respective tilt actuator to adjust a planarity of the support plate relative to the bottom plate.

Abstract: Exemplary carrier heads for a chemical mechanical polishing apparatus may include a carrier body. The carrier heads may include a flexible membrane coupled with the carrier body. The flexible membrane may include a substrate-receiving surface that faces away from the carrier body. The substrate-receiving surface may include a plurality of gripping elements that protrude away from the substrate-receiving surface. Each of the plurality of gripping elements may have a maximum lateral dimension that is no greater than 2 mm.

Abstract: Exemplary substrate processing system faceplates may include a plate that is characterized by a first surface and a second surface opposite the first surface. The second surface may define a plurality of recesses that extend through a portion of a thickness of the plate. The plate may define a plurality of apertures through the thickness of the plate. Each aperture may extend through a bottom surface of one recess of the plurality of recesses. Each recess may have a greater diameter than the aperture extending through the bottom surface of the recess. The faceplate may include a plurality of shape-memory actuators. Each shape-memory actuator may be seated within a respective one of the plurality of recesses. Each shape-memory actuator may define an actuator aperture. A diameter of the actuator aperture each shape memory actuator may be variable.

Abstract: Exemplary chemical mechanical cleaning systems may include a carrier head. The systems may include a motor that is coupled with the carrier head. The motor may be operable to rotate the carrier head about a central axis of the carrier head. The systems may include a two-stage downforce actuator that is operable to vertically translate the carrier head and the motor between a raised position and a cleaning position. The downforce actuator may include a first stage that includes a linear actuator that is operable to vertically translate the carrier head between the raised position and at least an upper 50% of a vertical travel distance between the raised and cleaning positions. The downforce actuator may include a second stage that includes an expandable flexure that is operable to vertically translate the carrier head between the cleaning position and no greater than a lower 50% of the vertical distance.

Abstract: A semiconductor processing chamber may include a pedestal configured to support a substrate during a plasma-enhanced chemical-vapor deposition (PECVD) process that forms a film on a surface of the substrate. The chamber may also include one or more internal meshes embedded in the pedestal. The one or more internal meshes may be configured to deliver radio-frequency (RF) power to a plasma in the semiconductor processing chamber during the PECVD process. An outer diameter of the one or more internal meshes may be less that a diameter of the substrate. The chamber may further include an RF source configured to deliver the RF power to the one more internal meshes. This configuration may reduce arcing within the processing chamber.

Abstract: Exemplary electroplating systems may include a vessel. The systems may include a head that is configured to hold a substrate. The head may be positionable within an interior of the vessel. The systems may include a spray jet array disposed within the interior of the vessel. The spray jet array may include a plate defining a plurality of apertures through a thickness of the plate. The systems may include at least one fluid pump that is fluidly coupled with an inlet end of each of the plurality of apertures.

Abstract: Printable resin precursor compositions and polishing articles including printable resin precursors are provided. Printable resin precursors include a curable precursor formulation having a viscosity of less than or about 15 cP at 70° which include at least one urethane acrylate oligomer, at least one reactive monomer, and a photoinitiator. The curable precursor formulation exhibits an ultimate tensile strength measured in mPa and an elongation at break (%), where a product of the ultimate tensile strength and the elongation at break is greater than or about 2,000.

Abstract: Exemplary semiconductor processing systems may include a chamber body having sidewalls and a base. The semiconductor processing systems may include a substrate support extending through the base of the chamber body. The substrate support may include a support plate. The substrates support may include a shaft coupled with the support plate. The semiconductor processing systems may include a liner positioned within the chamber body and positioned radially outward of a peripheral edge of the support plate. An inner surface of the liner may include an emissivity texture.

Abstract: Semiconductor processing systems and methods for increased etch selectivity and rate are provided. Methods include etching a target material of a semiconductor substrate by flowing one or more plasma precursors through a microwave applicator into a remote plasma region of a semiconductor processing chamber. Generating a remote plasma within the remote plasma region at a microwave frequency, where the generated remote plasma comprises a density of greater than 1×1010 per cm3, an ion energy of less than or about 50 eV, or a combination thereof. Flowing the plasma effluents into a processing region of the semiconductor processing chamber. The microwave applicator includes a resonator body and a plate, where the resonator body is formed from or coated with a first dielectric material and the plate is formed from or coated with a second dielectric material.

Abstract: Printable resin precursor compositions and polishing articles including printable resin precursors are provided. Printable resin precursors include a curable precursor formulation having a viscosity of less than or about 15 cP at 70° which include at least one urethane acrylate oligomer, at least one reactive monomer, and a photoinitiator. The curable precursor formulation exhibits an ultimate tensile strength measured in mPa and an elongation at break (%), where a product of the ultimate tensile strength and the elongation at break is greater than or about 2,000.

Abstract: Exemplary semiconductor processing systems may include a chamber body having a bottom plate. The systems may include a substrate support disposed within the chamber body. The substrate support may include a support plate and a shaft. The shaft may include a cooling hub that extends through the bottom plate. The shaft may include a ground shaft that is seated atop the cooling hub. The ground shaft may include a ceramic material. The systems may include an inner isolator coupled with a bottom of the support plate. The inner isolator may define an aperture therethrough that receives the shaft. The systems may include an outer isolator that is seated atop the inner isolator. Each of the inner isolator and the outer isolator may include a ceramic material.

Abstract: Exemplary substrate support assemblies may include a support plate that comprises a substrate support surface. The assemblies may include a support stem coupled with the support plate. A channel may be defined through at least a portion of a length of the support stem and extends through the substrate support surface. A temperature sensor assembly may be disposed within the channel. The temperature sensor assembly may include a light pipe disposed within the channel such that a top end of the light pipe extending through at least a portion of the support plate. The temperature sensor assembly may include a sensor that is coupled with a bottom end of the light pipe.