Abstract: Identifying hotspots, or regions on the semiconductor designer substrate that are prone to manufacturing defects or performance issues, requires either error-prone techniques like design rule checking, or resource-intensive techniques such as scanning electron microscopy (SEM) imaging. This disclosure describes training and using a model-based architecture to quickly identify a probability of these hotspots at specific locations. The model is scalable and multi-modal, using inputs of different types (images, tabular, timeseries, etc.) from different sources. Detecting the likelihood of a hotspot can be done very efficiently with this model-based solution and can be used to minimize false positives and negatives before employing more time-intensive inspection techniques.

Abstract: Exemplary methods of cleaning a rotor of an electroplating apparatus may include positioning a rotor of an electroplating apparatus into a rinse position. The methods may include rotating the rotor at a rinse speed. The methods may include spraying a rinsing fluid against a surface of the rotor using a rinse nozzle of the electroplating apparatus for a first period of time. The methods may include ceasing the spraying of the rinse fluid. The methods may include rotating the rotor at a dry speed for a second period of time.

Abstract: A method includes obtaining, by a processing device, data indicative of locations of defects of a substrate. The method further includes generating an image indicating the locations of the defects. The method further includes providing the image indicating the locations of the defects to a trained machine learning model. The method further includes obtaining, as output from the trained machine learning model, a classification of the locations of the defects. The method further includes performing a corrective action in view of the output from the trained machine learning model.

Abstract: Embodiments of the disclosure include an apparatus and a method for controlling plasma uniformity by controlling plasma density in the bulk plasma over the center region and circumferential edge region of the substrate. Plasma uniformity can be controlled by use of an RF tuning circuit coupled to one of a plurality of electrodes positioned relative to a substrate during plasma processing. By adjusting the electrical characteristics of at least one of the RF tuning circuits, the effect that the generated RF fundamental frequency and related RF harmonic frequencies have on the plasma processing results can be controlled. Beneficially, the use of one or more of the tuning circuits and methods of using the same may be used to provide individual tuning knobs for controlling reactive neutral species concentration, ion energy and angular distribution, ion directionality and directionality uniformity, and separately controlling ion flux and reactive neutral species uniformity across the surface of the substrate.

Abstract: Embodiments disclosed herein generally relate to in situ monitoring of film growth in processing chambers. In some examples, a sensor assembly for a processing chamber includes a sensor tube including silicon carbide and having an optical path therein and a sensor window including crystalline silicon carbide and having a proximal side coupled to a distal end of the sensor tube. The sensor window covers the optical path, and a distal side of the sensor window facing away from the proximal side is perpendicular to a center axis of the optical path.

Abstract: Exemplary substrate processing chambers may include a chamber body defining a processing region. The chambers may include a backing plate disposed atop the chamber body, a diffuser above the processing region and supported by the backing plate, and a cooling frame disposed between the backing plate and the diffuser. The cooling frame may be coupled with the diffuser. The cooling frame may include a body having one or more fluid inlets and one or more fluid outlets. The body may define an opening. The fluid inlets may be in fluid communication with the one or more fluid outlets via one or more fluid lumens that each extend at least partially about a periphery of the opening. The fluid inlets may be in fluid communication with one or more fluid supply lumens. The fluid outlets may be in fluid communication with one or more fluid return lumens.

Abstract: An electronic device manufacturing system configured to identify, by a processor, a first machine-learning model trained to generate predictive data for a first process chamber and obtain metrology data associated with a substrate produced by a second process chamber. The manufacturing system is further configured to train a second machine-learning model based on the first machine-learning model and the metrology data, wherein the second machine-learning model is trained to generate predictive data associated with the second process chamber.

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.

Abstract: The present disclosure relates to cleaning assemblies, components thereof, and methods associated therewith for substrate processing chambers. In one example, a method includes positioning a pedestal disposed in a substrate processing chamber in a first vertical position for a first time period, directing cleaning fluid into the internal volume of the substrate processing chamber located above the faceplate, diverting a portion of the cleaning fluid to the distribution ring and into the internal volume located below the faceplate by opening up the isolation valve, and positioning the pedestal in one or more additional vertical positions while the isolation valve is opened, the one or more additional vertical positions being different than the first vertical position.

Abstract: Embodiments of the disclosure relate to digital lithography systems and components thereof. Digital lithography systems may include a rotation assembly for an exposure unit, including a kinematic socket configured to support the exposure unit, the kinematic socket having a socket seat and a sphere received in the socket seat, wherein the socket seat is configured to support a load of the exposure unit during translational movement and the sphere is a pivot point for tip and tilt movement; and a motor configured to rotate the one or more exposure unit via the kinematic socket. The rotation assembly may provide a point of contact for the exposure unit together with two additional points of contact that stabilize movement of the exposure unit. Also disclosed are methods of preparation and use of such systems and components.

Abstract: Embodiments of the disclosure relate to techniques and apparatus for reducing out-of-plane distortion (OPD) in a substrate, as well as control of the effects of OPD and the effects that the modifications made to the substrate to correct for the OPD have on subsequent substrate processing operations performed on the substrate. The present embodiments employ novel techniques to reduce the OPD in a substrate without adding or modifying portions of the substrate that will create issues in subsequent substrate fabrication processes.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes combining selective recess of a sacrificial layer and isotropic etching of a silicon layer in order to form a protective cap that will allow the silicon layer of the substrate to be etched without affecting the sacrificial layer.

Abstract: Disclosed herein is a method for determining the endpoint of an etch operation used for forming high aspect ratio features and/or over low open area (<1%) on a substrate in a processing chamber. The method begins by obtaining a reference emission curve. An etch operation is performed on a patterned substrate. A plasma optical emission intensity is measured for each of the etch cycles. A differential curve between the reference emission and the plasma optical emissions is calculated. And endpoint is determined for the etch operation on the first substrate based on an inflection point detection or other unique features through pattern recognition in the differential curve for stopping the etch of the first substrate.

Abstract: In modern advanced electronic packages, such as 2.5D packages, very high communication bandwidth is required to meet the demands of modern artificial intelligence workloads. However, traditional 2.5 D interconnects use 1-2 ?m-micron wide copper traces that are typically implemented in a silicon dioxide dielectric material as individual strip lines or a microstrip of individual transmission lines. These existing copper transmission lines are unable to transmit signals at high frequencies without introducing a significant bit error rate. The modular coaxial bridge described herein can replace these traditional interconnect techniques by the densely packaging a large number of individual coaxial transmission lines into a single modular unit. This coaxial bridge greatly reduces the insertion loss transmissions between dies on an interposer, resulting in transmission speeds greater than 100 Gbps.

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide methods to reduce the resistance of the work function layer of an electronic device, as well as using a low resistivity metal for filling the gate.

Abstract: Methods of manufacturing semiconductor devices are described. The methods include etching a portion of a silicon layer of a transistor to form an opening adjacent to the silicon layer, the silicon layer extending between a source region and a drain region on a substrate; forming a p-type epitaxial liner layer in the opening and on the transistor in the source region and the drain region; an forming an n-type epitaxial gapfill layer on the p-type epitaxial liner layer to form a source and a drain.

Abstract: Methods of manufacturing semiconductor devices are described. The methods include depositing a molybdenum silicide layer directly on a substrate; depositing an interfacial layer directly on the molybdenum silicide layer; and depositing a metal nitride layer directly on the interfacial layer. The interfacial layer includes a metal silicide having a formula of MSix, where M is a metal and x is an integer in a range of from 1 to 3 or a metal silicon nitride having a formula MSiN where M is the metal.

Abstract: Provided are methods of forming a seed layer on a conductive metal layer of a semiconductor device. The method includes exposing the top surface of a substrate to a first reactant and a ruthenium precursor to deposit a seed layer on the top surface of the substrate. The substrate has at least one feature formed in a dielectric layer. The at least one feature defines a gap including sidewalls and a bottom. After deposition of the seed layer, the gap is filled with a metal by a gap filling process.

Abstract: The disclosure relates to a substrate support assembly and apparatus for measuring the temperature of a substrate disposed on the support assembly. In one embodiment, a substrate temperature measurement apparatus includes a substrate support assembly, a probe assembly, and a probe target. The substrate support assembly includes an electrostatic chuck and one or more plates. The probe assembly within the substrate support assembly extends through one or more of the one or more plates. The probe assembly includes an optical probe sensor, an optical fiber coupled to the optical probe sensor, and an insulating sheath surrounding the optical fiber. The probe target includes a phosphor coating, is in contact with the electrostatic chuck, and is spaced from the probe assembly.

Abstract: Embodiments disclosed herein include a plasma source. In an embodiment, a plasma source comprises a dielectric body with a top surface, a bottom surface, and sidewall surfaces. In an embodiment, a plurality of holes pass through the dielectric body, where a first set of holes pass from the top surface to the bottom surface, and a second set of holes pass between opposite sidewall surfaces. In an embodiment, a housing is around the dielectric body, and a monopole antenna extending into the dielectric body.