Abstract: A method of stress management in a substrate, using angled ion implantation to introduced anisotropic stress within the substrate.

Abstract: A method and apparatus for cooling a semiconductor chamber are described herein. A semiconductor chamber component, includes a powered region, a grounded region, and a fluid conduit disposed within the semiconductor chamber component and passing through the powered region and grounded region, the fluid conduit comprising a ceramic material.

Abstract: Embodiments of the present disclosure generally relate to fabricating electronic devices, such as memory devices. In one or more embodiments, a microelectronic device is provided and includes a film stack disposed on a substrate and a patterned hard mask disposed on an upper surface of the film stack. The film stack has a stack thickness and contains a plurality of alternating layers of oxide layers and nitride layers. The microelectronic device also includes a plurality of openings having a depth disposed between a plurality of structures, each structure has a sidewall and each opening has a bottom, the depth is less than the stack thickness, and each opening has an aspect ratio of greater than 50 relative to the depth. The microelectronic device also includes an etch protection liner disposed on the patterned hard mask and the sidewalls.

Abstract: A station for a substrate processing system that includes a magnetic levitation actuator assembly disposed in a first region of the station that is separated from a second region of the station by a membrane. The magnetic levitation actuator assembly is configured to contactlessly convey a carrier disposed in the second region to one or more positions within the second region.

Abstract: A faceplate and fasteners for attaching the faceplate to an ion source are disclosed. The faceplate includes a plurality of channels that open to the side of the faceplate. These channels are an elongated shape such that the channels are larger in one direction than in the orthogonal direction. The channels each terminate in an internal cavity, which has a larger size than the channels. The fasteners may be rods that are shaped such that the proximal ends of the fastener have a bent portion, which can only enter the channel when properly oriented. Once the bent portion is passed through the channel and extends into the internal cavity, the fastener can be rotated so as to secure it in place.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is etched and then crystallized. Epitaxially growth of the source and drain regions then proceeds, with growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

Abstract: Exemplary semiconductor processing methods may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber, the deposition precursors may be or include a tungsten-containing precursor. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the one or more deposition precursors in the processing region. The plasma may be at least partially formed by an RF power operating at less than or about 3,000 W and at a pulsing frequency less than or about 100,000 Hz. The methods may include forming a layer of material on the substrate. The layer of material may be or include a tungsten-containing material.

Abstract: Methods of depositing a molybdenum sulfide film with increased sulfur:molybdenum ratio are described. The methods include pre-cleaning a dielectric material with oxygen radicals prior to formation of a molybdenum sulfide film that has a lower oxygen content than would be formed without the pre-cleaning.

Abstract: Embodiments provided herein generally include apparatus and methods, controlled by flexible tuning algorithms, for generating a plasma in a plasma processing chamber. Flexible communications between equipment of the plasma processing system allows sharing of process information and equipment settings for evaluation and refinement of the tuning algorithms used. This enhances the productivity of batch processing of a plurality of semiconductor wafers during the manufacturing process since the tuning algorithms can be modified on the fly during processing thereof. The tuning algorithms may be recorded, reused and/or modified for controlling future plasma processing.

Abstract: Exemplary methods of semiconductor processing may include etching a first portion of a feature in a substrate disposed within a processing region of a semiconductor processing chamber. The first portion of the feature may at least partially extend through one or more layers of material formed on the substrate. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include generating plasma effluents of the carbon-containing precursor. The methods may include contacting the substrate with the plasma effluents of the carbon-containing precursor. The methods may include forming a carbon-containing material on the substrate. The carbon-containing material may line the first portion of the feature at least partially extending through the one or more layers of material formed on the substrate. The carbon-containing material may be formed in the same chamber where the feature is etched.

Abstract: A load lock including a substrate support device for supporting a substrate, and an indexer coupled to the substrate support device. The substrate support device may take measurements and acquire data to verify features of the supported substrate and an associated manufacturing system. Substrate features that are measured include, substrate temperature, substrate warping, and a substrate presence, absence, or misplacement on the support device. System features that are measured include system vibrations and substrate transfer mechanism calibration data. The substrate support device sensors and communications circuits can be integrated into the substrate support device, through use of an additive manufacturing process in making the substrate support device.

Abstract: A method and controller for processing substrates are described herein. In one example, a method of processing a substrate on a substrate support disposed on a cooling base comprises obtaining a temperature value at a bottom of the substrate support, obtaining a temperature value associated with the cooling base, determining a substrate temperature, and processing the substrate while disposed on the substrate support. The determined substrate temperature is based on, a thermal resistivity characteristic of the substrate support, the temperature value of the bottom of the substrate support, and the temperature value associated with the cooling base.

Abstract: Disclosed herein are methods for direct backside contact formation. In some embodiments, a method may include providing a stack of layers defining a front side and a backside, wherein the front side comprises one or more devices, and forming a plurality of vias in the backside, wherein each via of the plurality of vias extends to a source/drain. The method may further include performing a dopant implant to the backside including into the plurality of vias, wherein the dopant implant is performed at a temperature greater than 300° C., forming a silicide region within each of the source/drains, and forming a backside contact within each of the plurality of vias, wherein the backside contact is formed over the silicide region.

Abstract: Embodiments described herein relate to a device. The device includes a substrate, a plurality of overhang structures disposed over the substrate, and a plurality of sub-pixels. Each overhang structure includes a first structure, a second structure disposed over the first structure, and adjacent overhangs. The first structure includes an upper section and a lower section. The upper section includes a sidewall parallel to a surface normal of the substrate. The lower section includes a top surface with a first width equal to a second width of a lower surface of the upper section and a lower surface of the first structure having a third width greater than the second width of the lower surface of the upper section. The adjacent overhangs are defined by an overhang extension of the second structure extending laterally past the upper surface of the first structure.

Abstract: Methods of depositing titanium silicide (TiSi) in the formation of semiconductor structures are described. The methods include thermal chemical vapor deposition (CVD) in which a semiconductor substrate in a semiconductor processing chamber is exposed to a titanium-containing precursor, a silicon-containing precursor, and hydrogen (H2) to deposit the titanium silicide (TiSi) layer directly on the semiconductor substrate. Methods of selectively depositing titanium silicide (TiSi) in the formation of semiconductor structures, e.g., an n-type transistor and a p-type transistor, are also described.

Abstract: One or more first signals are obtained. The first signals indicate a current shape of an object placed on an end effector. The one or more first signals are compared to one or more second signals that each indicate a predefined shape for a process component on the end effector. A determination is made of whether a current placement of the object on the end effector satisfies a target placement criterion based on the comparison.

Abstract: The present disclosure provides shutter disk systems. The shutter disk systems include a body including a plurality of faces, a base, and a top. The body includes an interior volume. The interior volume includes an interlock region configured to receive at least one shutter disk. The interior volume includes an operation region adjacent to the interlock region, where the operational region is separate from the interlock region by an isolator plate. A shutter disk stack is disposed in the operational region. The shutter disk stack includes at least a storage rack configured to receive two or more shutter disks. A first door is disposed on a face of the plurality of faces proximal to the operational region. A second door is disposed proximal to the interlock region. A third door is disposed proximal to a portion of the interlock region and a portion of the operational region.

Abstract: A semiconductor device that implements artificial neurons and synapses together on the semiconductor device includes a plurality of fins formed on the semiconductor device, and a plurality of gates formed around the plurality of fins to form a plurality of fin field-effect transistors (FinFETs). The plurality of FinFETs may form one or more artificial synapses and one or more artificial neurons. Each of the one or more artificial synapses may include two or more of the plurality of gates. Each of the one or more artificial neurons comprises one of the plurality of gates.

Abstract: Implementations disclosed describe, among other things, a systems and techniques for perform efficient inspection of a semiconductor manufacturing sample. The techniques include collecting optical inspection data for training sample(s) that have a plurality of defects. The techniques further include generating, using the optical inspection data, a training data set that includes descriptions, images, and ground truth classifications for the defects. The techniques further include using the training data set to train a plurality of machine learning (ML) classifiers to generate predicted classifications for the defects in the training sample(s). The techniques further include selecting, using the predicted classifications and the ground truth classifications, one or more ML classifiers that meet one or more accuracy criteria, and using the selected ML classifier(s) to classify defects in the semiconductor manufacturing sample.

Abstract: Some embodiments are directed to a remote plasma system. The remote plasma system may include: a first tube; a second tube; a first isolation component coupled between a first end of the first tube and a first end of the second tube; a second isolation component coupled between a second end of the first tube and a second end of the second tube; and a first capacitive element coupled to the first isolation component.