Abstract: Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. A substrate with a metal surface, a dielectric surface and an aluminum oxide surface has a blocking layer deposited on the metal surface using an alkylsilane.

Abstract: Pull-back selective etching processes for bottom-up selective metal gapfill are described. The processes include depositing a metallic layer on a substrate including a top surface and at least feature having sidewalls and a bottom; depositing a mask layer directly on the metallic layer; exposing the substrate to a first plasma to remove a portion of the mask layer; exposing the substrate to a second plasma to remove a portion of the metallic layer; exposing the substrate to a third plasma to remove any remaining portion of the mask layer; and depositing a conductive material in bottom-up fashion to fill the at least one feature.

Abstract: The present subject matter relates to systems and methods for adjusting the resonant frequency of a resonator coil that is disposed within an enclosure. An adjustable coupling arrangement couples a first end of the resonator coil to the enclosure. The adjustable coupling arrangement is movable to adjust a position of the first end of the resonator coil with respect to the enclosure such that a pitch of the resonator coil is modified.

Abstract: Exemplary methods of semiconductor processing may include i) performing a carbon inhibition operation on a substrate disposed within a processing region of a semiconductor processing chamber. A layer of material may be disposed on the substrate. The layer of material may define one or more features characterized by an aspect ratio of greater than or about 30:1. The methods may include ii) performing a silicon-containing atomic layer deposition (ALD) process. The silicon-containing ALD may deposit a silicon-containing material in the one or more features. The methods may include iii) repeating operations i and ii for a plurality of cycles.

Abstract: A method of modifying an opening in a material layer provided on a substrate to achieve desired critical dimensions may include forming a plurality of openings in a material layer stack formed over a substrate, wherein each opening of the plurality of openings comprises a first side opposite a second side, a first end opposite a second end, and a set of connection areas between the first end and the first and second sides. The method may further include performing a first ion process on the material layer stack to modify one or more dimensions of the set of connection areas, wherein the first ion process comprises directing ions to the material layer stack at a first non-zero angle relative to a normal direction extending from a top surface of the material layer stack.

Abstract: Exemplary methods of semiconductor processing may include i) providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region and may define one or more features. The methods may include ii) contacting the substrate with the silicon-containing precursor to deposit a silicon-containing material that may extend within the features. The methods may include iii) providing an oxygen-containing precursor and a hydrogen-containing precursor to the processing region. The methods may include iv) forming plasma effluents of the oxygen-containing precursor and the hydrogen-containing precursor. The methods may include v) contacting the substrate with the plasma effluents of the oxygen-containing precursor and the hydrogen-containing precursor to convert the silicon-containing material to a silicon-and-oxygen-containing material. The contacting may increase Si—O—Si crosslinking in the silicon-and-oxygen-containing material.

Abstract: Embodiments of the disclosure relate to methods for molybdenum gap fill. The method includes forming a metal layer on a substrate surface with at least one feature formed therein by physical vapor deposition (PVD). The substrate surface is then exposed to a molybdenum halide precursor to remove a portion of the metal layer. A molybdenum precursor and a reductant are used to form a gap fill layer within the at least one feature.

Abstract: Ion beam implantation systems, devices, and methods for adjusting an ion beam. An ion beam implantation system includes a shutter component configured to adjust an ion beam received from an ion beam source and being incident on a wafer plane. The system includes a controller component communicatively coupled to the shutter component. The controller is configured to receive an ion beam implantation recipe and change a size of an aperture of the shutter component based the ion beam implantation recipe and one or more measurements of the ion beam.

Abstract: A chemical mechanical polishing system includes a first polishing station including a first platen to support a first polishing pad, a transfer station to receive a substrate from a robot, a carrier head movable on a predetermined path from the polishing station to the transfer station, a gas flow regulator having an input for a carrier gas, a liquid flow regulator having an input for a cleaning liquid, and a fluid jet cleaner at a position along the predetermined path. The fluid jet cleaner includes an atomizer nozzle including an input port coupled to the gas flow regulator, an injection port coupled to the liquid flow regulator, and an output port positioned to spray the cleaning liquid entrained in the carrier gas onto the substrate held by the carrier head when the carrier head is located above the fluid jet cleaner.

Abstract: Methods for modifying the interface of optical substrates. To achieve desirable optical properties, surface defects need to be removed from the interface layer. In one example, a substrate is exposed to an ion beam then a high temperature bake or laser annealing to correct the interface layer. In another example, a high energy ion beam can be used to remove the interface layer then a new interface layer can be added during a high temperature bake or laser annealing with a protective layer added last. If not removed surface defects in the interface layer may absorb a percentage of light in a single interaction. In a waveguide, light may bounce ten to hundreds of times inside a substrate causing significant light loss. Therefore, removing the surface defects significantly increases waveguide efficiency.

Abstract: A cleaning system includes a blade handling assembly configured to transport and clean a substrate. The blade handling assembly for handling a substrate in the cleaning system includes a gripping assembly including a pair of gripping blades, the blades operable with a gripping actuator to hold a substrate at its edges. The assembly includes a first blade actuator for moving the gripping assembly and substrate between a horizontal and a vertical orientation utilizing a first axis. The assembly includes a second blade actuator for moving the vertically oriented gripping assembly and substrate 180 degrees utilizing a second axis, thereby causing the substrate to face an opposite direction.

Abstract: Embodiments of the present disclosure generally relate to imprint compositions and materials and related processes useful for nanoimprint lithography (NIL). In one or more embodiments, an imprint composition is provided and contains a plurality of passivated nanoparticles, one or more solvents, a surface ligand, an additive, and an acrylate. Each passivated nanoparticle contains a core and one or more shells, where the core contains one or more metal oxides and the shell contains one or more passivation materials. The passivation material of the shell contains one or more silicon-containing compounds.

Abstract: Sealing bodies comprising a first body having a top surface and a bottom surface defining a thickness thereof. An inlet conduit and an outlet conduit are in fluid communication with one or more of the top surface, the bottom surface, or a top channel formed in the top surface or a bottom channel formed in the bottom surface.

Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. Alternating layers of material may be formed on the substrate. One or more recesses may be formed in the alternating layers of material. The methods may include forming a first silicon-containing material. The first silicon-containing material may extend into the one or more recesses formed in the alternating layers of material. The methods may include providing a halogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming a silicon-and-halogen-containing material. The silicon-and-halogen-containing material may overly the first silicon-containing material. The methods may include forming a second silicon-containing material.

Abstract: Apparatus and methods for cooling down a susceptor assembly are described. A heat exchange passage in a susceptor assembly thermal break transfers heat from processing gases that flow through the susceptor assembly to a cooling jacket and cools down the susceptor assembly and associated hardware.

Abstract: Methods and apparatus for processing a substrate are provided. In some embodiments, a method includes: depositing a metal buffer layer on a substrate and within a feature disposed in a dielectric layer of the substrate. The buffer layer is deposited using a first physical vapor deposition (PVD) process at a chamber pressure of less than 500 mTorr while applying less than or equal to 0.08 watts/cm2 of RF bias power to the substrate if the chamber pressure is less than or equal to 3 mTorr and applying less than or equal to 0.8 watts/cm2 of RF bias power to the substrate if the chamber pressure is greater than 3 mTorr. A metal liner layer is deposited atop the buffer layer using a second PVD process at a chamber pressure of less than or equal to 3 mTorr while applying greater than 0.08 watts/cm2 of RF bias power to the substrate.

Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.

Abstract: A method and apparatus for delivering IPA vapor to a substrate processing chamber. In one aspect, the invention includes a controller, a liquid mass flow controller (LMFC) associated with a vaporizer to convert a first fluid to a vapor, a mass flow controller (MFC) associated with the carrier gas, a mixing unit to mix the vapor with the carrier gas to create the predetermined mixture and a drain circuit including a first flow path having a first valve between the mixing unit and a drain, a second flow path having a second valve between the mixing unit and the processing chamber, whereby the first flow path can be opened until the predetermined mixture is reached and thereafter, the second flow path can be opened allowing the predetermined mixture to be delivered to the chamber.

Abstract: A method includes forming a plurality of voids within a substrate along a dicing path by exposing the substrate to a first burst of laser pulses at a first location along the dicing path of a respective waveguide combiner. The substrate has a plurality of waveguides. Each laser pulse within the first burst forms a respective void within a first column at the first location to form the plurality of voids. The method further includes exposing the substrate to a second burst of laser pulses at a second location along the dicing path of the respective waveguide combiner. Each laser pulse within the second burst forms the respective void within a second column at the second location to form the plurality of voids. The first column and the second column are spaced by a pitch between a center of the first column and the second column along the dicing path.

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices and multilayer inner spacers for GAA devices are described. The multilayer inner spacer comprises an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of a substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. In some embodiments, the methods are performed in situ in an integrated deposition and etch processing system.