Abstract: Bottom-fed ampoules for a semiconductor manufacturing precursors and methods of use are described. The ampoules comprise an outer cylindrical wall and an inner cylindrical wall defining a flow channel in between and a bottom wall having a top surface with a plurality of concentric elongate walls, each wall comprising an opening offset from the opening in adjacent walls defining a gas exchange zone through which a carrier gas flows in contact with the precursor.

Abstract: Embodiments of the present disclosure generally relate to inductively coupled plasma sources and plasma processing apparatus. In at least one embodiment, plasma source includes a first sidewall and a gas injection insert defining a plasma source interior volume. The gas injection insert includes a peripheral gas injection port, a second sidewall disposed concentric with the first sidewall, and a center gas injection port. The plasma source includes a first induction coil disposed proximate the first sidewall and disposed around the first sidewall. The plasma source includes a first radio frequency power generator coupled with the first induction coil. The plasma source includes a second induction coil disposed proximate the second sidewall and disposed around the second sidewall. The plasma source includes a second radio frequency power generator coupled with the second induction coil.

Abstract: Methods for filling a substrate feature with a carbon gap fill, while leaving a void, are described. Methods comprise flowing a process gas into a high density plasma chemical vapor deposition (HDP-CVD) chamber, the chamber housing a substrate having at least one feature, the process gas comprising a hydrocarbon reactant, generating a plasma, and depositing a carbon film.

Abstract: Methods and apparatus for depositing a coating on a semiconductor manufacturing apparatus component are provided herein. In some embodiments, a method of depositing a coating on a semiconductor manufacturing apparatus component includes: sequentially exposing a semiconductor manufacturing apparatus component including nickel or nickel alloy to an aluminum precursor and a reactant to form an aluminum containing layer on a surface of the semiconductor manufacturing apparatus component by a deposition process.

Abstract: Methods and apparatus for controlling a semiconductor process leverage phase shifting between at least two RF generators to improve wafer performance parameters. In some embodiments, an apparatus may include a first radio frequency (RF) generator, a second RF frequency generator, a cable connected between the first RF generator and the second RF generator wherein the cable is configured to synchronize the first RF generator and the second RF generator, and an adjustable phase shift assembly with a two-dimensional trace and an adjustable contact point. The adjustable phase shift assembly is connected to the cable and configured to alter at least one water performance parameter by changing a phase shift relationship between the first RF frequency generator and the second RF frequency generator.

Abstract: Embodiments of megasonic cleaning chambers are provided herein. In some embodiments, a megasonic cleaning chamber includes: a chamber body defining an interior volume therein; a substrate support to support a substrate disposed in the interior volume; a supply tube comprising a transparent material configured to direct a cleaning fluid to the substrate support; a megasonic power generator coupled to the supply tube to provide megasonic power to the cleaning fluid; a megasonic transducer coupled to the megasonic power generator and the supply tube to create megasonic waves in the cleaning fluid and to form cavities in the cleaning fluid, wherein the megasonic transducer is configured to direct the megasonic waves and cavities toward the substrate support; and one or more sensors configured to generate a signal indicative of a property of the cavities in the cleaning fluid.

Abstract: Methods for depositing a silicon-containing film on a substrate are described. The method comprises heating a processing chamber to a temperature greater than or equal to 200° C.; maintaining the processing chamber at a pressure of less than or equal to 300 Torr; coflowing a silicon precursor and nitrous oxide (N2O) into the processing chamber, and depositing a conformal silicon-containing film on the substrate. The silicon-containing film has dielectric constant (k-value) in a range of from about 3.8 to about 4.0, has a breakdown voltage of greater than 8 MV/cm at a leakage current of 1 mA/cm2 and has a leakage current of less than 1 nA/cm2 at 2 MV/cm.

Abstract: Chalcogen silane precursors are described. Methods for depositing a silicon nitride (SixNy) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (SixNy) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).

Abstract: Apparatus that forms low resistivity tungsten film on substrates. In some embodiments, the apparatus may provide reduced resistivity of tungsten by being configured to generate a plasma in a processing volume of a physical vapor deposition (PVD) chamber with a process gas of krypton and using an RF power with a frequency of approximately 60 MHz, apply bias power at frequency of approximately 13.56 MHz to a substrate, and sputter a tungsten target to deposit a tungsten thin film on the substrate. At least approximately 90% of the deposited tungsten thin film has a <110> crystalline orientation plane approximately parallel to a top surface of the substrate.

Abstract: A method for patterning a material layer on a substrate includes forming a hard mask layer on a material layer disposed on a substrate, the material layer comprising a plurality of first layers and a plurality of second layers alternately formed over the substrate, performing a first etch process to form features in the material layer through the hard mask layer by supplying a first etching gas, and performing a second etch process to smooth sidewalls of the features formed in the material layer by suppling a second etching gas. The first etching gas is supplied continuously and the second etching gas is pulsed.

Abstract: A method of patterning a substrate is provided. The method includes modifying a surface of a metal-containing layer formed over a substrate positioned in a processing region of a processing chamber by exposing the surface of the metal-containing layer to plasma effluents of a chlorine-containing gas precursor and an oxygen-containing gas precursor to form a modified surface of the metal-containing layer. The method further includes directing plasma effluents of an inert gas precursor towards the modified surface of the metal-containing layer. The plasma effluents of the inert gas precursor are directed by applying a bias voltage to a substrate support holding the substrate. The method further includes anisotropically etching the modified surface of the metal-containing layer with the plasma effluents of the inert gas precursor to form a first recess having a first sidewall in the metal-containing layer.

Abstract: A method of polishing a substrate includes polishing a conductive layer on the substrate at a polishing station, monitoring the layer with an in-situ eddy current monitoring system to generate a plurality of measured signals values for a plurality of different locations on the layer, generating thickness measurements the locations, and detecting a polishing endpoint or modifying a polishing parameter based on the thickness measurements. The conductive layer is formed of a first material having a first conductivity. Generating includes calculating initial thickness values based on the plurality of measured signals values and processing the initial thickness values through a neural network that was trained using training data acquired by measuring calibration substrates having a conductive layer formed of a second material having a second conductivity that is lower than the first conductivity to generated adjusted thickness values.

Abstract: Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.

Abstract: A shield encircles a sputtering target that faces a substrate support in a substrate processing chamber. The shield comprises an outer band having a diameter sized to encircle the sputtering target, the outer band having upper and bottom ends, and the upper end having a tapered surface extending radially outwardly and adjacent to the sputtering target. A base plate extends radially inward from the bottom end of the outer band. An inner band joined to the base plate at least partially surrounds a peripheral edge of a substrate support. The shield can also have a heat exchanger comprising a conduit with an inlet and outlet to flow heat exchange fluid therethrough.

Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).

Abstract: Embodiments of the present disclosure relate to an apparatus and methods for forming arrays of EL devices and forming the EL devices with overlapped mask plates. The methods utilize overlapping a first mask plate and a second mask plate to form a mask arrangement having first apertures of the first mask plate overlapped with second apertures of the second mask plate forming one or more opening areas. A material is evaporated through the mask arrangement such that layers of the material are formed in a device area of the EL devices. The device area of each of the EL devices corresponds to the opening area of the mask arrangement of the first mask plate and the second mask plate. The method described herein allows for a higher density of the EL devices and creates a smaller deposition area due to the opening area of the mask arrangement.

Abstract: Implementations disclosed describe a method and a system to perform the method of obtaining a reduced representation of a plurality of sensor statistics representative of data collected by a plurality of sensors associated with a device manufacturing system performing a manufacturing operation. The method further includes generating, using a plurality of outlier detection models, a plurality of outlier scores, each of the plurality of outlier scores generated based on the reduced representation of the plurality of sensor statistics using a respective one of the plurality of outlier detection models. The method further includes processing the plurality of outlier scores using a detector neural network to generate an anomaly score indicative of a likelihood of an anomaly associated with the manufacturing operation.

Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

Abstract: Molybdenum(0) coordination complexes comprising an arene ligand and one or more neutral ligands which coordinate to the metal center by carbon, nitrogen or phosphorous are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum nitride). The exposures can be sequential or simultaneous.