Patents Assigned to Applied Materials, Inc.
  • Publication number: 20210143029
    Abstract: A system may include a main line for delivering a first gas, and a sensor for measuring a concentration of a precursor in the first gas delivered through the main line. The system may further include first and second sublines for providing fluid access to first and second processing chambers, respectively. The first subline may include a first flow controller for controlling the first gas flowed through the first subline. The second subline may include a second flow controller for controlling the first gas flowed through the second subline. A delivery controller may be configured to control the first and second flow controllers based on the measured concentration of the precursor to deliver a first mixture of the first gas and a second gas and a second mixture of the first and second gases into the first and second semiconductor processing chambers, respectively.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 13, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Diwakar Kedlaya, Fang Ruan, Zubin Huang, Ganesh Balasubramanian, Kaushik Alayavalli, Martin Seamons, Kwangduk Lee, Rajaram Narayanan, Karthik Janakiraman
  • Publication number: 20210143058
    Abstract: Exemplary methods of forming a semiconductor structure may include forming a first silicon oxide layer overlying a semiconductor substrate. The methods may include forming a first silicon layer overlying the first silicon oxide layer. The methods may include forming a silicon nitride layer overlying the first silicon layer. The methods may include forming a second silicon layer overlying the silicon nitride layer. The methods may include forming a second silicon oxide layer overlying the second silicon layer. The methods may include removing the silicon nitride layer. The methods may include removing the first silicon layer and the second silicon layer. The methods may include forming a metal layer between and contacting each of the first silicon oxide layer and the second silicon oxide layer.
    Type: Application
    Filed: November 4, 2020
    Publication date: May 13, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Praket Prakash Jha, Shuchi Sunil Ojha, Jingmei Liang, Abhijit Basu Mallik, Shankar Venkataraman
  • Publication number: 20210140046
    Abstract: Silyl pseudohalides having a general formula of R4?nSiXn, where n is a range of 1-4, each R is independently selected from H, alkyl, alkenyl, aryl, amino, alkyl amino, alkoxide, and phosphine groups, and each X is a pseudohalide selected from nitrile, cyanate, isocyanate, thiocyanate, isothiocyanate, selenocyanate and isoselenocyanate are disclosed. Further, some embodiments of the disclosure provide methods for depositing silicon-containing films using silyl pseudohalides.
    Type: Application
    Filed: November 12, 2020
    Publication date: May 13, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Keenan N. Woods, Cong Trinh, Mark Saly, Mihaela A. Balseanu, Maribel Maldonado-Garcia, Lisa J. Enman
  • Publication number: 20210142984
    Abstract: Exemplary semiconductor processing chambers may include an inlet manifold defining a central aperture. The inlet manifold may also define a first channel and a second channel, and each of the channels may extend through the inlet manifold radially outward of the central aperture. The chambers may also include a gasbox characterized by a first surface facing the inlet manifold and a second surface opposite the first. The gasbox may define a central aperture aligned with the central aperture of the inlet manifold. The gasbox may define a first annular channel in the first surface extending about the central aperture of the gasbox and fluidly coupled with the first channel of the inlet manifold. The gasbox may define a second annular channel extending radially outward of the first and fluidly coupled with the second channel of the inlet manifold. The second annular channel may be fluidly isolated from the first.
    Type: Application
    Filed: November 4, 2020
    Publication date: May 13, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Fang Ruan, Diwakar Kedlaya, Truong Van Nguyen, Mingle Tong, Sherry L. Mings, Venkata Sharat Chandra Parimi
  • Publication number: 20210141131
    Abstract: Methods of producing gratings with trenches having variable height are provided. In one example, a method of forming a diffracted optical element may include providing an optical grating layer over a substrate, patterning a hardmask over the optical grating layer, and forming a sacrificial layer over the hardmask, the sacrificial layer having a non-uniform height measured from a top surface of the optical grating layer. The method may further include etching a plurality of angled trenches into the optical grating layer to form an optical grating, wherein a first depth of a first trench of the plurality of trenches is different than a second depth of a second trench of the plurality of trenches.
    Type: Application
    Filed: October 16, 2020
    Publication date: May 13, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Morgan Evans, Rutger Meyer Timmerman Thijssen, Joseph C. Olson
  • Publication number: 20210143039
    Abstract: Methods of controlling stress non-uniformity for semiconductor processing may include reflecting light off a surface of a wafer with an optical imaging device disposed within a cluster tool. The cluster tool may include a multi-chamber processing system. The methods may include collecting one or more color images of the surface of the wafer. The methods may include converting the one or more color images to sample stress intensity data comparing the sample stress intensity data to reference wafer stress intensity data. The methods may include identifying deviations of the sample stress intensity data relative to the reference wafer stress intensity data. The methods may include determining corrective actions for bringing the sample stress intensity data into conformity with the reference wafer stress intensity data. The methods may include implementing the corrective actions on the multi-chamber processing system.
    Type: Application
    Filed: November 10, 2020
    Publication date: May 13, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Gautam K. Hemani, Khokan Chandra Paul
  • Publication number: 20210140045
    Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the boron-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the silicon-containing precursor or the boron-containing precursor is greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-and-boron material on a substrate disposed within the processing region of the semiconductor processing chamber.
    Type: Application
    Filed: November 2, 2020
    Publication date: May 13, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Yi Yang, Krishna Nittala, Karthik Janakiraman, Aykut Aydin, Diwakar Kedlaya
  • Publication number: 20210143010
    Abstract: Exemplary methods of semiconductor processing may include treating a surface of a substrate with a hydrogen-containing precursor. The substrate may be disposed within a processing region of a semiconductor processing chamber. The methods may include contacting the substrate with a tungsten-containing precursor. The methods may include forming an initiation layer comprising tungsten on the substrate. The methods may include treating the initiation layer with a hydrogen-containing precursor. The methods may include forming a plasma of the tungsten-containing precursor and a carbon-containing precursor. Hydrogen in the plasma may be limited to hydrogen included in the carbon-containing precursor. The methods may include forming a tungsten-containing hardmask layer on the initiation layer.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 13, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Xiaoquan Min, Venkata Sharat Chandra Parimi, Prashant Kumar Kulshreshtha, Kwangduk Lee
  • Publication number: 20210140041
    Abstract: Methods of depositing metal films comprising exposing a substrate surface to a first metal precursor followed by a non-oxygen containing reducing agent comprising a second metal to form a zero-valent first metal film are described. The reducing agent has a metal center that is more electropositive than the metal center of the first metal precursor. In some embodiments, methods of depositing ruthenium films are described in which a substrate surface is exposed to a ruthenium precursor to form a ruthenium containing film on the substrate surface followed by exposure to a non-oxygen containing reducing agent to reduce the ruthenium containing film to a zero-valent ruthenium film and generate an oxidized form of the reducing agent.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 13, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Nasrin Kazem, Muthukumar Kaliappan, Jeffrey W. Anthis, Michael Haverty
  • Patent number: 11004663
    Abstract: Embodiments described herein provide an apparatus for improving deposition uniformity by improving plasma profile using a tri-cut chamber liner. The apparatus also includes a lid assembly having a split process stack for reducing downtime and a bottom heater support for more efficient heating of chamber walls.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: May 11, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Juan Carlos Rocha-Alvarez, Dale R. Du Bois, Amit Kumar Bansal
  • Patent number: 11004689
    Abstract: Exemplary methods for selectively removing silicon (e.g. polysilicon) from a patterned substrate may include flowing a fluorine-containing precursor into a substrate processing chamber to form plasma effluents. The plasma effluents may remove silicon (e.g. polysilicon, amorphous silicon or single crystal silicon) at significantly higher etch rates compared to exposed silicon oxide, silicon nitride or other dielectrics on the substrate. The methods rely on the temperature of the substrate in combination with some conductivity of the surface to catalyze the etch reaction rather than relying on a gas phase source of energy such as a plasma.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: May 11, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Zihui Li, Rui Cheng, Anchuan Wang, Nitin K. Ingle, Abhijit Basu Mallick
  • Patent number: 11001535
    Abstract: Embodiments of the present disclosure generally relate to methods of forming optical devices comprising nanostructures disposed on transparent substrates. A substrate, such as a silicon wafer, is provided as a base for forming an optical device. A transparent layer is disposed on a first surface of the substrate, and a structure layer is disposed on the transparent surface. An etch mask layer is disposed on a second surface of the substrate opposite the first surface, and a window or opening is formed in the etch mask layer to expose a portion of the second surface of the substrate. A plurality of nanostructures is then formed in the structure layer, and a portion of the substrate extending from the window to the transparent layer is removed. A portion of the transparent layer having nanostructures disposed thereon is then detached from the substrate to form an optical device.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: May 11, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tapashree Roy, Rutger Meyer Timmerman Thijssen
  • Patent number: 11004704
    Abstract: Embodiments described herein generally relate to a processing apparatus having a cover piece that participates in preheating a process gas. In one implementation, the cover piece includes an annulus. The annulus has an inner wall with a first height, an outer wall with a second height, and a top surface. The second height is greater than the first height. The cover piece also includes an inner lip disposed adjacent the inner wall, and a plurality of fins disposed on the top surface of the annulus. The cover piece and the plurality of fins are an opaque quartz material. The cover piece provides for more efficient heating of process gases, is composed of a material capable of withstanding process conditions while providing for more efficient and uniform processing, and has a low CTE reducing particle contamination due to excessive expansion during processing.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: May 11, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Lara Hawrylchak, Chaitanya A. Prasad, Emre Cuvalci
  • Patent number: 11003149
    Abstract: Electronic device processing systems including environmental control of the factory interface, a carrier purge chamber, and one or more substrate carriers are described. One electronic device processing system has a factory interface having a factory interface chamber, one or more substrate carriers coupled to the factory interface, and an environmental control system coupled to the factory interface, the carrier purge chamber, and the one or more substrate carriers and operational to control an environment at least within the factory interface chamber, carrier purge chamber, and the one or more substrate carriers. Methods for processing substrates are described, as are numerous other aspects.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: May 11, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Michael R. Rice, Dean C. Hruzek
  • Patent number: 11004708
    Abstract: An apparatus for chemical mechanical polishing includes a platen having a surface to support a polishing pad and an electromagnetic induction monitoring system to generate a magnetic field to monitor a substrate being polished by the polishing pad. The electromagnetic induction monitoring system includes a core positioned at least partially in the platen and a coil wound around a portion of the core. The core includes a back portion and a multiplicity of posts extending from the back portion in a first direction normal to the surface of the platen. The core and coil are configured such that the multiplicity of posts include a first plurality of posts to provide a first magnetic polarity and a second plurality of posts to provide an opposite second magnetic polarity, and the first plurality of posts and the second plurality of posts are arranged in an alternating pattern.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: May 11, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Hassan G. Iravani, Boguslaw A. Swedek, Tzu-Yu Liu, Kun Xu, Shih-Haur Shen
  • Patent number: 11002530
    Abstract: An additive manufacturing apparatus for forming a polishing pad for chemical mechanical polishing includes a platform, an actuator system coupled to the platform to adjust a tilt of the platform, one or more printheads supported above the platform, the one or more printheads configured to dispense successive layers of feed material on the platform to be form the polishing pad, a sensing system to detect a height of a surface on or above the platform at each of a plurality of horizontally spaced points, and a controller configured to selectively operate the actuator system to adjust the tilt of the platform based on the detected height of the platform at each of the points such that the surface is moved closer to horizontal.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: May 11, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Hou T. Ng, Nag B. Patibandla, Sivapackia Ganapathiappan
  • Patent number: 11003080
    Abstract: A method and apparatus disclosed herein apply to processing a substrate, and more specifically to a method and apparatus for improving photolithography processes. The apparatus includes a chamber body, a substrate support disposed within the chamber body, and an electrode assembly. The substrate support has a top plate disposed above the substrate support, a bottom plate disposed below the substrate support, and a plurality of electrodes connecting the top plate to the bottom plate. A voltage is applied to the plurality of electrodes to generate an electric field. Methods for exposing a photoresist layer on a substrate to an electric field are also disclosed herein.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 11, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Srinivas D. Nemani
  • Patent number: 11004661
    Abstract: A method and apparatus for substrate etching are described herein. A processing chamber described herein includes a source module, a process module, a flow module, and an exhaust module. An RF source may be coupled to the chamber and a remote plasma may be generated in the source module and a direct plasma may be generated in the process module. Cyclic etching processes described may use alternating radical and direct plasmas to etch a substrate.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: May 11, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Toan Q. Tran, Soonam Park, Junghoon Kim, Dmitry Lubomirsky
  • Patent number: 11004648
    Abstract: Embodiments herein provide systems and methods for multi-area selecting etching. In some embodiments, a system may include a plasma source delivering a plurality of angled ion beams to a substrate, the substrate including a plurality of devices. Each of the plurality of devices may include a first angled grating and a second angled grating. The system may further include a plurality of blocking masks positionable between the plasma source and the substrate. A first blocking mask of the plurality of blocking masks may include a first set of openings permitting the angled ion beams to pass therethrough to form the first angled gratings of each of the plurality of devices. A second blocking mask of the plurality of blocking masks may include a second set of openings permitting the angled ion beams to pass therethrough to form the second angled gratings of each of the plurality of devices.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: May 11, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Morgan Evans, Rutger Meyer Timmerman Thijssen
  • Patent number: 11004710
    Abstract: Methods and systems of detection of wafer placement error in a semiconductor processing chamber are disclosed. Methods and systems of interdiction are also disclosed to prevent hardware and wafer damage during semiconductor fabrication if and when a wafer placement error is detected. The method—is based on measuring a slope of current in an electrostatic chuck (ESC), which is correlated to lack of contact between the wafer and the ESC. Wafer placement detection at an early stage, when a heater and an ESC are being set up, gives the option of stopping the process before high power RF plasma is created.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: May 11, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Hemant Mungekar, Ganesh Balasubramanian