Abstract: A camera may capture reflected light from the surface of the wafer during a semiconductor process that adds or removes material from the wafer, such as an etch process. To accurately determine an endpoint for the process, a camera sampling rate and light source intensity may be optimized in the process recipe. Optimizing the light source intensity may include characterizing light intensities that will be reflected from the waiver using an image of the wafer. Pixel intensities may be used to adjust the light source intensity to compensate for more complex wafer patterns. Optimizing the camera sampling rates may include nondestructively rotating a view of the wafer and converting the sampled intensities to the frequency domain. The camera sampling rate may be increased or decreased to remove spatial noise from the image without oversampling unnecessarily. These optimized parameters may then generate a clean, repeatable trace for endpoint determination.

Abstract: Disclosed herein are approaches for forming dynamic DRAM devices without trench fill voids. A method may include providing a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures, and depositing a plurality of layers over the device structures. The layers may include a first layer over the device structures, a second layer over the first layer, and a third layer over the second layer. The method may further include forming a plurality of contact trenches through the plurality of layers to expose one or more device structures of the plurality of device structures, and directing ions into a sidewall of the trenches at a non-zero angle, wherein the ions impact the third layer without impacting the second layer. The method may further include forming a fill material within the trenches after the ions are directed into the sidewall of the trenches.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a source region and a drain region adjacent to a superlattice structure on a substrate. The source region and the drain region comprise a metallic silicide material. In some embodiments, a sacrificial material is first deposited and then removed to form a metallic silicide material in the source and drain region.

Abstract: An antenna assembly, comprising: an antenna; a dielectric enclosure surrounding the antenna; and a Faraday shield, disposed around the antenna, and arranged between the antenna and the dielectric enclosure, wherein the Faraday shield comprises a non-uniform opacity along an antenna axis of the antenna, wherein a first opacity of the Faraday shield at a first position along the antenna axis is greater than a second opacity of the Faraday shield at a second position along the antenna axis of the antenna.

Abstract: Embodiments disclosed herein include gas concentration sensors, and methods of using such gas concentration sensors. In an embodiment, a gas concentration sensor comprises a first electrode. In an embodiment the first electrode comprises first fingers. In an embodiment, the gas concentration sensor further comprises a second electrode. In an embodiment, the second electrode comprises second fingers that are interdigitated with the first fingers.

Abstract: Embodiments described herein relate to magnetic and electromagnetic systems and a method for controlling the density profile of plasma generated in a process volume of a PECVD chamber to affect deposition profile of a film on a substrate and/or facilitate chamber cleaning after processing. In one embodiment, a system is disclosed that includes a rotational magnetic housing disposed about an exterior sidewall of a chamber. The rotational magnetic housing includes a plurality of magnets coupled to a sleeve that are configured to travel in a circular path when the rotational magnetic housing is rotated around the chamber, and a plurality of shunt doors movably disposed between the chamber and the sleeve, wherein each of the shunt doors are configured to move relative to the magnets.

Abstract: Embodiments of the disclosure generally provide polishing pads having a composite pad body and methods for forming the polishing pads. In one embodiment, the composite pad body includes one or more first features formed from a first material or a first composition of materials, and one or more second features formed from a second material or a second composition of materials, wherein the one or more first features and the one or more second features are formed by depositing a plurality of layers comprising the first material or first composition of materials and second material or second composition of materials.

Abstract: Embodiments of a process kit are provided herein. In some embodiments, a process kit includes a deposition ring configured to be disposed on a substrate support, the deposition ring including an annular band configured to rest on a lower ledge of the substrate support, the annular band having an upper surface and a lower surface, the lower surface including a step between a radially inner portion and a radially outer portion; an inner lip extending upwards from the upper surface of the annular band and adjacent an inner surface of the annular band, wherein a depth between an upper surface of the annular band and a horizontal portion of the upper surface of the inner lip is between about 6.0 mm and about 12.0 mm; a channel disposed radially outward of and beneath the annular band; and an outer lip extending upwardly and disposed radially outward of the channel.

Abstract: Embodiments of the present technology include semiconductor processing methods to make boron-and-silicon-containing layers that have a changing atomic ratio of boron-to-silicon. The methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber, and also flowing a boron-containing precursor and molecular hydrogen (H2) into the substrate processing region of the semiconductor processing chamber. The boron-containing precursor and the H2 may be flowed at a boron-to-hydrogen flow rate ratio. The flow rate of the boron-containing precursor and the H2 may be increased while the boron-to-hydrogen flow rate ratio remains constant during the flow rate increase. The boron-and-silicon-containing layer may be deposited on a substrate, and may be characterized by a continuously increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer furthest from the substrate.

Abstract: A method of forming a high-? dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-? dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-? dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-? dielectric cap layer, and removing the sacrificial silicon cap layer.

Abstract: A ferroelectric capacitor or a ferroelectric transistor may include a first metal layer having a first metal having a first work function, and a second metal layer having a second metal having a second work function. The capacitor may also include a a vertical electrode and a ferroelectric material that surrounds the vertical electrode and forms a plurality of switching regions in the ferroelectric material. The transistor may include a vertical channel, a vertical buffer layer that surround the vertical channel, and a ferroelectric material that surrounds the vertical buffer layer and forms a plurality of gate regions in the ferroelectric material.

Abstract: A two part retaining ring is described. A rigid upper portion has an annular recess along its inner diameter. An annular wearable lower portion has an inner diameter, an annular extension defined by the inner diameter and a vertical wall that is perpendicular to a surface of the second portion and opposite to the inner diameter. The annular extension fits into the annular recess of the annular first portion. A bonding material is on the vertical wall of the annular second portion.

Abstract: A method includes receiving trace sensor data associated with a first manufacturing process of a manufacturing chamber. The method further includes processing the trace sensor data by a processing device to generate summary data associated with the trace sensor data. The method further includes generating a quality index score based on the summary data. The method further includes providing an alert to a user based on the quality index score. The alert includes an indication that the manufacturing chamber performance does not meet a first threshold.

Abstract: A light-emitting diode display including a substrate having a driving circuitry and a plurality of light emitting diode structures disposed on the substrate. Each light-emitting diode structure has a light emitting diode with a light emission zone having a planar portion, and a pigmentless light extraction layer of a UV-cured ink disposed over the light-emitting diode. The light extraction layer has a gradient in index of refraction along an axis normal to the planar portion, and the index of refraction of the light extraction layer decreases with distance from the planar portion.

Abstract: A gas injector for processing a substrate includes a body having an inlet connectable to a gas source that is configured to provide a gas flow in a first direction into the inlet when processing a substrate on a substrate support disposed within a processing volume of a processing chamber, and an a gas injection channel formed in the body. The gas injection channel is in fluid communication with the inlet and configured to deliver the gas flow to an inlet of the processing chamber. The gas injection channel has a first interior surface and a second interior surface that are parallel to a second direction and a third direction. The second and third directions are misaligned with a center of the substrate, and are at an angle to the first direction towards a first edge of the substrate support.

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface.

Abstract: Disclosed herein are approaches for forming contacts in a 4F2 vertical dynamic random-access memory device. One method includes providing a plurality of fins extending from a substrate, forming a spacer layer over the plurality of fins, and etching the substrate to expose a base portion of the plurality of fins. The method may include forming a doped layer along the base portion of the plurality of fins and along an upper surface of the substrate, and forming an oxide spacer over the doped layer.

Abstract: Exemplary methods of etching a silicon-containing material may include flowing a first fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The methods may include flowing a sulfur-containing precursor into the remote plasma region of the semiconductor processing chamber. The methods may include forming a plasma within the remote plasma region to generate plasma effluents of the first fluorine-containing precursor and the sulfur-containing precursor. The methods may include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region. The substrate may include a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The methods may include isotropically etching the layers of silicon nitride while substantially maintaining the silicon oxide.

Abstract: Exemplary methods of semiconductor processing may include etching a portion of a silicon-containing material from a substrate disposed within a processing region of a semiconductor processing chamber. The silicon-containing material may extend into one or more recesses defined by alternating layers of material deposited on the substrate. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting a remaining silicon-containing material with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the silicon-containing material. The methods may include providing a cleaning agent to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the cleaning agent. The contacting with the cleaning precursor may remove surface oxide from the substrate.

Abstract: A chemical mechanical polishing system includes a platen to hold a polishing pad, a carrier head to hold a substrate against a polishing surface of the polishing pad, and a controller. The polishing pad has a polishing control groove. The carrier is laterally movable by a first actuator across the polishing pad and rotatable by a second actuator. The controller synchronizes lateral oscillation of the carrier head with rotation of the carrier head such that over a plurality of successive oscillations of the carrier head such that when a first angular swath of an edge portion of the substrate is at an azimuthal angular position about an axis of rotation of the carrier head the first angular swath overlies the polishing surface and when a second angular swath of the edge portion of the substrate is at the azimuthal angular position the second angular swath overlies the polishing control groove.