Abstract: Silyl pseudohalides having a general formula of R4-nSiXn, where n is a range of 1-4, each R is independently selected from H, alkyl, alkenyl, aryl, amino, alkyl amino, alkoxide, and phosphine groups, and each X is a pseudohalide selected from nitrile, cyanate, isocyanate, thiocyanate, isothiocyanate, selenocyanate and isoselenocyanate are disclosed. Further, some embodiments of the disclosure provide methods for depositing silicon-containing films using silyl pseudohalides.

Abstract: Generating a recipe for controlling a polishing system includes receiving a target removal profile that includes a target thickness to remove for a plurality of locations on a substrate that are angularly distributed around the substrate, and storing a first function defining a polishing rate for a zone from a plurality of pressurizable zones of a carrier head that are angularly distributed around a the carrier head. The first function defines polishing rates as a function of pressures. For each particular zone of the plurality of zones a recipe defining a pressure for the particular zone over time is calculated by calculating an expected thickness profile after polishing using the first function, and minimizing a cost function that incorporates a first term representing a difference between the expected thickness profile and a target thickness profile.

Abstract: Methods and apparatus for bonding chiplets to substrates are provided herein. In some embodiments, a multi-chamber processing tool for processing substrates, includes: a first equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates, a second EFEM having one or more loadports; and a plurality of atmospheric modular mainframes (AMMs) coupled to each other and having a first AMM coupled to the first EFEM and a last AMM coupled to the second EFEM, wherein each of the plurality of AMMs include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein the transfer chamber includes a buffer, and wherein the transfer chamber includes a transfer robot, the one or more process chambers, and a buffer disposed in an adjacent AMM of the plurality of AMMs.

Abstract: A carrier head includes a housing, a support assembly having a support plate flexibly connected to the housing so as to be vertically movable, a plurality of fluid-impermeable barriers projecting from a bottom of the support plate to define a plurality of recesses that are open at bottom sides thereof, and pneumatic control lines. A volume between the support plate and the housing includes one or more independently pressurizable first chambers to apply pressure on a top surface of the support plate in one or more first zones. The barriers are positioned and configured such that when a planar substrate is loaded into the carrier head the barriers contact the substrate and divide a volume between the support plate and the substrate into a plurality of second chambers. The pneumatic control lines are coupled to the plurality of recesses to provide a plurality of independently pressurizable second zones.

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

Abstract: Disclosed is a coated chamber component comprising a body having a reduced metal surface such that the reduced metal surface has less metal oxide as compared to an amount of metal oxide on a metal surface that has not been reduced. The metal surface may be reduced by pulsing a reducing alcohol thereon. The reduced metal surface may be coated with a corrosion resistant film that may be deposited onto the reduced metal surface by a dry atomic layer deposition process.

Abstract: The disclosure pertains to a capacitively coupled plasma source in which VHF power is applied through an impedance-matching coaxial resonator having a symmetrical power distribution.

Abstract: A method of chemical mechanical polishing includes rotating a polishing pad about an axis of rotation, positioning a substrate against the polishing pad, the polishing pad having a groove that is concentric with the axis of rotation, oscillating the substrate laterally across the polishing pad such that a central portion of the substrate and an edge portion of the substrate are positioned over a polishing surface of the polishing pad for a first duration, and holding the substrate substantially laterally fixed in a position such that the central portion of the substrate is positioned over the polishing surface of the polishing pad and the edge portion of the substrate is positioned over the groove for a second duration.

Abstract: Exemplary deposition methods may include delivering a boron-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the boron-containing precursor and the nitrogen-containing precursor. A flow rate ratio of the hydrogen-containing precursor to either of the boron-containing precursor or the nitrogen-containing precursor may be greater than or about 2:1. The methods may include forming a plasma of all precursors within the processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-nitrogen material on a substrate disposed within the processing region of the semiconductor processing chamber.

Abstract: A method includes machining a raw surface of a metal component to remove first native oxide from a metal base of the metal component to generate an as-machined surface of the metal component. A second native oxide is formed on the metal base of the as-machined surface of the metal component subsequent to the machining. The method further includes, subsequent to the machining, performing operations to generate a finished surface of the metal component. The operations include a surface machining of the as-machined surface of the metal component to remove the second native oxide.

Abstract: Embodiments described herein relate to methods of forming layers using maskless based lithography. In these embodiments, the methods implement ladders of dose change such that a geometric shape can be divided into overlaying sections. The overlaying sections can include a different dose of each section such that taper control can be achieved. The taper can be achieved by manipulating the geometry “mask data” into overlaying sections that are exposed by various doses controlled by pixel blending (PB) exposure techniques. To perform the methods described herein, a maskless lithography tool is used. The maskless lithography tool includes a controller that performs software based “mask data” manipulation.

Abstract: Embodiments described and discussed herein generally relate to flexible or foldable display devices, and more specifically to flexible cover lens assemblies. In one or more embodiments, a flexible cover lens assembly contains a glass layer, an adhesion promotion layer disposed on the glass layer, a dry hardcoat layer having a nano-indentation hardness in a range from about 1 GPa to about 5 GPa and disposed on the adhesion promotion layer and an anti-fingerprint coating layer disposed on the dry hardcoat layer.

Abstract: Described herein is a method of depositing a conformal, optically transparent coating onto a surface of one or more internal components that are enclosed within an assembled device using a non-line-of-sight deposition process without altering a structure of the assembled device or impacting functionality of the assembled device. Also described is an assembled device including one or more internal components enclosed within the assembled device and a coating deposited onto a surface of the internal components enclosed within the assembled device, where the coating is a conformal, optically transparent coating that is resistant to corrosion by at least one of fluorine-, chlorine-, sulfur-, hydrogen-, bromine-, or nitrogen-based acids and that does not negatively impact functionality of the internal components.

Abstract: Exemplary package on package (PoP) assemblies may include a substrate. The PoP assemblies may include a first package positioned on a first side of the substrate with a bottom surface of the first package facing the substrate. The PoP assemblies may include a second package positioned on a second side of the substrate with a top surface of the second package facing the substrate. The second side may be positioned opposite the first side. The PoP assemblies may include a conductive element that contacts one or both of a top surface and the bottom surface of the second package and extends to a position that is aligned with or above a top surface of the first package.

Abstract: Methods and apparatus bonding chiplets to substrates are provided herein. In some embodiments, a multi-chamber processing tool for processing a substrate includes: an equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates; and a plurality of automation modules coupled to each other and having a first automation module coupled to the EFEM, wherein each of the plurality of automation modules include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein the transfer chamber includes a buffer configured to hold a plurality of the one or more types of substrates, and wherein the transfer chamber includes a transfer robot configured to transfer the one or more types of substrates between the buffer, the one or more process chambers, and a buffer disposed in an adjacent automation module of the plurality of automation modules.

Abstract: Apparatus and methods for calibrating a height-adjustable edge ring are described herein. In one example, a calibration jig for positioning an edge ring relative to a reference surface is provided that includes a transparent plate, a plurality of sensors coupled to a first side of the transparent plate, and a plurality of contact pads coupled to an opposing second side of the transparent plate.

Abstract: A process kit comprises a shield and ring assembly for positioning about a substrate support in a processing chamber to reduce deposition of process deposits on internal chamber components and an overhang edge of the substrate. The shield comprises a cylindrical band having a top wall configured to surround a sputtering target and a sloped portion of a bottom wall having a substantially straight profile with gas conductance holes configured to surround the substrate support. The ring assembly comprises a cover ring having a bulb-shaped protuberance about the periphery of the ring. The bulb-shaped protuberance of the cover ring is able to block a line-of-sight between the gas conductance holes on the shield and an entrance to a chamber body cavity in the processing chamber.

Abstract: A semiconductor processing method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include an exposed region of silicon-and-oxygen-containing material. The substrate may include an exposed region of a liner material. The methods may include providing a hydrogen-containing precursor to the semiconductor processing region. The methods may include contacting the substrate with the fluorine-containing precursor and the hydrogen-containing precursor. The methods may include selectively removing at least a portion of the exposed silicon-and-oxygen-containing material.

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. The methods include treating a surface of a metal gate stack with a radical treatment. The radical treatment may be used to treat one or more layers or surfaces of layers in the metal gate stack. The radical treatment may be performed once or multiple times during the methods described herein. The radical treatment comprises flowing one or more of nitrogen radicals (N2*) and hydrogen radicals (H*) over the surface of the metal gate stack.

Abstract: Describes are shutter disks comprising one or more of titanium (Ti), barium (Ba), or cerium (Ce) for physical vapor deposition (PVD) that allows pasting to minimize outgassing and control defects during etching of a substrate. The shutter disks incorporate getter materials that are highly selective to reactive gas molecules, including O2, CO, CO2, and water.