Abstract: A method for forming a metal containing feature includes performing a deposition process, the deposition process comprising conformally depositing an over layer on top surfaces of a patterned mandrel layer and over a spacer layer on sidewalls of the patterned mandrel layer, and performing an etch process, the etch process comprising removing the over layer from the top surfaces of the patterned mandrel layer and shoulder portions of the spacer layer, and removing the shoulder portions of the spacer layer, using a fluorine containing etching gas.

Abstract: Exemplary semiconductor processing systems may include a chamber body including sidewalls and a base. The system may include a substrate support extending through the base of the chamber body. The chamber body may define an access circumferentially extending about the substrate support at the base of the chamber body. The system may include one or more isolators disposed within the chamber body. The one or more isolators may define an exhaust path between the one or more isolators and the chamber body. The exhaust path may extend to the base of the chamber body. The systems may include a fluid source fluidly coupled with the chamber body at the access extending about the substrate support.

Abstract: A vapor deposition apparatus is provided. The vapor deposition apparatus includes a tank for providing a liquefied material, a first unit having an alterable first volume, the first unit including a first actuator and including a first line to be in fluid communication with the tank. Further, the vapor deposition apparatus includes a second unit having an alterable second volume, the second unit including a second actuator and including a second line to be in fluid communication with the tank. The vapor deposition apparatus includes an evaporation arrangement, the evaporation arrangement being in fluid communication with the first unit and the second unit. The first actuator and the second actuator are configured to alternatingly provide a force to the alterable first volume and the alterable second volume for providing the liquefied material to the evaporation arrangement.

Abstract: Methods and apparatus for a lift pin mechanism for substrate processing chambers are provided herein. In some embodiments, the lift pin mechanism includes a lift pin comprising a shaft with a top end, a bottom end, and a coupling end at the bottom end; a bellows assembly disposed about the shaft. The bellows assembly includes an upper bellows flange having an opening for axial movement of the shaft; a bellows having a first end coupled to a lower surface of the upper bellows flange such that the shaft extends into a central volume surrounded by the bellows; and a bellows guide assembly coupled to a second end of the bellows to seal the central volume. The shaft is coupled to the bellows guide assembly at the coupling end. The bellows guide assembly is axially movable to move the lift pin with respect to the upper bellows flange.

Abstract: A sealing member includes a monolithic body including a first portion adjoining a second portion. The first portion forms part of a circle. The second portion includes first and second lobes. Each lobe adjoins the first portion with a concave surface. In one example, each lobe includes a rounded tip, and a convex surface extends from one rounded tip to the other rounded tip.

Abstract: A mainframe of a device fabrication system comprises a base and a plurality of facets on the base. Each facet of the plurality of facets comprises a frame. The mainframe further comprises a plurality of replaceable interface plates. Each replaceable interface plate of the plurality of replaceable interface plates is attached to a respective facet such that at most one replaceable interface plate is attached to each facet. At least one replaceable interface plate comprises one or more access ports. The mainframe further comprises a lid over the plurality of facets. The base, the lid and the plurality of facets with the attached plurality of replaceable interface plates together define an interior volume of the mainframe. The mainframe further comprises a robot arm in the interior volume.

Abstract: Aspects of the present disclosure relate to one or more implementations of a substrate support for a processing chamber. In one implementation, a substrate support includes a body having a center, and a support surface on the body configured to at least partially support a substrate. The substrate support includes a first angled wall that extends upward and radially outward from the support surface, and a first upper surface disposed above the support surface. The substrate support also includes a second angled wall that extends upward and radially outward from the first upper surface, the first upper surface extending between the first angled wall and the second angled wall. The substrate support also includes a second upper surface extending from the second angled wall. The second upper surface is disposed above the first upper surface.

Abstract: A method includes forming, on a substrate by performing physical vapor deposition in vacuum, an absorber layer including copper (Cu), indium (In), gallium (Ga) and selenium (Se), forming a stack including the substrate and an oxygen-annealed absorber layer by performing in-situ oxygen annealing of the absorber layer to improve quantum efficiency of the image sensor by passivating selenium vacancies due to dangling bonds, and forming a cap layer over the oxygen-annealed absorber layer by performing physical vapor deposition in vacuum. The cap layer includes at least one of: Ga2O3·Sn, ZnS, CdS, CdSe, ZnO, ZnSe, ZnIn2Se4, CuGaS2, In2S3, MgO, or Zn0.8Mg0.2O.

Abstract: Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a substrate support within the chamber body. The substrate support may define a substrate support surface. The chambers may include a faceplate supported atop the chamber body. The substrate support and a bottom surface of the faceplate may at least partially define a processing region. The bottom surface of the faceplate may define an annular protrusion that is directly above at least a portion of a radially outer 10% of the substrate support surface and an annular groove that is positioned radially outward of the annular protrusion. At least a portion of the annular groove may extend radially outward beyond the substrate support surface. The faceplate may define apertures through the faceplate. A first subset of the apertures may extend through the annular protrusion and a second subset of the apertures may extend through the annular groove.

Abstract: Exemplary semiconductor processing methods may include providing a pre-treatment precursor to a processing region of a semiconductor processing chamber. A first layer of silicon-and-germanium-containing material and a second layer of silicon-and-germanium-containing material may be disposed on a substrate housed within the processing region. A native oxide may be present on the first layer and the second layer. The methods may include contacting the substrate with the pre-treatment precursor to remove the native oxide. The methods may include providing an oxygen-containing precursor to the processing region. The methods may include contacting the substrate with the oxygen-containing precursor to oxidize at least a portion of the second layer. The methods may include providing an etchant precursor to the processing region. The methods may include contacting the substrate with the etchant precursor to selectively etch the first layer of silicon-and-germanium-containing material.

Abstract: Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces.

Abstract: Exemplary semiconductor processing methods may include performing a treatment operation on a substrate housed within a first processing region of a first semiconductor processing chamber. The methods may include providing a nitrogen-containing precursor to the first processing region. The methods may include forming plasma effluents of the nitrogen-containing precursor. The methods may include contacting the substrate with the plasma effluents of the nitrogen-containing precursor. The contacting may nitride a surface of the substrate. The methods may include transferring the substrate from the first processing region of the first semiconductor processing chamber to a second processing region of a second semiconductor processing chamber. The methods may include providing one or more deposition precursors to the second processing region. The methods may include contacting the substrate with the one or more deposition precursors. The contacting may deposit a layer of dielectric material on the substrate.

Abstract: Gas distribution assemblies for a semiconductor manufacturing processing chamber comprising a first showerhead with a first flange and a second showerhead with a second flange. A first two-piece RF isolator comprises a first inner RF isolator spaced from a first outer RF isolator. The first inner RF isolator spaced from the first flange of the first showerhead to create a first flow path. A second two-piece RF isolator comprises a second inner RF isolator spaced from a second outer RF isolator. The second RF isolator spaced from the second flange of the second showerhead to create a second flow path. Processing chambers incorporating the gas distribution assemblies, and processing methods using the gas distribution assemblies are also described.

Abstract: Ampoules including a solid volume of the semiconductor chemical precursor and methods of use and manufacturing are described. The solid volume of the semiconductor chemical precursor includes an ingress opening, at least one flow channel, and an outlet passage that are in fluid communication with each other. The solid volume of the semiconductor manufacturing precursor is made of a porous or alternatively a non-porous material. A flow path is defined by at least one flow channel through which a carrier gas flows in contact with the solid volume of the semiconductor chemical precursor.

Abstract: Disclosed herein is a substrate support assembly having a ground electrode mesh disposed therein along a side surface of the substrate support assembly. The substrate support assembly has a body. The body has an outer top surface, an outer side surface and an outer bottom surface enclosing an interior of the body. The body has a ground electrode mesh disposed in the interior of the body and adjacent the outer side surface, wherein the ground electrode does not extend through to the outer top surface or the outer side surface.

Abstract: Methods and systems for rating a current substrate support assembly based on impedance circuit electron flow are provided. Data associated with an amount of radio frequency (RF) power flowed through an electrical component of a current substrate support assembly during a current testing process performed for the current substrate support assembly is provided as input to a trained machine learning model. One or more outputs of the trained machine learning model are obtained. A measurement value for an electron flow across an impedance circuit of the current substrate support assembly is extracted from the one or more outputs. In response to a determination that the extracted measurement value for the electron flow satisfies an electron flow criterion, a first quality rating is assigned to the current substrate support assembly.

Abstract: Methods of processing a substrate in a PVD chamber are provided herein. In some embodiments, a method of processing a substrate in a PVD chamber, includes: sputtering material from a target disposed in the PVD chamber and onto a substrate, wherein at least some of the material sputtered from the target is guided to the substrate through a magnetic field provided by one or more upper magnets disposed about a processing volume of the PVD chamber above a support pedestal for the substrate in the PVD chamber, one or more first magnets disposed about the support pedestal and providing an increased magnetic field strength at an edge region of the substrate, and one or more second magnets disposed below the support pedestal that increase a magnetic field strength at a central region of the substrate.

Abstract: Methods for forming 3D DRAM leverage L-pad formations to increase memory density. Methods may include etching a substrate to form two Si walls oriented parallel to each other and forming a space therebetween, depositing a plurality of alternating Si layers and SiGe layers using epitaxial growth processes to form horizontal deposition layers on the space between the two Si walls and vertical deposition layers on sidewalls of the two Si walls, depositing a CMP stop layer on the substrate, planarizing the substrate to the CMP stop layer, removing a portion of a top of the two Si walls and forming an L-pad formation, deep etching a pattern of holes into the space between the two Si walls in horizontal portions of the plurality of alternating Si layers and SiGe layers, and forming vertical wordline structures from the pattern of holes in the horizontal portions.

Abstract: Embodiments of the present disclosure generally relate to a batch processing chamber that is adapted to simultaneously cure multiple substrates at one time. The batch processing chamber includes multiple processing sub-regions that are each independently temperature controlled. The batch processing chamber may include a first and a second sub-processing region that are each serviced by a substrate transport device external to the batch processing chamber. In addition, a slotted cover mounted on the loading opening of the batch curing chamber reduces the effect of ambient air entering the chamber during loading and unloading.

Abstract: Embodiments provided herein generally include apparatus, plasma processing systems, and methods for generation of a waveform for plasma processing of a substrate in a processing chamber. One embodiment includes a waveform generator having three MOSFETs and three series-connected capacitors. The capacitors are connected across a DC power supply and, depending on the value of the capacitors, voltage across each of them may be varied. Each of the top two capacitors is followed by a diode. The bottom capacitor is connected to the ground. The drain terminal of each MOSFET is connected to higher potential end of the series connected capacitors. Each MOSFET is followed by a diode and the cathode ends of the diodes are connected together. An electrode is connected between the common cathode and ground.