Patents Assigned to Applied Materials, Inc.
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Patent number: 11925073Abstract: A display device includes a display layer having a plurality of light-emitting diodes and an encapsulation layer covering a light-emitting side of the display layer. The encapsulation layer includes a plurality of first polymer projections on display layer, the plurality of first polymer projections having spaces therebetween, and a first dielectric layer conformally covering the plurality of first polymer projections and any exposed underlying surface in the spaces between the first polymer projections, the dielectric layer forming side walls along sides of the first polymer projections and defining wells in spaces between the side walls.Type: GrantFiled: October 5, 2021Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: Kyuil Cho, Byung Sung Kwak, Robert Jan Visser
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Patent number: 11922131Abstract: A method for performing vector-matrix multiplication may include converting a digital input vector comprising a plurality of binary-encoded values into a plurality of analog signals using a plurality of one-bit digital to analog converters (DACs); sequentially performing, using an analog vector matrix multiplier and based on bit-order, vector-matrix multiplication operations using a weighting matrix for the plurality of analog signals to generate analog outputs of the analog vector matrix multiplier; sequentially performing an analog-to-digital (ADC) operation on the analog outputs of the analog vector matrix multiplier to generate binary partial output vectors; and combining the binary partial output vectors to generate a result of the vector-matrix multiplication.Type: GrantFiled: November 7, 2020Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: Xiaofeng Zhang, She-Hwa Yen
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Patent number: 11923217Abstract: An embodiment is a processing system for processing a substrate. The processing system includes a Front Opening Unified Pod (FOUP) load lock (FLL) and a vacuum system. The FLL has walls defining an interior space therein. The FLL includes load lock isolation and tunnel isolation doors. The load lock isolation door is operable to close a first opening in a first sidewall of the FLL. The first opening is sized so that a FOUP is capable of passing therethrough. The tunnel isolation door is operable to close a second opening in a second sidewall of the FLL. The second opening is sized so that a substrate is capable of passing therethrough. The vacuum system is fluidly connected to the interior space of the FLL and is operable to pump down a pressure of the interior space of the FLL.Type: GrantFiled: July 5, 2022Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventor: Jacob Newman
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Patent number: 11920994Abstract: A sensor assembly that includes a surface acoustic wave (SAW) sensor. The SAW sensor is adapted to measure a first environmental condition in response to receiving an RF signal. The SAW sensor includes a substrate having a layer of piezoelectric material. The SAW sensor further includes a interdigitated transducer (IDT) formed on the piezoelectric material. The IDT includes two comb-shaped electrodes having interlocking conducting digits in a first arrangement. The interlocking conducting digits in the first arrangement generates a first signal modulation of an RF signal received by the first IDT. The first signal modulation identifies the first SAW sensor.Type: GrantFiled: October 12, 2020Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventor: Chuang-Chia Lin
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Patent number: 11921422Abstract: Embodiments of baking chambers for baking a substrate and methods of use thereof are provided herein. In some embodiments, a multi-chamber process tool for processing a substrate including: a wet clean chamber for cleaning the substrate; and a baking chamber configured to heat the substrate to remove residue or haze left over after a wet clean process performed in the wet clean chamber, the baking chamber comprising: a chamber body enclosing an interior volume; a heater disposed in the interior volume, wherein the heater is configured to have a surface temperature of about 100 to about 400 degrees Celsius during use; a substrate support configured to support a substrate disposed in the interior volume, wherein the substrate support has a direct line of sight with the heater such that the heater heats the substrate support via convection; and a gas inlet and a gas outlet coupled to the interior volume.Type: GrantFiled: April 9, 2021Date of Patent: March 5, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Banqiu Wu, Khalid Makhamreh, Eliyahu Shlomo Dagan
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Patent number: 11923244Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 ??·cm or less.Type: GrantFiled: March 5, 2021Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: He Ren, Hao Jiang, Shi You, Mehul B. Naik
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Patent number: 11923221Abstract: A master controller determines a first flow setpoint for a process flow gas and/or a carrier gas flow through a first mass flow controller. The master controller obtains a back pressure setpoint of a distribution manifold and determines a second flow setpoint for the process gas flow and/or the carrier gas flow through a second mass flow controller or a back pressure controller based on the determined first flow setpoint and the obtained back pressure setpoint. The master controller controls the process gas flow and/or the carrier gas flow through the first mass flow controller to the first flow setpoint and the second mass flow controller and/or the back pressure controller to the second flow setpoint. The master controller controls the back pressure of the distribution manifold to the back pressure set point in view of a back pressure reading from a back pressure sensor of the distribution manifold.Type: GrantFiled: September 27, 2022Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: Kevin Brashear, Ashley M. Okada, Dennis L. Demars, Zhiyuan Ye, Jaidev Rajaram, Marcel E. Josephson
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Patent number: 11923441Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.Type: GrantFiled: August 16, 2022Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
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Patent number: 11919121Abstract: Controlling a polishing system includes receiving from an in-situ monitoring system, for each region of a plurality of regions on a substrate being processed by the polishing system, a sequence of characterizing values for the region. For each region, a polishing rate is determined for the region, and an adjustment is calculated for at least one processing parameter. Calculation of the adjustment includes minimizing a cost function that includes, for each region, a difference between a current characterizing value or an expected characterizing value at an expected endpoint time and a target characterizing value for the region, and optimization of the cost function is subject to at least one constraint.Type: GrantFiled: February 28, 2022Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: Benjamin Cherian, Sivakumar Dhandapani
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Patent number: 11923172Abstract: Processing chambers with a plurality of processing stations and individual wafer support surfaces are described. The processing stations and wafer support surfaces are arranged so that there is an equal number of processing stations and heaters. An RF generator is connected to a first electrode in a first station and a second electrode in a second station. A bottom RF path is formed by a connection between a first support surface and a second support surface.Type: GrantFiled: February 8, 2022Date of Patent: March 5, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Hari Ponnekanti, Tsutomu Tanaka, Mandyam Sriram, Dmitry A. Dzilno, Sanjeev Baluja, Mario D. Silvetti
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Patent number: 11919120Abstract: A polishing system includes a platen having a top surface to support a main polishing pad. The platen is rotatable about an axis of rotation that passes through approximately the center of the platen. An annular flange projects radially outward from the platen to support an outer polishing pad. The annular flange has an inner edge secured to and rotatable with the platen and vertically fixed relative to the top surface of the platen. The annular flange is vertically deflectable such that an outer edge of the annular flange is vertically moveable relative to the inner edge. An actuator applies pressure to an underside of the annular flange in an angularly limited region, and a carrier head holds a substrate in contact with the polishing pad and is movable to selectively position a portion of the substrate over the outer polishing pad.Type: GrantFiled: February 25, 2021Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: David J. Lischka, Jay Gurusamy, Danielle Loi, Steven M. Zuniga
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Patent number: 11919123Abstract: A chemical mechanical polishing apparatus includes a rotatable platen to hold a polishing pad, a carrier to hold a substrate against a polishing surface of the polishing pad during a polishing process, and a temperature control system including a source of heated or coolant fluid and a plenum having a plurality of openings positioned over the platen and separated from the polishing pad for delivering the fluid onto the polishing pad, wherein at least some of the openings are each configured to deliver a different amount of the fluid onto the polishing pad.Type: GrantFiled: June 29, 2021Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: Surajit Kumar, Hari Soundararajan, Hui Chen, Shou-Sung Chang
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Patent number: 11920234Abstract: Described herein is a protective coating composition that provides erosion and corrosion resistance to a coated article (such as a chamber component) upon the article's exposure to harsh chemical environment (such as hydrogen based and/or halogen based environment) and/or upon the article's exposure to high energy plasma. Also described herein is a method of coating an article with the protective coating using electronic beam ion assisted deposition, physical vapor deposition, or plasma spray. Also described herein is a method of processing wafer, which method exhibits, on average, less than about 5 yttrium based particle defects per wafer.Type: GrantFiled: December 28, 2022Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: Vahid Firouzdor, Christopher Laurent Beaudry, Hyun-Ho Doh, Joseph Frederick Behnke, Joseph Frederick Sommers
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Patent number: 11924972Abstract: A diagnostic disc includes a disc-shaped body having raised walls that encircle the interior of the disc-shaped body and at least one protrusion extending outwardly from the disc-shaped body. The raised walls of the disc-shaped body define a cavity of the disc-shaped body. A non-contact sensor is attached to each of the at least one protrusion. A a printed circuit board (PCB) is positioned within the cavity formed on the disc-shaped body. A vacuum and high temperature tolerant power source is disposed on the PCB along with a wireless charger and circuitry that is coupled to each non-contact sensor and includes at least a wireless communication circuit and a memory. A cover is positioned over the cavity of the disc-shaped body and shields at least a portion of the PCB, circuitry, power source, and wireless charger within the cavity from an external environment.Type: GrantFiled: June 2, 2020Date of Patent: March 5, 2024Assignee: Applied Materials, Inc.Inventors: Phillip A. Criminale, Zhiqiang Guo, Andrew Myles, Martin Perez-Guzman
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Publication number: 20240068095Abstract: Gas distribution apparatuses described herein include a mixing plate adjacent a back plate of a showerhead. The mixing plate has a back surface and a front surface defining a thickness of the mixing plate. The mixing plate has a mixing channel comprising a top portion and a bottom portion defining a mixing channel length and at least two gas inlets in fluid communication with the top portion of the mixing channel. The gas distribution apparatus also includes a mixer disposed within the thickness of the mixing plate in the top portion of the mixing channel. The mixer has a top plate and a mixer stem extending from the top plate and a plurality of blades positioned along the mixer stem length. Also provided are processing chambers including the gas distribution apparatuses described herein.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: Applied Materials, Inc.Inventors: Youngki Chang, Dhritiman Subha Kashyap, Rakesh Ramadas, Ashutosh Agarwal, Shashidhara Patel H B, Muhannad Mustafa, Sanjeev Baluja
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Publication number: 20240074162Abstract: Methods for DRAM device with a buried word line are described. The method includes forming a metal nitride layer comprising lanthanum nitride (LaN) and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal nitride layer.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Applicant: Applied Materials, Inc.Inventors: Rand Haddadin, Kunal Bhatnagar
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Publication number: 20240071927Abstract: Methods of forming interconnects and electronic devices are described. Methods of forming interconnects include forming a tantalum nitride layer on a substrate; forming a ruthenium layer on the tantalum nitride layer; and exposing the tantalum nitride layer and ruthenium layer to a plasma comprising a mixture of hydrogen (H2) and argon (Ar) to form a tantalum doped ruthenium layer thereon. Apparatuses for performing the methods are also described.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Applicant: Applied Materials, Inc.Inventors: Shinjae Hwang, Feng Chen, Muthukumar Kaliappan, Michael Haverty
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Publication number: 20240071773Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.Type: ApplicationFiled: August 11, 2023Publication date: February 29, 2024Applicant: Applied Materials, Inc.Inventors: Lei Liao, Yichuan Ling, Zhiyu Huang, Hideyuki Kanzawa, Fenglin Wang, Rajesh Prasad, Yung-Chen Lin, Chi-I Lang, Ho-yung David Hwang, Lequn Liu
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Publication number: 20240071817Abstract: Exemplary semiconductor processing methods may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. A semiconductor substrate may be positioned within the processing region. The methods may include forming a layer of low dielectric constant material on the semiconductor substrate. The methods may include purging the processing region of the one or more deposition precursors. A plasma power may be maintained at less than or about 750 W while purging the processing region. The methods may include forming an interface layer on the layer of low dielectric constant material. The methods may include forming a cap layer on the interface layer.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Applicant: Applied Materials, Inc.Inventors: Ruitong Xiong, Rui Lu, Xiaobo Li, Bo Xie, Yijun Liu, Li-Qun Xia
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Publication number: 20240072059Abstract: Disclosed herein are approaches for forming a FDSOI, single diffusion break device. In one approach, a method may include providing a plurality of gates in a stack of layers, wherein each gate of the plurality of gates comprises a sidewall spacer, and forming a mask over the stack of layers, wherein an opening through the mask exposes a dummy gate of the plurality of gates. The method may further comprise etching a gate material of the dummy gate to form a recess in a silicon-on-insulator (SOI) layer of the stack of layers, implanting oxygen ions into the recess, and annealing the SOI layer within the recess to form an isolation area.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: Applied Materials, Inc.Inventors: Sipeng Gu, Qintao Zhang
