Patents Assigned to Applied Materials
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Publication number: 20220310531Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Applicant: Applied Materials, Inc.Inventors: Amirhasan Nourbakhsh, Lan Yu, Joseph F. Salfelder, Ki Cheol Ahn, Tyler Sherwood, Siddarth Krishnan, Michael Jason Fronckowiak, Xing Chen
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Publication number: 20220310909Abstract: Methods of forming a stack without damaging underlying layers are discussed. The encapsulation layer and dielectric layer are highly conformal, have low etch rates, and good hermeticity. These films may be used to protect chalcogen materials in PCRAM devices or any substrates sensitive to oxygen or moisture. Some embodiments utilize a two-step process comprising a first ALD process to form an encapsulation layer and oxidation process to form a dielectric layer.Type: ApplicationFiled: March 24, 2021Publication date: September 29, 2022Applicant: Applied Materials, Inc.Inventors: Maribel Maldonado-Garcia, Cong Trinh, Mihaela A. Balseanu
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Publication number: 20220307134Abstract: Methods for plasma enhanced atomic layer deposition (PEALD) of low-? films are described. A method of depositing a film comprises exposing a substrate to a silicon precursor having the general formula (I) wherein R1, R2, R3, R4, R5, and R6 are independently selected from hydrogen (H), substituted alkyl, or unsubstituted alkyl; purging the processing chamber of the silicon precursor; exposing the substrate to a carbon monoxide (CO) plasma to form one or more of a silicon oxycarbide (SiOC) or silicon oxycarbonitride (SiOCN) film on the substrate; and purging the processing chamber.Type: ApplicationFiled: June 15, 2022Publication date: September 29, 2022Applicant: Applied Materials, Inc.Inventors: Shuaidi Zhang, Ning Li, Mihaela A. Balseanu
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Patent number: 11456178Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.Type: GrantFiled: June 15, 2021Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Steven C. H. Hung, Benjamin Colombeau, Abhishek Dube, Sheng-Chin Kung, Patricia M. Liu, Malcolm J. Bevan, Johanes F. Swenberg
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Patent number: 11456345Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in an organic light-emitting diode (OLED) display are described herein. The overhang structures are permanent to the sub-pixel circuit. The overhang structures include a conductive oxide. A first configuration of the overhang structures includes a base portion and a top portion with the top portion disposed on the base portion. In a first sub-configuration, the base portion includes the conductive oxide of at least one of a TCO material or a TMO material. In a second sub-configuration, the base portion includes a metal alloy material and the conductive oxide of a metal oxide surface. A second configuration of the overhang structures includes the base portion and the top portion with a body portion disposed between the base portion and the top portion. The body portion includes the metal alloy body and the metal oxide surface.Type: GrantFiled: May 11, 2022Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Ji-young Choung, Chung-Chia Chen, Yu Hsin Lin, Jungmin Lee, Dieter Haas, Si Kyoung Kim
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Patent number: 11454876Abstract: Methods of coating extreme ultraviolet (EUV) reticle carrier assemblies are disclosed. The method includes depositing an adhesion layer on the EUV reticle carrier assembly, depositing at least one EUV absorber layer on the EUV reticle carrier assembly and depositing a stress-relieving layer on EUV reticle carrier assembly. The coated EUV reticle carrier assemblies exhibit reduced particle defect generation during EUV mask blank manufacturing.Type: GrantFiled: December 14, 2020Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Binni Varghese, Vibhu Jindal, Azeddine Zerrade, Shiyu Liu, Ramya Ramalingam
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Patent number: 11456205Abstract: Methods of producing grating materials with variable height fins are provided. In one example, a method may include providing a mask layer atop a substrate, the mask layer including a first opening over a first processing area and a second opening over a second processing area. The method may further include etching the substrate to recess the first and second processing areas, forming a grating material over the substrate, and etching the grating material in the first and second processing areas to form a plurality of structures oriented at a non-zero angle with respect to a vertical extending from a top surface of the substrate.Type: GrantFiled: May 11, 2020Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Morgan Evans, Joseph C. Olson, Rutger Meyer Timmerman Thijssen, Daniel Distaso, Ryan Boas
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Patent number: 11456171Abstract: Exemplary methods of forming a semiconductor structure may include forming a liner along sidewalls of a trench defined from a first surface of a semiconductor substrate. The liner may extend along the first surface of the semiconductor substrate. The methods may include filling the trench with a dielectric material. The methods may include removing the dielectric material and the liner from the first surface of the semiconductor substrate. The methods may include forming a layer of the liner across the first surface of the semiconductor substrate and the trench defined within the semiconductor substrate.Type: GrantFiled: November 20, 2020Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Lan Yu, Tyler Sherwood
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Patent number: 11456197Abstract: The disclosure describes devices, systems, and methods for causing a factory interface of an electronic device manufacturing system to be moveable between a first position and a second position. An electronic device manufacturing system can include a transfer chamber, processing chambers connected to the transfer chamber, a load lock connected to the transfer chamber, and a factory interface connected to the load lock. The factory interface can be moveable between a first position and a second position. The factory interface, while oriented in the first position, is positioned for transfer of one or more substrates between the factory interface and the load lock, where at least one of the transfer chamber or the load lock are inaccessible for maintenance while the factory interface is oriented at the first position. The factory interface, while oriented in the second position, is positioned to provide maintenance access to at least one of the transfer chamber or the load lock.Type: GrantFiled: April 2, 2020Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Michael R. Rice, Juan Carlos Rocha-Alvarez, Jeffrey C. Hudgens
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Patent number: 11456301Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.Type: GrantFiled: July 16, 2020Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Arvind Kumar, Mahendra Pakala, Sanjeev Manhas, Satendra Kumar Gautam
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Patent number: 11453099Abstract: Some implementations of a retaining ring has an inner surface having a first portion formed of multiple planar facets and a second portion that adjoins the first portion along a boundary and includes a frustoconical surface that is sloped downwardly from outside in. Some implementations of the retaining ring have a crenellated or serpentine inner surface, and/or an inner surface with alternating region of different surface properties or different tilt angles.Type: GrantFiled: December 9, 2019Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Steven Mark Reedy, Simon Yavelberg, Jeonghoon Oh, Steven M. Zuniga, Andrew J. Nagengast, Samuel Chu-Chiang Hsu, Gautam Shashank Dandavate
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Patent number: 11456179Abstract: Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include providing a patterned hardmask over a substrate, and providing, from an ion source, a plasma treatment to a first section of the patterned hardmask, wherein a second section of the patterned hardmask does not receive the plasma treatment. The method may further include etching the substrate to form a plurality of fins in the substrate, wherein the first section of the patterned hardmask is etched faster than the second section of the patterned hardmask.Type: GrantFiled: July 14, 2020Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventor: Min Gyu Sung
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Patent number: 11453097Abstract: A substrate polishing apparatus is disclosed that includes a polishing platform having two or more zones, each zone adapted to receive a different slurry component. A substrate polishing system is provided having a holder to hold a substrate, a polishing platform having a polishing pad, and a distribution system adapted to dispense, in a timed sequence, at least two different slurry components selected from a group consisting of an oxidation slurry component, a material removal slurry component, and a corrosion inhibiting slurry component. Polishing methods and systems adapted to polish substrates are provided, as are numerous other aspects.Type: GrantFiled: November 21, 2019Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Rajeev Bajaj, Thomas H. Osterheld, Hung Chen, Terrance Y. Lee
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Patent number: 11456161Abstract: The systems and methods discussed herein are associated with substrate support pedestals used in processing chambers to manufacture semiconductors, electronics, optics, and other devices. The substrate support pedestals include an electrostatic chuck body bonded to a cooling base via a bond layer. A gas flow passage is formed between a top surface of the electrostatic chuck body and a bottom surface of the cooling base, and a porous plug is positioned in the gas flow passage. The gas flow passage passes through a hole in the bond layer and the porous plug and has a swept volume physically shielded from an inside edge of the hole in the bond layer, protecting the bond layer from erosion.Type: GrantFiled: May 24, 2019Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Steven Joseph Larosa, Stephen Prouty
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Publication number: 20220301915Abstract: Exemplary support assemblies may include an electrostatic chuck body defining a support surface that defines a substrate seat. The assemblies may include a support stem coupled with the chuck body. The assemblies may include a heater embedded within the chuck body. The assemblies may include a first bipolar electrode embedded within the electrostatic chuck body between the heater and support surface. The assemblies may include a second bipolar electrode embedded within the chuck body between the heater and support surface. The assemblies may include at least one inner capacitive sensor embedded within the electrostatic chuck body at a position proximate a center of the substrate seat. The assemblies may include at least one outer capacitive sensor embedded within the electrostatic chuck body at a position proximate a peripheral edge of the substrate seat.Type: ApplicationFiled: March 22, 2021Publication date: September 22, 2022Applicant: Applied Materials, Inc.Inventors: Job George Konnoth Joseph, Syam Sundeep Boosa, Gopu Krishna, Rupankar Choudhury
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Publication number: 20220301913Abstract: Semiconductor substrate support assemblies may include an electrostatic chuck body having a substrate support surface. The electrostatic chuck body may define a plurality of protrusions extending from the substrate support surface. The assemblies may include an electrode embedded within the electrostatic chuck body. The electrode may define apertures through the electrode in line with the plurality of protrusions extending from the substrate support surface.Type: ApplicationFiled: March 18, 2021Publication date: September 22, 2022Applicant: Applied Materials, Inc.Inventors: Sumanth Banda, Vladimir Knyazik, Stephen D. Prouty
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Publication number: 20220301127Abstract: A system for optimizing images may include a camera sensor configured to capture a first image, and an image pipeline configured to receive the first image from the camera sensor. The image pipeline may identify a plurality of regions in the first image, and generate a second image from the plurality of regions in the first image. The second image may be smaller than the first image such that the second image can be more efficiently processed by a neural network. The system may also include a neural network configured to receive the second image from the image pipeline and train the neural network using the second image or process the second image using the neural network.Type: ApplicationFiled: March 18, 2021Publication date: September 22, 2022Applicant: Applied Materials, Inc.Inventor: Itai Leshniak
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Publication number: 20220301887Abstract: Embodiments of this disclosure provide methods for etching ruthenium. A halide-containing-gas is flowed into a substrate processing chamber, and then an oxygen-containing gas is flowed into the substrate processing chamber. The methods may include atomic layer etching (ALE). The methods may be conducted at higher processing chambers, permitting deposition and etching of ruthenium to be conducted in the same processing chamber.Type: ApplicationFiled: March 16, 2021Publication date: September 22, 2022Applicant: Applied Materials, Inc.Inventors: Nasrin Kazem, Jeffrey W. Anthis
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Publication number: 20220302339Abstract: Exemplary processing methods of forming an LED structure on a backplane may include coupling a first transfer substrate with an LED source substrate. The LED source substrate may include a plurality of fabricated LEDs. The coupling of the first transfer substrate may be produced with a first coupling material extending between the first transfer substrate and each LED of the plurality of fabricated LEDs. The methods may include separating the LED source substrate from the LEDs. The methods may include coupling a second transfer substrate with the first transfer substrate. The coupling of the first transfer substrate may be produced with a second coupling material extending between the second transfer substrate and each LED of the plurality of fabricated LEDs. The methods may include separating the first transfer substrate from the second transfer substrate. The methods may include bonding the plurality of fabricated LEDs with a display backplane.Type: ApplicationFiled: February 14, 2022Publication date: September 22, 2022Applicant: Applied Materials, Inc.Inventors: Hou T. Ng, Nag Patibandla, Uma Sridhar, Sivapackia Ganapathiappan, Mingwei Zhu
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Publication number: 20220301883Abstract: Exemplary methods of etching gallium oxide from a semiconductor substrate may include flowing a first reagent in a substrate processing region housing the semiconductor substrate. The first reagent may include HX. X may be at least one of fluorine, chlorine, and bromine. The semiconductor substrate may include an exposed region of gallium oxide. Fluorinating the exposed region of gallium oxide may form a gallium halide and H2O. The methods may include flowing a second reagent in the substrate processing region. The second reagent may be at least one of trimethylgallium, tin acetylacetonate, tetramethylsilane, and trimethyltin chloride. The second reagent may promote a ligand exchange where a methyl group may be transferred to the gallium halide to form a volatile Me2GaY or Me3Ga. Y may be at least one of fluorine, chlorine, and bromine from the second reagent. The methods may include recessing a surface of the gallium oxide.Type: ApplicationFiled: June 9, 2022Publication date: September 22, 2022Applicant: Applied Materials, Inc.Inventors: Feng Q. Liu, Lisa J. Enman, Lakmal C. Kalutarage, Mark J. Saly