Abstract: Gas distribution apparatus, processing chambers and methods using a dead volume-free valve are described. The valve has a first inlet line with upstream and downstream ends and a second inlet line with a downstream end that connects to the first inlet line. A sealing surface at the downstream end of the second inlet line separates the first inlet line from the second inlet line preventing fluid communication between the first inlet line and the second inlet line.

Abstract: An apparatus with a grating structure and a method for forming the same are disclosed. The grating structure includes forming a recess in a grating layer. A plurality of channels is formed in the grating layer to define slanted grating structures therein. The recess and the slanted grating structures are formed using a selective etch process.

Abstract: Exemplary deposition methods may include delivering a silicon-containing precursor and an inert gas to a processing region of a semiconductor processing chamber. The methods may include providing a hydrogen-containing precursor with the silicon-containing precursor and the inert gas. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a silicon-containing material on a substrate disposed within the processing region of the semiconductor processing chamber. The processing region may be maintained free of helium delivery during the deposition method.

Abstract: Exemplary semiconductor processing chamber showerheads include an inner core region. The inner core region may define a plurality of apertures. The showerheads may include an outer core region disposed about an outer periphery of the inner core region. The outer core region may define an annular channel. The showerheads may include a heating element disposed within the annular channel. The showerheads may include an annular liner disposed about an outer periphery of the outer core region. The inner core region and the outer core region may include an aluminum alloy. The annular liner may have a lower thermal conductivity than the aluminum alloy.

Abstract: Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing a boron-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor, the carbon-containing precursor, and the boron-containing precursor at a temperature above about 250° C. The methods may include forming a silicon-and-carbon-containing layer on the substrate.

Abstract: Methods of depositing a metal film with high purity are discussed. A catalyst enhanced CVD process is utilized comprising an alkyl halide catalyst soak and a precursor exposure. The precursor comprises a metal precursor having the general formula (I): M-L1(L2)y, wherein M is a metal, L1 is an aromatic ligand, L2 is an aliphatic ligand, and y is a number in the range of from 2 to 8 to form a metal film on the substrate surface, wherein the L2 comprises 1,5-hexdiene, 1,4-hexadiene, and less than 5% of 1,3-hexadiene. Selective deposition of a metal film with high purity on a metal surface over a dielectric surface is described.

Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

Abstract: Physical vapor deposition methods for reducing the particulates deposited on the substrate are disclosed. The pressure during sputtering can be increased to cause agglomeration of the particulates formed in the plasma. The agglomerated particulates can be moved to an outer portion of the process chamber prior to extinguishing the plasma so that the agglomerates fall harmlessly outside of the diameter of the substrate.

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Abstract: Exemplary substrate processing systems may include a transfer region housing defining an internal volume. A sidewall of the transfer region housing may define a sealable access for providing and receiving substrates. The systems may include a plurality of substrate supports disposed within the transfer region. The systems may also include a transfer apparatus having a central hub including a first shaft and a second shaft concentric with and counter-rotatable to the first shaft. The transfer apparatus may include a first end effector coupled with the first shaft. The first end effector may include a plurality of first arms. The transfer apparatus may also include a second end effector coupled with the second shaft. The second end effector may include a plurality of second arms having a number of second arms equal to the number of first arms of the first end effector.

Abstract: Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an ?-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).

Abstract: A method for creating a flat optical structure is disclosed, having steps of providing a substrate, etching at least one nanotrench in the substrate, placing a dielectric material in the at least one nanotrench in the substrate and encapsulating a top of the substrate with a film.

Abstract: Described are lanthanide-containing metal coordination complexes which may be used as precursors in thin film depositions, e.g. atomic layer deposition processes. More specifically, described are homoleptic lanthanide-aminoalkoxide metal coordination complexes, lanthanide-carbohydrazide metal coordination complexes, and lanthanide-diazadiene metal coordination complexes. Additionally, methods for depositing lanthanide-containing films through an atomic layer deposition process are described.

Abstract: An ion implantation system, including an ion source and extraction system, arranged to generate an ion beam at a first energy, and a linear accelerator, disposed downstream of the ion source, the linear accelerator arranged to receive the ion beam as a bunched ion beam accelerate the ion beam to a second energy, greater than the first energy. The linear accelerator may include a plurality of acceleration stages, wherein a given acceleration stage of the plurality of acceleration stages comprises: a drift tube assembly, arranged to conduct the ion beam; a resonator, electrically coupled to the drift tube assembly; and an RF power assembly, coupled to the resonator, and arranged to output an RF signal to the resonator. As such, the given acceleration stage does not include a quadrupole element.

Abstract: An electrostatic chuck comprises a ceramic body comprising an embedded electrode and a first ceramic coating on a surface of the ceramic body, wherein the first ceramic coating fills pores in the ceramic body. The electrostatic chuck further comprises a second ceramic coating on the first ceramic coating and a plurality of elliptical mesas on the second ceramic coating, the plurality of elliptical mesas having rounded edges.

Abstract: Disclosed herein is a system for pulsed DC biasing and clamping a substrate. The system can include a plasma chamber having an ESC for supporting a substrate. An electrode is embedded in the ESC and is electrically coupled to a biasing and clamping circuit. The biasing and clamping circuit includes at least a shaped DC pulse voltage source and a clamping network. The clamping network includes a DC voltage source and a diode, and a resistor. The shaped DC pulse voltage source and the clamping network are connected in parallel. The biasing and clamping network automatically maintains a substantially constant clamping voltage, which is a voltage drop across the electrode and the substrate when the substrate is biased with pulsed DC voltage, leading to improved clamping of the substrate.

Abstract: Embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The device includes a plurality of sub-pixels, each sub-pixel of the plurality of sub-pixels defined by adjacent pixel-defining layer (PDL) structures with inorganic overhang structures disposed on the PDL structures, each sub-pixel having an anode, organic light-emitting diode (OLED) material disposed on the anode, and a cathode disposed on the OLED material. The device is made by a process including the steps of: depositing the OLED material and the cathode by evaporation deposition, and depositing an encapsulation layer disposed over the cathode.

Abstract: Embodiments provided herein generally include apparatus, plasma processing systems and methods for generation of a waveform for plasma processing of a substrate in a processing chamber. One embodiment includes a waveform generator having a voltage source circuitry, a first switch coupled between the voltage source circuitry and a first output node of the waveform generator, the first output node being configured to be coupled to a chamber, and a second switch coupled between the first output node and electrical ground node. The waveform generator also includes a third switch coupled between the voltage source circuitry and a second output node of the waveform generator, the second output node being configured to be coupled to the chamber, and a fourth switch coupled between the second output node and the electrical ground node.