Abstract: Monitoring operations of a polishing system includes obtaining a time-based sequence of reference images of a component of the polishing system performing operations during a test operation of the polishing system, receiving from a camera a time-based sequence of monitoring images of an equivalent component of an equivalent polishing system performing operations during polishing of a substrate, determining a difference value for the time-based sequence of monitoring images by comparing the time-based sequence of reference images to the time-based sequence of monitoring image using an image processing algorithm, determining whether the difference value exceeds a threshold, and in response to determining the difference value exceeds the threshold, indicating an excursion.

Abstract: A method of plating substrates may include placing a substrate in a plating chamber comprising a liquid, and applying a current to the liquid in the plating chamber to deposit a metal on exposed portions of the substrate, where the current may include alternating cycles of a forward plating current and a reverse deplating current. To determine the current characteristics, a model of a substrate may be simulated during the plating process to generate data points that relate characteristics of the plating process and a pattern on the substrate to a range nonuniformity of material formed on the substrate during the plating process. Using information from the data points, values for the forward and reverse currents may be derived and provided to the plating chamber to execute the plating process.

Abstract: Describes are shutter disks comprising one or more of titanium (Ti), barium (Ba), or cerium (Ce) for physical vapor deposition (PVD) that allows pasting to minimize outgassing and control defects during etching of a substrate. The shutter disks incorporate getter materials that are highly selective to reactive gas molecules, including O2, CO, CO2, and water.

Abstract: A method and a system for illuminating a substrate, the system may include an acousto-optic device (AOD); and an etendue expanding optical module. The AOD may include a surface having an illuminated region; wherein the illuminated region is configured to receive a collimated input beam while being fed with a control signal that causes the illuminated region to output illuminated region output beams that are collimated and exhibit deflection angles that scan, during a scan period, a deflection angular range. The etendue expanding optical module is configured to convert the illuminated region output beams to collimated output beams that impinge on an output aperture; wherein a collimated output beam has a width that exceeds a width of an illuminated region output beam; and wherein the etendue expanding optical module comprises a Dammann grating that is configured to output diffraction patterns, each diffraction pattern comprises diffraction orders that cover a continuous angular range.

Abstract: Exemplary deposition methods may include introducing hydrogen into a processing chamber, a powder disposed within a processing region of the processing chamber. The method may include striking a first plasma in the processing region, the first plasma including energetic hydrogen species. The method may include exposing the powder to the energetic hydrogen species in the processing region. The method may include chemically reducing the powder through a reaction of the powder with the energetic hydrogen species. The method may include removing process effluents including unreacted hydrogen from the processing region. The method may also include forming a layer of material on grains of the powder within the processing region.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes combining selective recess of a sacrificial layer and isotropic etching of a silicon layer in order to form a protective cap that will allow the silicon layer of the substrate to be etched without affecting the sacrificial layer.

Abstract: A method of delayering a sample that includes a second layer formed under a first layer, where the first and second layers are different materials or different texture, the method including: acquiring a plurality of gray scale images of the region of interest in an iterative process by alternating a sequence of delayering the region of interest with a first charged particle beam and imaging a surface of the region of interest with a second charged particle beam; after each iteration of acquiring a gray scale image, calculating an entropy of the acquired gray scale image and calculating a second derivative of the entropy; determining whether a transition from the first layer to the second layer occurred based on the second derivative of the entropy; and if it is determined that a transition from the first layer to the second layer did not occur, proceeding with a next iteration of acquiring a plurality of gray scale images, and if it is determined that a transition from the first layer to the second layer did

Abstract: Embodiments of the disclosure relate to methods for reducing or eliminating the first wafer effect after chamber cleans for plasma etch processes. In some embodiments, the wafer support is maintained at an elevated temperature relative to the etch process. In some embodiments, the etch process is a NF3+NH3 plasma etch to remove native oxides from a silicon substrate.

Abstract: Disclosed herein are approaches for reducing EUV dose during formation of a patterned metal oxide photoresist. In one approach, a method may include providing a stack of layers atop a substrate, the stack of layers comprising a film layer, and implanting the film layer with ions. The method may further include depositing a metal oxide photoresist atop the film layer, and patterning the metal oxide photoresist.

Abstract: Embodiments of the present disclosure generally relate to methods and apparatus for backside stress engineering of substrates to combat film stresses and bowing issues. In one embodiment, a method of depositing a film layer on a backside of a substrate is provided. The method includes flipping a substrate at a factory interface so that the backside of the substrate is facing up, and transferring the flipped substrate from the factory interface to a physical vapor deposition chamber to deposit a film layer on the backside of the substrate. In another embodiment, an apparatus for depositing a backside film layer on a backside of a substrate, which includes a substrate supporting surface configured to support the substrate at or near the periphery of the substrate supporting surface without contacting an active region on a front side of the substrate.

Abstract: Exemplary methods of manufacturing a semiconductor cover wafer may include sintering aluminum nitride particles into a substrate characterized by a thickness and characterized by a disc shape. The methods may include grinding a surface of the substrate to reduce the thickness to less than or about 2 mm. The methods may include polishing the surface of the substrate to reduce a roughness. The methods may include annealing the substrate at a temperature of greater than or about 800° C. for a time period of greater than or about 60 minutes.

Abstract: Processing methods may be performed to expose a contact region on a semiconductor substrate. The methods may include selectively removing a first region of a silicon material between source/drain regions of a semiconductor substrate to expose a first region of oxide material. The methods may include forming a liner over the first region of oxide material and contacting second regions of the silicon material proximate the source/drain regions of the semiconductor substrate. The methods may also include selectively removing the second regions of the silicon material proximate the source/drain regions of the semiconductor substrate to expose a second region of the oxide material. The methods may further include selectively removing the second region of the oxide material from a surface of a contact in the semiconductor structure.

Abstract: A crested barrier memory device may include a first electrode, a first self-rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately ?0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.

Abstract: Embodiments disclosed herein include a housing for a source assembly. In an embodiment, the housing comprises a conductive body with a first surface and a second surface opposite from the first surface, and a plurality of openings through a thickness of the conductive body between the first surface and the second surface. In an embodiment, the housing further comprises a channel into the first surface of the conductive body, and a cover over the channel. In an embodiment, a first stem over the cover extends away from the first surface, and a second stem over the cover extends away from the first surface. In an embodiment, the first stem and the second stem open into the channel.

Abstract: Embodiments disclosed herein include a process power controller for a plasma processing tool. In an embodiment, the process power controller includes a process power source optimizer, a source predictor, and a process uniformity controller. In an embodiment, the source predictor is communicatively coupled to the process power source optimizer and the process uniformity controller.

Abstract: The subject matter of this specification can be implemented in, among other things, a method, system, and/or device to receive current metrology data for an operation on a current sample in a fabrication process. The metrology data includes a current value for a parameter at each of one or more locations on the current sample. The method further includes determining a current rate of change of the parameter value for each of the one or more locations. The current rate of change is associated with the current sample. The method further includes identifying one or more violating locations each having an associated current rate of change of the parameter value that is greater than an associated reference rate of change of the parameter value, and identifying an instance of abnormality of the fabrication process based on the one or more violating locations.

Abstract: The present disclosure generally relates to a substrate processing chamber, a substrate processing apparatus, and a substrate processing method for self-assembled monolayer (SAM) deposition of low vapor pressure organic molecules (OM) followed by further substrate processing, such as atomic layer deposition.

Abstract: Plasma source assemblies comprising a housing with an RF hot electrode having a body and a plurality of source electrodes extending vertically from the RF hot electrode toward the opening in a front face of the housing are described. Processing chambers incorporating the plasma source assemblies and methods of using the plasma source assemblies are also described.

Abstract: Chalcogen silane precursors are described. Methods for depositing a silicon nitride (SixNy) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (SixNy) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).

Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in an organic light-emitting diode (OLED) display are described herein. The overhang structures are permanent to the sub-pixel circuit. The overhang structures include a conductive oxide. A first configuration of the overhang structures includes a base portion and a top portion with the top portion disposed on the base portion. In a first sub-configuration, the base portion includes the conductive oxide of at least one of a TCO material or a TMO material. In a second sub-configuration, the base portion includes a metal alloy material and the conductive oxide of a metal oxide surface. A second configuration of the overhang structures includes the base portion and the top portion with a body portion disposed between the base portion and the top portion. The body portion includes the metal alloy body and the metal oxide surface.