Abstract: Chemical precursor recovery systems and methods of recovering and reusing semiconductor manufacturing chemistry are disclosed. The recovery systems include a cold trap inlet line in fluid communication with a plurality of cold traps and a cold trap outlet line. The plurality of cold traps is configured to condense the chemical precursors and are arranged based on semiconductor manufacturing process conditions.

Abstract: Methods of forming semiconductor devices by enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a barrier layer. The methods include exposing a substrate with a metal surface, a dielectric surface and an aluminum oxide surface or an aluminum nitride surface to a blocking molecule, such as a boron-containing compound, to form the blocking layer selectively on the metal surface over the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface.

Abstract: Methods of depositing a nanocrystalline diamond film are described. The method may be used in the manufacture of integrated circuits. Methods include treating a substrate with a plasma to form a treated substrate surface, incubating the treated substrate with a carbon-rich plasma to nucleate diamond particles on the treated substrate surface, followed by treating the substrate with a plasma to form a nanocrystalline diamond film. The resulting nanocrystalline diamond films are formed on an interfacial oxide-rich amorphous layer between the nanocrystalline diamond film and a silicon substrate.

Abstract: Apparatus and methods to process one or more substrates are described. A plurality of process stations are arranged in a circular configuration around a rotational axis. A support assembly with a rotatable center base defining a rotational axis, at least two support arms extending from the center base and heaters on each of the support arms is positioned adjacent the processing stations so that the heaters can be moved amongst the various process stations to perform one or more process condition. The support assembly configured to offset the position of the substrate with respect to the processing stations.

Abstract: Disclosed herein are approaches for treating a film layer of a semiconductor device to modify an etch resistance of the film later. In one approach, a method may include forming a first film over a substrate base, depositing a second film over the first film, and introducing an inert species into the second film while the second film is deposited over the first film, wherein the inert species increases an etch-resistance of a first portion of the first film. The method may further include removing the second film by stopping deposition of the second film while continuing to introduce the inert species into the second film.

Abstract: Embodiments provided herein generally include apparatus, e.g., plasma processing systems, and methods for the plasma processing of a substrate in a processing chamber. Some embodiments are directed to a waveform generator. The waveform generator generally includes a first voltage stage having: a first voltage source; a first switch; and a second switch, where a first terminal of the first voltage source is coupled to a first terminal of the first switch, and where a second terminal of the first voltage source is coupled to a first terminal of the second switch. The waveform generator also includes a current stage coupled to a common node between second terminals of the first switch and the second switch, the current stage having a current source and a third switch coupled to the current source.

Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor in the processing region. The plasma may be at least partially formed by an RF power operating at between about 50 W and 1,000 W, at a pulsing frequency below about 100,000 Hz, and at a duty cycle between about 5% and 95%. The methods may include forming a layer of material on the substrate. The layer of material may include a silicon-containing material.

Abstract: An ion extraction assembly for an ion source is provided. The ion extraction assembly may include a plurality of electrodes, wherein the plurality of electrodes comprises: a plasma-facing electrode, arranged for coupling to a plasma chamber; and a substrate-facing electrode, disposed outside of the plasma-facing electrode. The at least one electrode of the plurality of electrodes may include a grid structure, defining a plurality of holes, wherein the at least one electrode has a non-uniform thickness, wherein a first grid thickness in a middle region of the at least one electrode is different than a second grid thickness, in an outer region of the at least one electrode.

Abstract: Disclosed herein are methods and systems for analyzing a cross-sectional feature of a structural element on a semiconductor wafer to determine whether an isolated or a systemic failure to reach preselected parameters occurred.

Abstract: Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.

Abstract: Embodiments described herein relate to a device including a substrate, a plurality of adjacent pixel-defining layer (PDL) structures disposed over the substrate, and a plurality of sub-pixels. Each sub-pixel includes adjacent first overhangs, adjacent second overhangs, an anode, a hole injection layer (HIL) material, an additional organic light emitting diode (OLED) material, and a cathode. Each first overhang is defined by a body structure disposed on and extending laterally past a base structure disposed on the PDL structure. Each second overhang is defined by a top structure disposed on and extending laterally past the body structure. The HIL material is disposed over and in contact with the anode and disposed under the adjacent first overhangs. The additional OLED material is disposed on the HIL material and extends under the first overhang.

Abstract: Exemplary semiconductor processing systems may include a chamber body having sidewalls and a base. The semiconductor processing systems may include a substrate support extending through the base of the chamber body. The substrate support may include a support plate. The substrates support may include a shaft coupled with the support plate. The semiconductor processing systems may include a liner positioned within the chamber body and positioned radially outward of a peripheral edge of the support plate. An inner surface of the liner may include an emissivity texture.

Abstract: Exemplary substrate support assemblies may include an electrostatic chuck body. The body may include a support plate defining a substrate support surface. The body may include a base plate coupled with the support plate. A bottom surface of the base plate may define an annular recess. The body may include a cooling plate coupled with the base plate. The assemblies may include a support stem coupled with the body. The assemblies may include a heater embedded within the body. The assemblies may include one or more electrodes embedded within the body. The assemblies may include an annular plate disposed within the annular recess. The annular plate may have a thermal conductivity of less than about 20 W/mK. The assemblies may include a vacuum sealing element disposed between the annular plate and the cooling plate. The assemblies may include a thermal gasket disposed radially inward of the vacuum sealing element.

Abstract: Implementations of the present disclosure generally relates to a transfer chamber coupled to at least one vapor phase epitaxy chamber a plasma oxide removal chamber coupled to the transfer chamber, the plasma oxide removal chamber comprising a lid assembly with a mixing chamber and a gas distributor; a first gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; a second gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; a third gas inlet formed through a portion of the lid assembly and in fluid communication with the mixing chamber; and a substrate support with a substrate supporting surface; a lift member disposed in a recess of the substrate supporting surface and coupled through the substrate support to a lift actuator; and a load lock chamber coupled to the transfer chamber.

Abstract: Molybdenum(0) coordination complexes comprising ligands which each coordinate to the metal center by nitrogen or phosphorous are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum nitride). The exposures can be sequential or simultaneous.

Abstract: Sealing bodies comprising a first body having a top surface and a bottom surface defining a thickness thereof. An inlet conduit and an outlet conduit are in fluid communication with one or more of the top surface, the bottom surface, or a top channel formed in the top surface or a bottom channel formed in the bottom surface.

Abstract: Exemplary processing methods may include providing a component for semiconductor processing to a processing region of a processing chamber. The methods may include providing one or more deposition precursors to the processing region. The one or more deposition precursors may include a metal-containing precursor and a fluorine-containing precursor. The methods may include depositing a layer of material on the component for semiconductor processing in the processing region. The layer of material comprises a metal-and-fluorine-containing material.

Abstract: A three-dimensional semiconductor (3D) device. The 3D device may include a substrate, and a monocrystalline layer stack. The monocrystalline layer stack may include at least one monocrystalline semiconductor layer, separated from, and disposed over a main surface of the substrate. The 3D device may further include a plurality of epitaxial heterostructures, integrally grown from the at least one monocrystalline semiconductor layer. As such, a first epitaxial heterostructure may be disposed on a lower surface of the at least one monocrystalline semiconductor layer, facing the substrate, and wherein a second epitaxial heterostructure may be disposed on an upper surface of the monocrystalline semiconductor layer, opposite the lower surface.

Abstract: A first robot arm places a calibration object into a load lock that separates a factory interface from a transfer chamber using a first taught position. A second robot arm retrieves the calibration object from the load lock using a second taught position. A controller determines, using a sensor, a first offset amount between a calibration object center of the calibration object and a pocket center of the second robot arm. The controller determines a characteristic error value that represents a misalignment between the first taught position of the first robot arm and the second taught position of the second robot arm based on the first offset amount. The first robot arm or the second robot arm uses the first characteristic error value to compensate for the misalignment for objects transferred between the first robot arm and the second robot arm via the load lock.

Abstract: Molybdenum(0) coordination complexes comprising an arene ligand and one or more neutral ligands which coordinate to the metal center by carbon, nitrogen or phosphorous are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum nitride). The exposures can be sequential or simultaneous.