Abstract: Methods for depositing metal films using a metal halide and metal organic precursors are described. The substrate is exposed to a first metal precursor and a second metal precursor to form the metal film. The exposures can be sequential or simultaneous. The metal films are relatively pure with a low carbon content.

Abstract: Methods and apparatus for cleaning a dielectric tube are described. The dielectric tube is exposed to a cleaning gas comprising a fluorine-containing compound and a microwave plasma is generated. The dielectric tube is cleaned to restore transparency and increase electronic coupling between the microwave waveguide and the plasma through the dielectric tube.

Abstract: Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a depth of the array of contact opening pairs varies in the first direction. The method may further include forming a second lithography mask over the film stack, and performing a second series of alternating lithography and etch processes, wherein an opening through the second lithography mask is expanded in a second direction following each etch process, and wherein the depth of the array of contact opening pairs varies in the second direction.

Abstract: Methods for depositing an amorphous carbon layer on a substrate and for filling a substrate feature with an amorphous carbon gap fill are described. The method comprises performing a deposition cycle comprising: introducing a hydrocarbon source into a processing chamber; introducing a plasma initiating gas into the processing chamber; generating a plasma in the processing chamber at a temperature of greater than 600° C.; forming an amorphous carbon layer on a substrate with a deposition rate of greater than 200 nm/hr; and purging the processing chamber.

Abstract: Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a depth of the array of contact opening pairs varies in the first direction. The method may further include forming a second lithography mask over the film stack, and performing a second series of alternating lithography and etch processes, wherein an opening through the second lithography mask is expanded in a second direction following each etch process, and wherein the depth of the array of contact opening pairs varies in the second direction.

Abstract: Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. The method comprises forming a P-dipole stack and an N-dipole stack on a semiconductor substrate by: depositing an interfacial layer (e.g., silicon oxide (SiOx)) on the top surface of the channel; depositing a hafnium-containing layer comprising hafnium oxide (HfOx) and having a thickness of less than or equal to 5 ? on the interfacial layer; and depositing a dipole layer comprising lanthanum nitride (LaN) on the hafnium-containing layer.

Abstract: Aspects generally relate to methods, systems, and apparatus for processing substrates using one or more amorphous carbon hardmask layers. In one aspect, film stress is altered while facilitating enhanced etch selectivity. In one implementation, a method of processing a substrate includes depositing one or more amorphous carbon hardmask layers onto the substrate, and conducting a rapid thermal anneal operation on the substrate after depositing the one or more amorphous carbon hardmask layers. The rapid thermal anneal operation lasts for an anneal time that is 60 seconds or less. The rapid thermal anneal operation includes heating the substrate to an anneal temperature that is within a range of 600 degrees Celsius to 1,000 degrees Celsius. The method includes etching the substrate after conducting the rapid thermal anneal operation.

Abstract: Exemplary semiconductor processing systems may include a chamber body including sidewalls and a base. The chamber body may define an interior volume. The systems may include a substrate support extending through the base of the chamber body. The substrate support may be configured to support a substrate within the interior volume. The systems may include a faceplate positioned within the interior volume of the chamber body. The faceplate may define a plurality of apertures through the faceplate. The systems may include a leveling apparatus seated on the substrate support. The leveling apparatus may include a plurality of piezoelectric pressure sensors.

Abstract: Examples of the present technology include semiconductor processing methods that may include generating a plasma from a deposition precursor in a processing region of a semiconductor processing chamber. The plasma may be generated at a delivered power within a first period of time when plasma power is delivered from a power source operating at a first duty cycle. The methods may further include transitioning the power source from the first duty cycle to a second duty cycle after the first period of time. A layer may be deposited on a substrate in the processing region of the semiconductor processing chamber from the generated plasma. The layer, as deposited, may be characterized by a thickness of 50 ? or less. Exemplary deposition precursors may include one or more silicon-containing precursors, and an exemplary layer deposited on the substrate may include an amorphous silicon layer.

Abstract: An apparatus with a grating structure and a method for forming the same are disclosed. The grating structure includes forming a recess in a grating layer. A plurality of channels is formed in the grating layer to define slanted grating structures therein. The recess and the slanted grating structures are formed using a selective etch process.

Abstract: A method includes receiving first sensor data associated with a first iteration of a first recipe operation of a substrate processing recipe. The method further includes determining disturbance data, the disturbance data being a difference between the first sensor data and first setpoint data of the first recipe operation. The method further includes determining, based at least in part on the disturbance data, a first actuation value associated with one or more components of a processing chamber. Actuation of the one or more components according to the first actuation value compensates for the disturbance data. The method further includes causing the actuation of the one or more components based on the first actuation value during a subsequent iteration of the first recipe operation of the substrate processing recipe to compensate for the disturbance data.

Abstract: Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component) obtained using directional etching to remove predetermined portions of a seed layer covering the substrate. In several embodiments, directional etching followed by selective deposition can enable fill material (e.g., metal) patterning in tight spaces without any voids or seams. Void-free material depositions may be used in a variety of semiconductor devices, such as transistors, dual work function stacks, dynamic random-access memory (DRAM), non-volatile memory, and the like.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract: Disclosed herein are a substrate sorter, an inspection and sorting system having the substrate sorter, and a method for the inspection and sorting system. The substrate sorter includes an annular gripper comprising a rotator and a plurality of vacuum applicators concyclically disposed around an axis, a carrier operable to move a substrate towards the rotator and into a loading region below the rotator, and an actuator coupled with the annular gripper and operable to rotate the rotator about the axis relative to the plurality of vacuum applicators while one or more of the plurality of vacuum applicators hold the substrate against the rotator.

Abstract: There is provided a system to examine a semiconductor specimen, the system comprising a processor and memory circuitry configured to obtain a training sample comprising an image of a semiconductor specimen and a design image based on design data, train a machine learning module, wherein the training includes minimizing a function representative of a difference between a simulated image generated by the machine learning module based on a given design image, and a corrected image corresponding to a given image after correction of pixel position of the given image in accordance with a given displacement matrix, wherein the minimizing includes optimizing parameters of the machine learning module and of the given displacement matrix, wherein the trained machine learning module is usable to generate a simulated image of a specimen based on a design image of the specimen.

Abstract: Methods of enhancing selective deposition are described. In some embodiments, a blocking layer is deposited on a metal surface before deposition of a dielectric. In some embodiments, a metal surface is functionalized to enhance or decrease its reactivity.

Abstract: A method includes measuring a subset of property values within a manufacturing chamber during a process performed on a substrate within the manufacturing chamber. The method further includes determining property values in the manufacturing chamber at locations removed from the locations the measurements are taken. The method further includes performing a corrective action based on the determined properties.

Abstract: A membrane for a CMP carrier head includes a circular lower portion that provides a substrate mounting surface for a central region of a substrate, a first plurality of flaps that extend upward from the circular lower portion to form a plurality of inner chambers, an annular upper portion that provides a lower surface for applying pressure to an annular outer region of the substrate, and a second plurality of flaps that extend upward from the annular upper portion to form a plurality of independently pressurizable outer chambers. The annular upper portion surrounds the circular lower portion and is vertically offset from the circular lower portion such that the lower surface is positioned above a plane defined by the circular lower portion, and the annular upper portion is coupled to an outermost flap of the first plurality of flaps.

Abstract: A method includes receiving historical time-series data and generating training data comprising a plurality of randomized data points associated with the historical time-series data. The historical time-series data was generated by one or more sensors during one or more processes. The method further includes training a logistic regression classifier based on the training data to generate a trained logistic regression classifier. The trained logistic regression classifier is associated with a logistic regression that indicates a location of a transition pattern from a first data point to a second data point. The transition pattern reflects about a reflection point located on the transition pattern. The trained logistic regression classifier is capable of indicating a probability that new time-series data generated during a new execution of the one or more processes matches the historical time-series data.

Abstract: Exemplary semiconductor processing chambers may include a chamber body having sidewalls and a base. The chambers may include a pumping liner seated atop the chamber body. The pumping liner may at least partially define an annular pumping plenum and at least one exhaust aperture that fluidly couples the pumping plenum with an interior of the chamber body. The chambers may include a purge ring seated below the pumping liner. The purge ring may define an annular channel that extends about a body of the purge ring. The purge ring may define a gas inlet that is fluidly coupled with the annular channel. The purge ring may define purge ports that are disposed at different radial positions about the purge ring, each of the purge ports being aligned and in fluid communication with the pumping plenum. The chambers may include a purge gas source coupled with the gas inlet.