Abstract: Optical inspection system detects defects of an object, such as an electronic device during manufacturing. The optical inspection system includes a first linear light source that irradiates a first light beam on a top surface of the object along a scan line across the width of the object. A second linear light source forms an angle with the first linear light source and irradiates a second light beam on a side surface of the object. A camera receives scattered light from the top surface and the side surface of the object and captures a subimage of the object along the scan line. An image processing system receives each subimage from the camera, stitches the subimages, and detects defects on the top surface and the side surface of the object.

Abstract: Systems and methods that provide reconfigurable shifter configurations supporting multiple instruction, multiple data (MIMD) are described. Shifters implemented according to embodiments support multiple data shifts with respect to an instance of data shifting, wherein multiple individual different data shifts are implemented at a time in parallel. Reconfigurable segmented scalable shifters of embodiments, in addition being reconfigurable for scalability in supporting data shifting with respect to various bit lengths of data, are configured to support data shifting of differing bit lengths in parallel. The data shifters of embodiments implement segmentation for facilitating data shifting with respect to differing bit lengths. Different data shift commands may be provided with respect to each such segment, thereby facilitating multiple data shifts in parallel with respect to various bit lengths of data.

Abstract: A wireless power transmitter that supplies power to a wireless power receiver. The wireless power transmitter includes a control unit, a resonator and an amplifier. The control unit generates an identification information of the wireless power transmitter. The resonator transmits power to the wireless power receiver. The amplifier drives the resonator and is controlled by the control unit such that the power transmitted by the resonator includes a first signal that carries the identification information of the wireless power transmitter. The wireless power transmitter further includes a wireless communication unit that sends a second signal having the identification information of the wireless power transmitter.

Abstract: A method for annotating a batch of original samples is provided. A first subset of original samples, selected from the batch and determined by minimizing an entropy-mean difference between the first subset and the batch, is used for human annotation to yield human-annotated samples. The human-annotated samples are used as training data to configure an annotation process for annotating an input sample to yield an annotated output sample, and a check process for verifying annotation accuracy of the annotated output sample. Remaining original samples in the hatch are processed by the annotation process to yield machine-annotated samples, whose accuracy is verified by the check process. In one embodiment, part of the original samples corresponding to erroneous machine-annotated samples are selected for human annotation. Resultant additional human-annotated samples are used to update the two processes. The remaining original samples not yet annotated are then processed by the two processes.

Abstract: A two-point modulation Phase-Locked Loop (PLL) has a dual-input Voltage-Controlled Oscillator (VCO). A digital data modulation signal is combined with a carrier and input to a feedback divider. The data modulation signal is also input to an offset Digital-to-Analog Converter (DAC) to generate an analog voltage to a second input of the VCO. The loop path through the VCO has a higher gain than the DAC path through the VCO, which has better linearity. A calibration unit divides the VCO output and counts pulses. The offset DAC has a data input and a gain input. During calibration, the data input of the DAC is set to minimum and then maximum values and VCO output pulses counted, and repeated for two values of the gain input to the DAC. From the four counts a K(DAC) calculator calculates the calibrated gain to apply to the gain input of the offset DAC.

Abstract: A segmented 3D multi-view image generator generates fewer multi-view view images for partitions having less salient features. Saliency values are calculated based on a depth map and image processing of the input image. The saliency values are compared to thresholds to map pixel locations to first, second, and third partitions. First, second, and third segmented images are created from the input image using a partition map. A multi-view generator uses the depth map and viewer eye locations to generates 28 view images from the first segmented image, 14 unique view images from the second segmented image that are replicated to 28 view images, and 7 unique view images from the third segmented image that are replicated to 28 view images. The view images for each segment are interlaced to generated interlaced segmented images that are then integrated together into a single 3D image that drives a 28-view autostereoscopic display.

Abstract: A method for setting-up a tunnel connection for transporting data packets over a high latency network connection in a communication network comprises the step of, at a module or node configured on a tunnel connection initiator side of the high latency network connection, using a non-TCP connection to encapsulate a set-up connection message for sending to a module or node configured on a core network (CN) side of the backhaul network to offset-up a data packet transport tunnel connection between the initiator side of the high latency network connection and core network (CN) side of the high latency network connection.

Abstract: A method for recognizing and extracting named entities in a natural language input text processing comprising: performing, by a compressed named entities recognition (NER)-model-based named entity recognizer, a first stage NER on the input text to generate a first stage determination of whether at least one named entity exists in the input text; if the first stage NER determines no named entity exists in the input text, performing, by a rule based named entity recognizer, a second stage NER on the input text to generate a second stage NER result; if the first stage NER determines at least one named entity exists in the input text, generating, by the compressed NER-model-based named entity recognizer, a first stage NER result; and integrating, by a NER result integrator, the first stage NER result and the second stage NER result to generate a final NER result.

Abstract: Described is a controller for a DC/DC converter of a type having N power stages, where N is a natural number greater or equal to 2. The controller comprises a decision maker module, a proportional-integral-derivative (PID) or proportional-integral (PI) control module and a transient compression control module. The decision maker module determines a first steady state mode of operation and a second transient mode of operation and is configured to switch control between said first steady state mode of operation to said second transient mode of operation when an operating parameter of one of the N power stages exhibits a predetermined operating condition relative to a predetermined operating limit and/or a predetermined, calculated or selected threshold. The PID or PI module regulates the operating parameter during said first steady state mode of operation.

Abstract: A low-core-loss transformer for high transfer ratio and high power density applications can have five pillars including four corner pillars and at least one center pillar between magnetic metal plates. The center pillar provides an additional flux path to reduce thermal and core losses and improve efficiency. Magnetic flux density may be further reduced by having multiple central pillars in an N-track configuration in several kinds of symmetrical arrangements. The low-core-loss transformer achieves a flexible voltage transfer ratio. The ratio can be either even or odd numbers. An odd ratio design is able to fulfill the requirement of future data centers to supply a 400-volt high-distribution power bus. The transformer windings can be traces on a Printed Circuit Board (PCB) that integrate electronic components for a compact and modular design.

Abstract: A receiver is energized by wireless power from a coil antenna. A matching network tunes the receiver to a resonant frequency and a bridge and capacitor generate an output voltage. The output voltage is divided and compared to a reference voltage. An asynchronous digital controller increases a digital count when the compare result is true, but decreases the digital count when the compare result is false. A current-steering Digital-to-Analog Converter (DAC) shunts a current from the output that is a function of the digital count. The asynchronous digital controller, comparator, and DAC do not use a system clock, so the digital feedback to the shunt current operates when the target output voltage is reached, preventing over-voltage when waiting for the system clock to begin pulsing. The digital count is compared to a digital threshold to recover transmitted Amplitude-Shifted-Keyed (ASK) data.

Abstract: Systems and methods which provide a compact spectrometer using static Fourier transform interferometer (SFTI) cube configurations, such as are suitable for use with respect to mobile and portable electronic devices, are described. A SFTI cube of embodiments comprises a monolithic dual mirrored wedge beam splitter structure wherein mirrored wedge surfaces provide two reflective mirrors that are slightly tilted away from the orthogonal directions so that the resultant beams of light cross over one another and form an interference pattern. SFTI cube implementations of embodiments facilitate highly compact spectrometer configurations having a wide wavelength range, high resolution, high throughput, and low cost.

Abstract: Systems and methods providing low-density parity-check (LDPC) decoder configurations capable of decoding multiple code blocks in parallel are described. Parallel LDPC decoders of embodiments can be reconfigured to simultaneously decode multiple codewords with reconfigurable size. In operation of embodiments of a parallel LDPC decoder, a plurality of active portions of the decoder logic are configured for parallel processing of a plurality of code blocks, wherein each active region processes a respective code block. The decoder logic active portions of embodiments are provided using a reconfigurable segmented scalable cyclic shifter supporting multiple instruction, multiple data (MIMD), wherein multiple individual different data shifts are implemented with respect to a plurality of code blocks in an instance of data shifting operation.

Abstract: A method for character recognition and semantic for natural language processing comprising extracting a sequence of feature vectors from a sequence of input character images by a convolutional neural network (CNN) feature extractor. The sequence of feature vectors comprises a plurality of feature vectors, each feature vector representing an approximate-match of its corresponding input character in the sequence of input character images. The method further comprises applying a sequential classifier sequentially as a sliding window of a size of a plurality consecutive feature vectors upon the sequence of feature vectors from a first feature vector in the sequence of feature vectors to the last feature vector in the sequence of feature vectors; and recognizing an output character for a targeted feature vector among the applied-upon consecutive feature vectors within the sliding window as it is sliding across the sequence of feature vectors.

Abstract: Systems and methods which provide for accurate decoding of a received channel signal when station identifier information is unknown. Embodiments accurately decode a physical downlink control channel (PDCCH), such as to obtain downlink control information (DCI), without knowing radio network temporary identifier (RNTI) information. An unknown station identifier information (USII) of embodiments uses redundancy reduction-based error checking (performing error checking between data decoded from a candidate control channel data block containing redundant data and a portion of that candidate control channel data block containing redundancy reduced data) for implementing decoding when station identifier information is unknown. Embodiments of a USII decoder may use a power detection technique for identifying candidate control channel data blocks used in redundancy reduction-based error checking operation.

Abstract: A power device package includes a substrate, a high side power device, a low side power device and a driver device. The substrate includes a top surface, a bottom surface and a plurality of vias that extend through the substrate. The high side and low side power devices are disposed on the top surface of the substrate and connected with each other. The driver device is disposed on the bottom surface of the substrate and electrically connected with the high side and low side power devices through the vias to drive the high side and low side power devices in response to a control signal. The distance between the driver device and the high side and low side power devices is determined by the thickness of the substrate such that that a parasitic inductance between the driver device and the high side power device or the low side power device is reduced.

Abstract: A synchronizer generates cross-products of In-phase (I) and Quadrature (Q) samples and stores the sign bits for the sine and cosine cross-products. The sign bits are compared to a local reference of a frame-start bit-sequence and the compare results accumulated as I and Q correlations for symbol and half-symbol sampling. Linear combinations of the accumulated I and Q correlations for the symbol and half-symbol sampling generate linear combination results for frequency bins that peak at a different implied Carrier Frequency Offset (CFO) settings. The maximum of the linear combination results is selected and the implied CFO setting for that frequency bin is applied to a demodulator to adjust the receiver's CFO setting and bit synchronization. Computational complexity is reduced since only the sign bit of each cross-product is retained for correlation with the frame-start bit-sequence. Linear combinations can support a wide CFO range.

Abstract: A shielded Schottky heterojunction power transistor is made from a Silicon-Carbide (SiC) wafer with SiC epitaxial layers including a N+ source and a Silicon N-epitaxial layer under the gate with higher channel mobility than SiC. The bulk of the wafer is a N+ SiC drain contacted by backside metal. A trench is formed between heterojunction transistors. Metal contacting the N+ source is extended into the trench to form a Schottky diode with the N-SiC substrate. P+ taps on the sides of the trench connect the metal to a P-SiC body diode under the heterojunction gate, and also prevent the Schottky metal from directly contacting the P body diode. Buried P pillars with P+ pillar caps are formed under the trench Schottky diode and under the heterojunction transistors. The P pillars provide shielding by balancing charge with the N substrate, acting as dielectrics to reduce the E-field above the pillars.

Abstract: Systems and methods providing synchronization of wireless device data based upon device synchronization prioritization determinations are described. Embodiments may make device synchronization prioritization determinations using device grouping identifiers with respect to a plurality of wireless devices and/or one or more device synchronization parameters for the wireless devices. Logic of a synchronization prioritization gateway of embodiments may implement a prioritization determination algorithm to determine a sequence of wireless devices for data synchronization for facilitating data synchronization with respect to a plurality of wireless devices in a timely and efficient manner. The logic of the synchronization prioritization gateway may implement a priority penalty attribute with respect to particular wireless devices to address aberrant behavior or other operation likely to impede efficient and/or timely data synchronization.

Abstract: A panoramic video stream is compressed. Sinusoidal projection is performed on spherical input images to generate pseudo-cylindrical projection images. A lower-left region and a lower-right region of the image are cut and moved to upper corners of the rectangular bounding box around the pseudo-cylindrical projection image. These upper corners are non-effective areas of default dark pixels with no image pixels. A bottom one-third of the rows of pixels from the image that contained the moved regions are deleted, compressing the image by 33%. Default dark pixels in interface regions between the moved regions and the pseudo-cylindrical projection image are linear interpolated to provide gradual changes in pixel values across the remaining formerly non-effective regions, preventing encoding artifacts caused by abrupt changes in pixel values. Functions may be implemented using lookup tables.