Abstract: A well-less Transient Voltage Suppressor (TVS) Silicon-Controlled Rectifier (SCR) has a P+ anode region that is not in an N-well. The P+ anode region 20 is surrounded by N+ isolation regions near the surface, and a deep N+ region underneath that is formed in a p-substrate. A N+ cathode region is formed in the p-substrate. The deep N+ region has a doping of 5×1018 to 5×1019/cm3, compared to a doping of 1×1016/cm3 for a typical N-well, or a doping of 1×1013 to 1×1015/cm3 for the p-substrate. The high doping in the deep N+ region causes a recombination current that can shunt half of the anode current. Since the deep N+ region is much shallower than an N-well, the sidewall capacitance is greatly reduced, allowing for higher speed applications.

Abstract: A wireless power transfer system with a class DE inverter for power transfer to a load. The wireless power transfer system includes a half-bridge circuit, a zero voltage switching (ZVS) tank, a shunt capacitor array, an evaluation circuit, and a controller. The half-bridge circuit has two transistors connected in series with each of the two transistors driven by a gate driving signal with a duty cycle. The ZVS tank and the shunt capacitor array are electrically connected with the half-bridge circuit. The ZVS tank includes two capacitors and an inductor. The shunt capacitor array has a capacitance that is tunable. The evaluation circuit calculates a power conversion efficiency of the system. The controller receives the power conversion efficiency from the evaluation circuit and generates control signals to adjust the duty cycle of the gate driving signal and to adjust the capacitance of the shunt capacitor array in order to maximize the power conversion efficiency of the system.

Abstract: The invention provides an apparatus for inspecting a light transmissible optical component. The apparatus comprises an image capturing module arranged on a first side of a support configured to hold a light transmissible optical component whilst it is being inspected. The apparatus includes an illumination device configured to shape light from a light source and to illuminate a selected portion of a surface of said light transmissible optical component with said shaped light to enable the image capturing module to capture any of a bright field image, a dark field image, or a combined bright field and dark field image of the light transmissible optical component being held by the support.

Abstract: A silicon carbide chip array containing a silicon carbide substrate; a silicon carbide layer on top of the silicon carbide substrate; a first metal contact connected to the silicon carbide substrate; and two second metal contacts connected to the first portion and the second portion respectively. The silicon carbide layer is thinner and having lower doping than the silicon carbide layer. The silicon carbide layer includes a first portion and a second portion which are separate from each other. Each one of the second metal contacts forms a semiconductor device with the first metal contact. At least one of the first and second portions contains a side face which is inclined with respect to the silicon carbide substrate. Such a configuration enhances the breakdown voltage and reduces leakage current of the resultant silicon carbide diode array.

Abstract: A method of generating an electronic 3D walkthrough environment of a targeted environment, comprising: capturing a panorama at a first location point in the targeted environment; measuring an initial orientation of the camera whenever a panorama is captured; moving through the targeted environment and at each location point, capturing a live image of surrounding, and measuring an orientation of the camera; determining whether a new panorama is required to be captured at the current location point at where the camera is with the current orientation of the camera, comprising: identifying a sub-image in the panorama last captured that matches the live image captured; and if the sub-image cannot be identified, then a new panorama is required; and generating the electronic 3D walkthrough environment by connecting the panoramas captured.

Abstract: Example embodiment is a power converter that adopt a 3D structure to increase the power density and improve thermal performance. The power converter includes a bottom substrate and at least one side substrate. Both the bottom substrate and the side substrate are rigid. Each side substrate is connected with the bottom substrate by a flexible substrate and forms an angle with the bottom substrate. The bottom substrate is further electrically connected with a plurality of surface mounting devices which are rigid. The flexible substrate provides electrical connection between the bottom substrate and the side substrate.

Abstract: Provided is a method of modifying a data path between a user equipment (UE) and a core network node (CNN) in a wireless communication network. The method comprises the steps of: at a network node handling both signalling messages and user data for an existing data path between said UE and said CNN, obtaining data uniquely associated with a data path resource for said UE and/or uniquely identifying said UE and mapping said data to said existing data path; and modifying said existing data path based on said mapping. The network node handling both signal messaging and user data for an existing data path may comprise a gateway (GW) connecting a source base station (SBS) and a target base station (TBS) to a Mobility Management Entity (MME) of the core network, said GW being configured to handle both user plane data and control plane data for a plurality of UEs.

Abstract: A method and a device for image inpainting on arbitrary surfaces in three-dimensional space are described for inpainting a region of a three-dimensional image utilizing a partial differential equation. The method includes obtaining a three-dimensional image on a surface S in three-dimensional space, and each point of the image includes an image point value and a position vector. The method includes locating an inpainting region D and generating an inpainting mask. The method further includes calculating image point values for points inside the inpainting region D and creating a second three-dimensional image to obtain an inpainted image. The present disclosure solves technical problems that previous methods do not work well on three-dimensional images on arbitrary surfaces and improves image inpainting technology.

Abstract: A fully convolutional network (FCN) implemented on a specialized processor optimized for convolution computation can achieve a speed-up in cell classification. Without re-optimizing the specialized processor, a further speed-up is achieved by compacting a testing image of cells, and processing the compacted testing image with the FCN. The testing image is first segmented into a background and regions of interest (ROIs). The ROIs are packed closer together by rearranging the ROIs without resizing them under a constraint that any two adjacent rearranged ROIs are separated by a distance in pixel not less than a minimum distance determined according to stride values of FCN convolutional layers. Geometrical operations in ROI rearrangement include relocating the ROIs and, optionally, rotating the ROIs. The rearranged ROIs are enclosed by a boundary, typically a rectangular boundary, to form the compacted testing image having an area smaller than that of the testing image.

Abstract: A system for detecting a gazing point of a user in a three-dimensional (3D) space based on a virtual screen is provided. The system includes at least a processor and a wearable device, the wearable device further comprising an external camera arranged for capturing images of the user's field of view, and two internal cameras arranged for capturing binocular images of the user's left and right eyes. The processor is designed to determine the gazing point of the user based on a virtual screen. The coordinates of the pupil center as determined according to the images from the internal cameras are mapped to the images from the external camera based on a left and a right mapping relationships, which further mapped to the virtual screen as an intermediate screen for calculating the 3D coordinates of the gazing point.

Abstract: The invention relates to a toy for discharging a liquid. The toy comprises a discharging chamber adapted to receive a liquid from a liquid storage tank; an outlet arranged at the discharging chamber adapted to discharge at least some of the liquid received in the discharging chamber, the outlet being controllable by a covering mechanism movable between a closed position and an open position to thereby close and open the outlet, respectively; a movable member operably connected with the covering mechanism; wherein, in response to a triggering action of the toy, the movable member is movable from a first position to a second position thereby actuating the covering mechanism to move from the closed position to the open position, and at the same time, triggering discharge of the at least some of the liquid from the discharging chamber via the outlet.

Abstract: Methods and systems which provide object edge image representation generation using block based edgel techniques implementing post edgel detection processing to eliminate false edges are described. Embodiments subdivide image data (e.g., image point clouds) to facilitate separate edgel detection processing of a plurality of sub-blocks of the image data. A false edge elimination algorithm of embodiments is applied in recombining the object edge image representation sub-blocks resulting from the sub-block edgel detection processing to eliminate false edge artifacts associated with use of block based edgel detection.

Abstract: An Electro-Static-Discharge (ESD) protection device has a Fin Field-Effect Transistor (FinFET) with a silicon fin with a step separating a top fin and a bottom fin. The gate wraps around the top fin but not the bottom fin. Normal gate-controlled channel conduction occurs in the top fin between a source and a drain in the top fin. Underneath the conducting channel is a buried conducting region in the bottom fin that conducts after a breakdown voltage is reached during ESD. A ledge, abrupt slope change in the sidewalls of the fin, or a doping increase occurs at the step between the top fin and bottom fin. The bottom fin is 2-3 times wider than the top fin, causing the resistance of the buried conducting region to be 2-3 times less than the resistance of the conducting channel, steering breakdown current away from the channel, reducing failures during breakdown.

Abstract: An Electro-Static-Discharge (ESD) input-protection device has an NPNP structure of a N+ cathode formed in a FINFET fin or highly-doped region over a floating P-well, and a P+ fin or highly-doped region anode formed over a floating N-well that touches the floating P-well. The floating P-well is surrounded by an isolating N-well and has a deep N-well underneath to completely isolate the floating P-well from the p-type substrate. No well taps are formed in the floating wells or in the isolating N-wells. The floating P-well and the floating N-well are thus truly floating at all times. Since the wells are floating, the NPNP structure appears as three junction diodes in series, which has a lower capacitance than a single diode that the NPNP structure would appear as when one of the wells was shorted or biased. During an ESD event the NPNP structure behaves as a single diode.

Abstract: An apparatus and method for performing real object detection and control using a Virtual Reality Head Mounted Display System, and more particularly, when the real object detection and control are detecting hand presence and control in free space, in a virtual reality environment, the control being, for example, gestures or movement, in the free space.

Abstract: For an augmented reality (AR) content creation system having a marker database, when a user requests this system to use a first sub-image of an image to update the marker database, this system computes a suitability score of the first sub-image for rating feature richness of the first sub-image and uniqueness thereof against existing markers in the marker database. When the suitability score is less than a threshold value, a second sub-image of the image having a suitability score not less than the threshold value and completely containing the first sub-image is searched. Then the second sub-image, the suitability score thereof and the suitability score of the first sub-image are substantially-immediately presented to the user for real-time suggesting the user to use the second sub-image instead of the first sub-image as a new marker in updating the marker database to increase feature richness or uniqueness of the new marker.

Abstract: Provided is a method and an apparatus for signaling allocation of resources in a joint transmission communication system. The method includes determining one of a plurality of resource allocation schemes to be implemented by two or more of a plurality of transmission points (TPs) comprising a set of coordinated TPs for enabling said two or more of said TPs to transmit data to a scheduled user equipment (UE). The method may comprise determining a bit length of a resource allocation field for a resource allocation signal message based on a number N of resource blocks groups (RBGs) related to a bandwidth of the joint transmission communication system and a number M of TPs comprising said set of coordinated TPs and further include formatting the resource allocation signal message to provide the resource allocation field based on said determined bit length. The resource allocation signal message is transmitted from only one of said set of coordinated TPs to said scheduled UE.

Abstract: A method that prevents overload to input source and reduces parasitic inductance in an inverter circuit with dead-time control. A sensing capacitor senses temperatures of transistors in the inverter circuit. A delay generator changes delay times in response to receiving the temperatures of the transistors from the sensing capacitor. A dead time generation unit changes the dead times for the transistors in response to changes in the delay times.

Abstract: A programmable-threshold power supply selector has two power-supply inputs VDD1 and VDD2. The higher of these two voltages is pre-selected as a common supply that powers all transistors and circuitry in the programmable-threshold power supply selector, including substrates under transistors. An open-loop decision circuit is very stable since it uses no feedback. A tunable voltage divider divides VDD1 by a programmable divisor. The divided VDD1 is compared to a reference voltage to generate switch-control signals. The switch-control signals drive the gates of p-channel switch transistors that connect either VDD1 or VDD2 to an output supply voltage. The different programmable divisor values effectively cause VDD1 to be compared to a programmable threshold voltage VTH. The switch transistors switch the output supply voltage to VDD2 only when VDD1 falls below VTH. The output supply voltage remains at VDD1 even when VDD1 falls below VDD2, eliminating unnecessary power switching.

Abstract: A Quadrature-In, Quadrature-Out (QIQO) clock divider divides by an odd divisor, such as three. An IQ input clock has in-phase and quadrature differential signals. Four stages of dynamic logic are arranged into a loop, with each stage output being one of four IQ output signals that have 90-degree phase separations. Each stage output drives the gates of a p-channel charging transistor and an n-channel discharging transistor of a next stage. Two p-channel charging logic transistors are in series between the next stage output and the p-channel charging transistor, and two n-channel evaluation transistors are in series between the next stage output and the n-channel discharging transistor. Different pairs of the four IQ input clock signals are applied to their gates. When the prior stage output is low, the stage output is charged. When the prior stage output is high, the stage output discharge timing is determined by the IQ signals.