Abstract: A system, apparatus and method for enabling a FIFO-like (first-in-first-out) communication between a plurality of executing processes that are distributed throughout a computing system. Embodiments exploit locality in the hierarchy of the cache memory and communication busses within the computing system to enable the passing of messages or streams of bytes with a low latency and high throughput. In addition, this allows for participating components to be very simple, or very sophisticated, but still benefit from the improved communications patterns.

Abstract: A graphics processing system maintains a fragment tracking record that stores metadata relating to one or more previously received primitives. The metadata can indicate that the one or more previously received primitives are suitably covered by a subsequently received primitive such that one or more fragment processing operations need not be performed in respect of those one or more previously received primitives. The metadata stored for the one or more previously received primitives can then later be queried by one or more later stages of the graphics processing system to determine whether one or more fragments for the one or more previously received primitives can be at least partially discarded or “killed”.

Abstract: Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with an array of bitcells accessible via wordlines arranged in rows and bitlines arranged in columns. The integrated circuit may include source lines coupled to the bitcells. The integrated circuit may include source line drivers coupled between the wordlines and the source lines, and the source line drivers may allow the source lines to be used as switched source lines.

Abstract: A graphics processing system includes a cache system for transferring texture data stored in memory to a graphics processing unit for use by the graphics processing unit when generating a render output. The cache system includes a first cache operable to receive texture data from the memory system, and a second cache operable to receive texture data from the first cache and to provide texture data to the graphics processing unit for use when generating a render output, and a data processing unit intermediate the first cache and the second cache and operable to process data stored in the first cache and to store the processed data in the second cache.

Abstract: The present techniques generally relate to a method of monitoring for a fault event in a lockstep processing system having a plurality of cores configured to operate in lockstep, the method having: power gating, for a period of time, a subset of cores of the plurality of cores from a first power source and providing power to the subset of cores from a second power source for the period of time; processing, at each of the cores of the plurality of cores, one or more instructions; providing an output from each core of the plurality of cores to error detection circuitry to monitor for the fault event, the output from each core based on or in response to processing the one or more instructions during the period of time.

Abstract: To determine whether a first n-bit binary data value and a second n-bit binary data value in a data processing system, such as texel position coordinates in a graphics processing system, are the same or differ from each other by exactly one, it is determined whether the first and second data values excluding the least significant bits of the data values are the same as each other, and the least significant bits of the data values are compared. A mask value that is generated for each data value using an XOR operation and a thermometer scanning operation is used to generate an output value for the two data values, based on whether the mask values for a bit position for the first and second data values are both set or not, and a comparison of the bit values of the first and second data values for that bit position.

Abstract: A data processing system includes multiple powered domains which communicate using a bridge 10. The bridge 10 includes first bridge circuitry 14 within a first power domain and second bridge circuitry 16 within a second power domain. The first bridge circuitry 14 and the second bridge circuitry 16 exchange intra-bridge power control signals which serve to control management of the communication channel through the bridge 10 to adopt a communication open state or a communication quiesced state independent of whether either side of the bridge is in a power-active state or a power-inactive state.

Abstract: A data processing system has an execution pipeline with programmable execution stages which execute instructions to perform data processing operations provided by a host processor and in which execution threads are grouped together into groups in which the threads are executed in lockstep. The system also includes a compiler that compiles programs to generate instructions for the execution stages. The compiler is configured to, for an operation that comprises a memory transaction: issue to the execution stage instructions for executing the operation for the thread group to: perform the operation for the thread group as a whole; and provide the result of the operation to all the active threads of the group. At least one execution stage is configured to, in response to the instructions: perform the operation for the thread group as a whole; and provide the result of the operation to all the active threads of the group.

Abstract: A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

Abstract: Subject matter herein disclosed relates to an improved CEM switching device and methods for its manufacture. In this device, a conductive substrate and/or conductive overlay comprises a primary layer of a conductive material and a secondary layer of a conductive material. The primary layer contacting the CEM layer is substantially inert to the CEM layer and/or acts as an oxygen barrier for the secondary layer at temperatures used for the manufacture of the device.

Abstract: When a shader program is to be executed by a graphics processor, the graphics processor is caused to execute at least two variants of the shader program and the operation of the graphics processor when executing execution threads for the different variants of the shader program is monitored. A variant of the shader program to be executed by subsequent execution threads that are to execute the shader program is then selected based on the monitoring of the operation of the shading stage when executing the execution threads for the different variants of the shader program.

Abstract: Apparatuses and methods of data processing are disclosed. An apparatus comprises two data processing clusters each having multiple data processing lanes to perform single instruction multiple data (SIMD) processing. Decoded instructions are issued to at least one of the two data processing clusters. A decoded SIMD instruction specifying a vector length which is more than the width of the data processing lanes of the first data processing cluster has a first part issued to the first data processing cluster for execution. An issuance target for a second remaining part of the decoded SIMD instruction is selected in dependence on a dynamic performance condition. When the dynamic performance condition has a first state the issuance target is the first data processing cluster and when the dynamic performance condition has a second state the issuance target is the second data processing cluster.

Abstract: An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.

Abstract: An apparatus comprises a cache memory to store data as a plurality of cache lines each having a data size and an associated physical address in a memory, access circuitry to access the data stored in the cache memory, detection circuitry to detect, for at least a set of sub-units of the cache lines stored in the cache memory, whether a number of accesses by the access circuitry to a given sub-unit exceeds a predetermined threshold, in which each sub-unit has a data size that is smaller than the data size of a cache line, prediction circuitry to generate a prediction, for a given region of a plurality of regions of physical address space, of whether data stored in that region comprises streaming data in which each of one or more portions of the given cache line is predicted to be subject to a maximum of one read operation or multiple access data in which each of the one or more portions of the given cache line is predicted to be subject to more than one read operation, the prediction circuitry being configured

Abstract: A cache is disclosed in which a dedicated cache portion comprising one or more extra lines dedicated for data of a particular data type is provided alongside a shared cache portion. So long as there is a cache line available in the shared cache portion, data can be written into the shared cache portion. However, when the shared cache portion is fully locked such that no new data can be written into the shared cache portion, data can instead be written to its respective dedicated cache portion, effectively bypassing the fully locked shared cache portion.

Abstract: A sequence of instructions is included in a graphics processing shader program for controlling the way in which blending is implemented. The sequence of instructions includes a blend instruction which determines whether blending for a processing item is to be performed by fixed-function blending hardware or by executing a blend shader routine. If blend shading is to be performed, a sequence of instructions for setting up and performing blend shading is executed. If fixed-function blending is to be performed, an execution thread initiates fixed-function blending in response to the blend instruction, and skips over the sequence of instructions for setting up and performing blend shading.

Abstract: A data processing system including a data processor which is operable to execute programs to perform data processing operations and in which execution threads executing a program to perform data processing operations may be grouped together into thread groups. The data processor comprises a cross-lane permutation circuit which is operable to perform processing for cross-lane instructions which require data to be permuted (copied or moved) between the threads of a thread group. The cross-lane permutation circuit has plural data lanes between which data may be permuted (moved or copied). The number data lanes is fewer than the number of threads in a thread group.

Abstract: A data processing system (2) supports non-speculative execution of vector load instructions that perform at least one contingent load of a data value. Fault detection circuitry (26) serves to detect whether a contingent load is fault-generating contingent load or a fault-free contingent load. Contingent load suppression circuitry (28) detects and suppresses a fault-free contingent load that matches a predetermined criteria that may result in an undesired change of architectural state (undesired side-effect). Examples of such predetermined criteria are that the contingent load is to a non-memory device or that the contingent load will trigger a diagnostic response such as entry of a halting debug halting mode or triggering of a debug exception.

Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry.