Abstract: The present disclosure relates to a data processing apparatus for a processing resource to perform a transform operation on an input tensor for the processing resource, said input tensor being formed of a plurality of blocks, each block being a portion of said input tensor capable of being operated on independently of each other, said data processing apparatus comprising: communication circuitry to communicate with a control module and a shared storage of said processing resource; processing circuitry to perform said transform operation, said processing circuitry comprising sub-block processing circuitry and transformation circuitry; and a local storage to store transform operation output from said processing circuitry; wherein said communication circuitry is configured to: receive one or more transform parameters; read a first input sub-block from said shared storage, said first input sub-block being a portion of a first block of said input tensor corresponding to a processing unit of said processing circuit

Abstract: A data processing apparatus includes first vector registers and second vector registers, both dynamically spatially and dynamically temporally dividable. Decode circuitry receives one or more matrix multiplication instructions that indicate a set of first elements in the first vector registers and a set of second elements in the second vector registers, and in response to receiving the matrix multiplication instructions they generate a matrix multiplication operation. The matrix multiplication operation causes one or more execution units to perform a matrix multiplication of the set of first elements by the set of second elements and an average bit width of the first elements is different to an average bit width of the second elements.

Abstract: An apparatus comprises combined divide/square root processing circuitry to perform, in response to a divide instruction, a given radix-64 iteration of a radix-64 divide operation, and in response to a square root instruction, a given radix-64 iteration of a radix-64 square root operation; in which: the combined divide/square root processing circuitry comprises shared circuitry to generate at least one output value for the given radix-64 iteration on a same data path used for both the radix-64 divide operation and the radix-64 square root operation.

Abstract: A data processing method and processor instructions are provided that leverage scatter operations to efficiently merge vector and matrix indices, as compared to standard matrix and vector operations, as well as merge other arithmetic results, lists of numbers, etc.

Abstract: An apparatus for data processing comprises a data processing pipeline to perform data processing operations, and extension processing circuitry to perform a delegated task asynchronously to the data processing pipeline in response to the decoding circuitry decoding an extension start instruction. The apparatus also comprises hazard detection circuitry to detect data hazards associated with processing operations performed by the data processing pipeline. When the data processing pipeline is in an extension hazard checking state, the presence of a hazard condition can be determined in dependence on whether a given memory access, to be performed in response a given memory access instruction following the extension start instruction in program order, is for accessing an address which falls within a group of addresses anticipated to be accessed by the extension processing circuitry during performance of the delegated task.

Abstract: A memory device includes a bitcell array having at least a first plurality of first adjacent bitcell banks and a second plurality of second adjacent bitcell banks. One or more bitcell array input lines are coupled to the bitcell array at a first physical location between the first adjacent bitcell banks. One or more bitcell array output lines are coupled to the bitcell array at a second physical location between the second adjacent bitcell banks. The one or more bitcell array input lines are further coupled from the first plurality of adjacent bitcell banks to the second plurality of bitcell banks at a physical location between the second plurality of adjacent bitcell banks. The one or more bitcell array output lines are further coupled from the second plurality of bitcell banks to the first plurality of bitcell banks at a physical location between the first plurality of bitcell banks.

Abstract: A method and a system for dynamically deriving and verifying a measure of a computing environment is presented. The proposed method and system are used to reliably verify measurements of the computing environment. The method includes receiving a dataset recorded by an untrusted source describing elements used to create a computing system operating in a computing environment, receiving attestation evidence generated by a trusted source including an initial measurement value describing the elements of the computing system, deriving a measurement value based on the received dataset, and performing a verification process on a measurement of the computing environment. The verification process is performed by comparing the derived measurement value with the measurement value of the attestation evidence. In response to the comparison of the derived measurement value with the measure value of the attestation evidence being equal, trustworthiness of the computing environment is determined.

Abstract: A graphics processor that is operable to execute a processing pipeline to generate an output. The graphics processor includes one or more processing circuits that can be configured (and re-configured) to execute a plurality of ‘generic’ pipeline stages defining at least a part of the processing pipeline. The ‘generic’ pipeline stages can thus be programmed appropriately to execute the perform the desired pipeline processing operations. A pipeline stage can issue shading requests via a generic shading interface.

Abstract: Various implementations described herein are directed to a method that tests and repairs memory fabricated on a wafer or a package. The method may generate and store a reuse table based on memory repair results. The method may manufacture the memory after repairing the memory. The method may access and reuse data stored in the reuse table to repair the memory after manufacturing the memory.

Abstract: The present disclosure relates to a method of operating a graphics processor to process a frame formed of a plurality of regions, the graphics processor comprising at least one execution unit with an associated storage element, the at least one execution unit is operable to process the plurality of regions according to a shading rate for each region to generate a processing output to the associated storage element, the method comprising: obtaining the shading rate for one or more of the plurality of regions; determining a respective processing output size for each of the one or more regions based on the shading rate for the one or more regions; forming the one or more regions into at least one variable processing unit based on the respective processing output size for each of the one or more regions and a capacity of the associated storage element; and assigning the at least one variable processing unit as a processing task to the at least one execution unit.

Abstract: A data processing apparatus includes configuration circuitry that receives, from software, a set of test information and configures each of a first storage circuit and a second storage circuit to perform a consistency test based on the test information. Check circuitry performs the consistency test between data stored in the first storage circuit and the second storage circuit and updates result storage circuitry with a result of the consistency test. The result storage circuitry is accessible to the software.

Abstract: The present techniques relate to voltage droop detection and there is disclosed circuitry for detecting a voltage droop event, the circuitry configured to: receive a clock signal from a clock distribution network; obtain, from a storage, a first predetermined value, a second predetermined value and a predetermined threshold count; obtain one or more measurement values associated with a system voltage; when a first measurement value of the one or more measurement values reaches the first predetermined value, initiate a count of clock cycles until a subsequent measurement value of the one or more measurement values reaches the second predetermined value, the second predetermined value being different from the first predetermined value; and when the count of clock cycles is lower than the predetermined threshold count, cause a control entity to take mitigation action.

Abstract: Data processing apparatus comprises a processing module to initiate data handling transactions, for transmission to a data handling module by a transaction interface, in response to successive processing instructions; a verification module connectable to the transaction interface and configured to detect test data, representing an ordered series of communications via the transaction interface generated in response to a test series of processing instructions; in which the verification module is configured to compare two or more instances of the test data generated in response to the same test series of processing instructions and to detect whether the two or more instances of the test data are identical.

Abstract: A producer-consumer relationship is stored. The producer-consumer relationship defines an association between a producer instruction and at least one consumer instruction, wherein a consumer value of the at least one consumer instruction is generated in dependence on producer data resulting from the producer instruction. A first producer-consumer pair and a second producer-consumer pair are selected from a plurality of observed instructions and a linear relationship between consumer values and producer data values is determined based on: respective consumer values of the first producer-consumer pair and the second producer-consumer pair and respective producer data values of the first producer-consumer pair and the second producer-consumer pair.

Abstract: An apparatus for handling exceptions, including a processing circuitry operable in at least one security domain to execute program code that includes a plurality of exception handling routines executed in response to corresponding exceptions, and a plurality of registers for storing data for access by the processing circuitry when executing the program code. The exception control circuitry is arranged in response to occurrence of a given exception from background processing to trigger a state saving operation to save data from the plurality of registers before triggering the processing circuitry to execute a given exception handling routine. Configuration storage provides configuration information used to categorise exception handling routines.

Abstract: A graphics processing system that comprises a graphics processor operable to perform ray tracing is disclosed. Instructions of set of ray tracing shader programs that define different elements of a ray tracing pipeline are combined to generate a combined ray tracing shader program, and the combined ray tracing shader program is provided for execution by a graphics processor.

Abstract: An apparatus (10) and a method are provided, wherein the apparatus comprises interrupt detection circuitry (40) which detects interrupts raised by at least one interrupt source (14), and interrupt tracking circuitry (44) which manages one or more hard-ware-managed linked list data structures to track pending interrupts detected by the interrupt detection circuitry. A computer program comprising computer-readable code for fabrication of the apparatus, and a computer-readable storage medium are also provided.

Abstract: An interconnect circuit comprises an unblock-request-receiving interconnect circuit node configured to receive a given write push request specifying write target data and write target address information identifying one or more addressed locations to which the write target data is to be written, and to enforce a requirement that a conflicting read request, which requests a read to one of the one or more addressed locations identified by the write target address information specified by the given write push request, is blocked from completing until an unblocking condition is satisfied for the given write push request, where for at least one type of write push request, satisfaction of the unblocking condition is dependent on an unblock request for the given write push request being received by the unblock-request-receiving interconnect circuit node; and an unblock-request-transmitting interconnect circuit node configured to transmit the given write push request to the unblock-request-receiving interconnect circ

Abstract: When sampling a 3D texture using anisotropic filtering, an anisotropy direction along which to take samples in the texture is determined by determining reduced precision representations of the texture coordinate derivative vectors and using the reduced precision texture coordinate derivative vectors to determine a pair of vectors representing the directions of x and y axes for a 2D coordinate system on the plane in the 3D texture defined by the texture coordinate derivative vectors. The x and y axis vectors are used together with the texture coordinate derivative vectors to determine both a X-axis component and a Y-axis component for projected representations of the texture coordinate derivative vectors in the 2D coordinate system on the plane in the 3D texture defined by the texture coordinate derivative vectors. The projected representations of the texture coordinate derivative vectors are then used to determine the anisotropy direction.

Abstract: A data processing apparatus for compiling computation graphs is disclosed. The apparatus includes graph partitioning circuitry that receives a computation graph, which comprises a plurality of nodes representing operators and edges representing their relationships, and divides the graph into a plurality of partitions. The apparatus also contains graph compilation circuitry and storage for compilation outputs. The graph compilation circuitry compiles a first partition to generate a first compilation output, which is then output to a first target portion of storage assigned to that first partition.