Abstract: Performance monitoring circuitry (40) has event counters (42) each to maintain a respective event count value based on monitoring of events during processing of the software by the processing circuitry. Control circuitry (44) configures the event counters based on counter configuration information. For at least a subset of the event counters, a given event counter (42) in the subset supports a chained-counter operation comprising incrementing a given event count value by an increment value determined based on a logical combination of a first event status indication indicative of status of a first event type assigned by the counter configuration information to be monitored by the given event counter and a second event status indication indicative of status of a second event type assigned by the counter configuration information to be monitored by a further event counter.

Abstract: A system and computer-implemented method to train and use a neural network is disclosed. For each group of elements of a feature map in a layer in the neural network, a record is accessed to determine if at least one element of the group is active. When at least one element of the group is active, a gradient is determined for each active element of the group, copied to a 5 group element position indicated by the entry for the group in record, and the group is sent to a dot product unit to update weights in the layer based on the group. When no element of the group is active, the dot product unit is signaled to prevent update of weights based on the group. The record is set during the forward path of the feature map through the network.

Abstract: A method of operating a network-reachable initiator computing entity, comprising: determining a requirement, at the initiator computing entity, for offloading data processing; initiating a message, to be sent on a network to a destination, requesting a response from network-reachable recipient computing entities along the network, from the network-reachable initiator computing entity to the destination, indicating a capacity to perform offloaded data processing; and receiving a response from a first network-reachable recipient computing entity indicating a capacity to perform offloaded data processing.

Abstract: A method of compressing a set of weight values is provided in which an uncompressed set of weight values is obtained, which uncompressed set of weight values includes a plurality of weight values associated with a neural network. A frequently occurring value is identified among the plurality of weight values within the set of weight values and each occurrence of the frequently occurring weight value is replaced within the set of weight values with an index value. The frequently occurring weight value and the index value are associated with the set of weight values. The index value is selected to be less storage intensive than the frequently occurring weight value that it replaces.

Abstract: A circuit and method for dynamic register allocation for a graphics processing unit is provided. The circuit includes circuitry to receive a binary vector having a length of M bits, the binary vector indicating one or more available blocks of memory in a register file memory; to perform a parallel prefix scanning method to identify positions of bits in-order within the binary vector to search for the one or more available blocks of memory in the register file memory to generate an allocation state for a warp, and to decode the allocation state into entries for a lookup table used to generate memory addresses of available blocks of register file memory. The parallel prefix multilayer scanning method includes scanning the binary vector for high bits in-order. The high bits indicating the one or more available blocks of memory in a register file memory.

Abstract: A first image frame in a first resolution format comprising image signal intensity values mapped to first pixel locations has sampling points offset from the centers of first pixel locations according to associated jitter vectors. The image signal intensity values are mapped to second pixel locations in a second image frame in a second resolution format based at least in part on the jitter vectors, the second resolution format being higher resolution than the first resolution format. The mapped image signal intensity values are combined with image signal intensity values of an accumulated history image buffer according to coefficients predicted by a neural network such as based on magnitudes of the jitter vectors. Interpolated pixel image intensities are added to the accumulated history buffer for empty or null pixel locations in the second image frame in the second image format. Upsampling artifacts such as checkerboarding and aliasing are reduced.

Abstract: A method for detecting defective pixel values determines an isotropic dispersion difference value by determining a ratio or difference between a pixel error and an isotropic dispersion, where the isotropic dispersion is a measure of how much pixel values in a set of neighbouring pixel values uniformly distributed around the pixel under consideration vary. The method compares the isotropic dispersion difference value to an isotropic threshold. A directional dispersion difference value is found by determining a ratio or difference between a pixel error and a directional dispersion, wherein the directional dispersion is a weighted measure of how much pixel values in a set of neighbouring pixel values around the pixel under consideration in a given direction vary. The directional dispersion difference value is compared to a directional threshold and it is determined that the pixel under consideration is defective based on at least one of the comparison results.

Abstract: Subject matter disclosed herein may relate to wireless energy harvesting and may relate more particularly to power-dependent tuning at energy-harvesting devices.

Abstract: A data processing apparatus includes mode circuitry for indicating a first format of a first floating-point parameter and separately indicating a second format of a second floating-point parameter. Floating-point circuitry performs a two-parameter floating-point operation using the first floating-point parameter in the first format and the second floating-point parameter in the second format. At least one of the first format and the second format is dynamically changeable at runtime.

Abstract: Various implementations described herein are related to a device having multi-page memory with a first core array and bitcells accessible via first wordlines and a second core array with bitcells accessible via second wordlines. The device may have wordline drivers coupled to the bitcells in the first core array via the first wordlines and to the bitcells in the second core array via the second wordlines. The device may have buried metal lines formed within a substrate, and the buried metal lines may be used to couple the wordline drivers to the first wordlines.

Abstract: A method and system for processing image data having a first bit depth using at least one trained neural network configured to operate on data having a second bit depth, where the second bit depth is smaller than the first bit depth by generating a plurality of image data portions by splitting the image data. Each of the plurality of image data portions is encoded to produce a plurality of encoded image data portions having the second bit depth. The plurality of image data portions are then processed by at least one trained neural network, before being decoded and combined to produce composite image data. The composite image data is then output.

Abstract: Apparatuses, methods and programs are disclosed relating to the predication of multiple vectors in vector processing. An encoding of predicate information is disclosed which comprises an element size and an element count, wherein the predicate information comprises a multiplicity of consecutive identical predication indicators given by the element count, each predication indicator corresponding to the element size.

Abstract: A method of processing color filter array, CFA, image data comprising receiving CFA image data comprising a plurality of pixel values in a frame of image data representable as a main two-dimensional row-columnar pattern, each pixel value corresponding to a color filter in a CFA. Different pixel values of the plurality of pixel values are associated with respective different filter colors including first pixel values associated with a first filter color and second pixel values associated with a second filter color. The first pixel values are arranged in at least a two-dimensional checkerboard sub-pattern in the main two-dimensional row-columnar pattern. The method involves performing a diagonally-aligned processing operation on the first pixel values, wherein the processing operation operates on the first pixel values in accordance with a reprojected array, the reprojected array corresponding to a reprojection of the two-dimensional checkerboard sub-pattern into a row-columnar array.

Abstract: A processor comprising: a handling unit; a plurality of components each configured to execute a function. The handling unit can receive a task comprising operations on data in a coordinate space having N dimensions, receive a data structure describing execution of the task and comprising a partially ordered set of data items each associated with instructions usable by the plurality of components when executing the task, each data item is associated with a component among the plurality of components, each data item indicates dimensions of the coordinates space for which changes of coordinate causes the function of the associated component to execute, and dimensions of the coordinate space for which changes of coordinate causes the function of the associated component to store data ready to be used by another component. The handling unit iterates over the coordinate space and executes the task using the partially ordered set of data items.

Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives for a tile are processed to determine visibility information, the visibility information being usable to determine whether fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output in a hierarchical manner.

Abstract: Access control circuitry (15), responsive to a memory access request, compares a tag value determined based on a tag portion (40) of an address pointer (42) with an allocation tag (32) associated with the memory location identified by a memory address determined from the address pointer. In response to the comparison indicating a given result, a tag error response is performed. Processing circuitry (4), executing a tag protecting instruction, detects whether an operation involves an attempt to set a bit in an identified portion (74) of an output value to a value other than that in a corresponding bit in an input operand. The processing circuitry sets, when it detects said attempt, a given portion of the output value to an error-indicating value. The identified portion is a portion of the output value which would be used as the tag portion if the output operand was used as the address pointer for a memory access instruction.

Abstract: An apparatus comprises instruction decoding circuitry configured to decode instructions; and processing circuitry configured to perform data processing in response to the instructions decoded by the instruction decoding circuitry. Cache control circuitry is configured to set, in response to the instruction decoding circuitry decoding a mark-live instruction specifying mark-live target address information, discard-eligibility metadata associated with one or more target cache lines selected based on the mark-live target address information, to identify the one or more target cache lines as being eligible for being treated as a discardable cache line which is allowed to be discarded without data writeback even if the discardable cache line is dirty. In response to a mark-dead event associated with a given cache line, the cache control circuitry determines depending on the discard-eligibility metadata for the given cache line whether the given cache line is eligible for becoming a discardable cache line.

Abstract: Interconnect circuitry comprises: receiving interface circuitry configured to receive, from a metadata-transmitting caching agent, discard control metadata for a given cache line previously held in a private cache of the data-transmitting caching agent; and transmitting interface circuitry configured to transmit the discard control metadata for the given cache line to a metadata-receiving caching agent for caching in a private cache of the metadata-receiving caching agent. The discard control metadata indicating whether the given cache line is, or is eligible for becoming, a discardable cache line allowed to be discarded without data writeback even if the discardable cache line is dirty.

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may facilitate and/or support scheduling tasks for one or more hardware components of a computing device.

Abstract: According to one implementation of the present disclosure, a method includes: receiving, by a hardware design generation circuit, a plurality of input signals of a software workload on a processing unit; training a power prediction model based on a toggling of the input signals accumulated over a training interval range; determining, by the hardware design generation circuit, a plurality of prediction proxies and respective weightings for the plurality of prediction proxies based at least partially on the trained power prediction model, wherein the plurality of weighted prediction proxies correspond to a power output of the hardware design generation circuit; and generating an updated circuit design of the processing unit based on the power output.