Abstract: A method to operate a head-mountable processing system, is provided. The head-mountable processing system comprising generating one or more control signals based upon a visual motion of a sequence of images for display by the head-mountable processing system, and transmitting the generated one or more control signals to a plurality of transducers to stimulate a wearer's vestibular system.

Abstract: A tiled-based graphics processor that comprises a plurality of tiling units is disclosed. The graphics processor includes an assigning circuit that assigns tiling units to sort geometry for initial regions of a render output that encompass plural primitive listing regions, and causes assigned tiling units to sort geometry for an initial region into primitive listing regions that the initial region encompasses.

Abstract: A first memory instance comprises one or more first bitcell arrays and one or more peripheral circuits. The first memory instance further comprises a high-speed voltage monitoring circuit operable to monitor a supply voltage and a power down signal in the first memory instance, the high-speed voltage monitoring circuit further operable to provide an output power ready signal derived from the supply voltage and the power down signal such that the output power ready signal indicates when the power down signal is low and the supply voltage is high.

Abstract: The present disclosure relates to a method of contrast-based autofocus for an image capture device, the method comprising: obtaining first sensor data representative of a first contrast characteristic of one or more images captured with a first focus setting, the first sensor data comprising first data values from respective image zones of the one or more images, an image zone being a region of an image; obtaining second sensor data representative of a second contrast characteristic of the one or more images, the second sensor data comprising second data values from respective image zones of the one or more images; processing the first sensor data by performing a first filtering operation on the first sensor data to obtain a first contrast characteristic metric, the first filtering operation being determined by the first contrast characteristic and based on the first sensor data of at least one image zone on a first image of the one or more images and one or more image zones related to the at least one image

Abstract: A graphics processing system that is operable to perform ray tracing is disclosed. It may be determined whether a ray may intersect geometry associated with a node by testing the ray against two different types of geometric object associated with the node: a first type that defines the volume that the node represents, and a second, different type that defines a region of the volume that the node represents within which geometry does not fall.

Abstract: A data processing system is disclosed that includes a data processing unit and a codec unit. A set of addresses of an address space is associated with the codec unit, and the codec unit, in response to a request from the data processing unit to access an address of the set of addresses associated with the codec unit, provides decoded data to the data processing unit or causes data provided by the data processing unit to be encoded.

Abstract: An order controlling interconnect circuit node of a data processing system couples to an interconnect circuit of a network and to target nodes. The node includes transmitting interface circuitry, message receiving interface circuitry, and control circuitry. The control circuitry is configured to monitor incoming “ready” response messages at the message receiving circuitry and to control the message transmitting interface circuity to send a cancellation request message to the target node of the oldest write request of the one or more second write-push requests when a “ready” response message has not been received for the first write-push request within a designated time period. Subsequent to sending the cancellation request message, a continuation request message is to the target node of the oldest write-push request of the one or more second write-push requests when a “ready” response message has been received for the first write-push request.

Abstract: A data processing apparatus is provided, which includes addition circuitry that performs a calculation of a sum of a first operand and a second operand. The addition circuitry produces an intermediate data prior to the calculation completing. Determination circuitry uses the intermediate data to produce the sum of the first operand and the second operand plus 1. Further determination circuitry configured to use the intermediate data to produce the sum of the first operand and the second operand plus 2.

Abstract: A method of image processing. The method comprises obtaining a set of image data, the set being associated with one or more parameters representative of one or more image capture characteristics for the set and comprising pixel intensity values representing image pixels having respective pixel locations in an image. The method comprises, for a given pixel intensity value in the set: determining an estimated noise value based on at least: the one or more parameters associated with the set, and a representative intensity value derived from one or more pixel intensity values in the set. The method comprises associating the estimated noise value with the given pixel intensity value.

Abstract: A command for causing a graphics processor to perform processing work for a graphics processing pipeline that the graphics processor can execute. A command to perform processing work for the graphics processing pipeline includes a first portion including a generic opcode that can be interpreted by a command processing circuit of the graphics processor to identify that the command is a command to perform processing work for the graphics processing pipeline and a second portion that is not used by command processing circuit but identifies to the graphics processing pipeline the particular processing operations to be performed. The first portion also includes information indicating a set of zero or more data values to be used for one or more processing operations for the graphics processing pipeline.

Abstract: A graphics processing apparatus includes a workload execution circuit to execute workloads and a performance counting circuit to count instances of performance metrics. A workload handling circuit receives commands and responds to performance counter sampling commands that indicate performance counter sampling contexts comprising performance metrics to be sampled and sampling intervals. The workload handling circuit monitors sampling intervals and triggers the workload execution circuit to write out sample values for performance metrics upon interval elapse. A driver receives performance metric sampling indications, allocates memory for sample values, generates performance counter sampling commands, and provides these to the workload handling circuit.

Abstract: There are provided apparatuses, methods, systems, chip-containing products and computer-readable storage media. Prefetching retrieves content from a memory system. History storage stores plural entries, each identifying a basic block of memory addresses, wherein the basic block of memory addresses is a contiguous range of memory addresses from which content has been requested to be retrieved from the memory system. An entry order of the plural entries corresponds to a basic block order in which corresponding basic blocks have been requested to be retrieved from the memory system. An entry-order-older basic block is associated with with an entry-order-younger basic block for which respective entries are stored in the history storage circuitry, these basic blocks being separated by at least a defined minimum number of entries in entry order in the history storage. A sequence of request addresses from which content is requested to be retrieved from the memory system is monitored.

Abstract: When processing regions of interest in frames in a data processing system that can execute a plurality of neural networks that are each configured to more optimally process a region of interest of a respective size, a region of interest is first identified within a frame, the size of the region of interest is determined, and one of the plurality of available neural networks is selected to use to process the region of interest based on the determined size. The region of interest is scaled to produce a scaled version of the region of interest, where the scaling is determined based on the selected neural network. The scaled version of the region of interest is then processed using the selected neural network.

Abstract: A method of malware detection includes performing, by a second device of a plurality of devices on a network, a fuzzy matching between a second sequence of events occurring at the second device and a first sequence of captured events that occurred at a first device of the plurality of devices on the network; determining, by the second device, that a result of the fuzzy matching reaches a first threshold; and in response to determining that the result of the fuzzy matching reaches the first threshold, initiating a detailed instrumentation at the second device. The method can further include determining, by the second device, that a first condition is satisfied; and in response to determining that the first condition is satisfied: generating a second malware behavior package including information from the detailed instrumentation; and communicating the second malware behavior package over the network.

Abstract: When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks from different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks for the different render outputs are enforced.

Abstract: An apparatus is described having processing circuitry for performing operations during which access requests to memory are generated. The processing circuitry generates memory addresses for the access requests using capabilities, where each capability indicates a pointer value and constraining information used to constrain access to memory using memory addresses derived from the pointer value. A marker indication field is stored in association with each capability to provide a marker value used to distinguish between static capabilities used to access statically allocated memory and dynamic capabilities used to access dynamically allocated memory.

Abstract: An apparatus comprises interface circuitry to interface with one or more peripheral devices, processing circuitry to execute software to communicate with a given peripheral device of the one or more peripheral devices, trusted execution environment circuitry communicatively coupled to the interface circuitry and the processing circuitry. The trusted execution circuitry is configured to: receive a transmission from one of the processing circuitry and the given peripheral device to the other one of the processing circuitry and the given peripheral device; and apply a control policy in respect of the received transmission and, based on the control policy, determine whether to forward the received transmission to said other one of the processing circuitry and the given peripheral device.

Abstract: A method of managing write-after-read (WAR) hazards in a graphics processor. A host processor when preparing a graphics processor command stream can identify possible WAR hazards between rendering jobs for example by detecting layout transitions and insert a suitable barrier into the graphics processor command stream. The graphics processor when encountering such a barrier can then determine whether it is possible to ignore the barrier and allow rendering jobs to be processed concurrently.

Abstract: A neural network system, method and apparatus are provided. A truth table matrix, an index vector and an input data tensor are read from a memory. At least a portion of the input data tensor is flattened into an input data vector. A scatter accumulate instruction is executed on the index vector and the input data vector to generate an intermediate vector. The truth table matrix and the intermediate vector are then multiplied to generate an output data vector.

Abstract: Various implementations described herein are directed to a device having neural network circuitry with an array of synapse cells arranged in columns and rows. The device may have input circuitry that provides voltage to the synapse cells by way of row input lines for the rows in the array. The device may have output circuitry that receives current from the synapse cells by way of column output lines for the columns in the array. Also, conductance for the synapse cells in the array may be determined based on the voltage provided by the input circuitry and the current received by the output circuitry.