Abstract: Prediction circuitry for a data processing system comprises input circuitry to receive status inputs associated with instructions or memory access requests processed by the data processing system. Unified predictor circuitry comprises shared hardware circuitry configurable to act as a plurality of different types of predictor. The unified predictor circuitry generates, according to a unified prediction algorithm based on the status inputs and a set of predictor parameters, an array of predictions comprising different types of prediction of instruction/memory-access behaviour for the data processing system. A configuration subset of the predictor parameters is configurable to adjust a relative influence of each status input in the unified prediction algorithm used to generate the array of predictions. Output circuitry outputs, based on the plurality of types of prediction, speculative action control signals for controlling the data processing system to perform speculative actions.

Abstract: Apparatuses, systems, chip-containing products, methods and computer-readable media are disclosed relating to register bank circuitry providing registers holding data values and comprising at least one read port. On receipt of a register selection vector a read address compression procedure is performed on a vector of read addresses. The register selection vector comprises element validity indicators corresponding to address elements of the vector of read addresses. The compression procedure comprises identifying selected/non-selected element positions and shifting in the vector of read addresses a set of active read addresses in a predetermined direction towards a predetermined element position to form a contiguous group in the vector of read addresses ending on one side at the predetermined element position. A read vector of data values identified by the set of active read addresses is read out from the registers via a selected read port of the at least one read port.

Abstract: There is provided an apparatus, a system, a chip containing product, a method, and a medium. The apparatus comprises: a plurality of registers comprising at least one array register having a plurality of array regions. The apparatus comprises processing circuitry to receive issued instructions and to process those instructions. The apparatus is also provided with control circuitry responsive to receipt of an instruction requiring access to two or more array regions: to decompose the instruction into two or more execution parts, each corresponding to one of the two or more array regions; and for each execution part, to delay issuing the execution part until it is predicted that the execution part can be processed hazard free. The control circuitry is capable of issuing the two or more execution parts in different cycles based on when it is predicted that each execution part can be processed hazard free.

Abstract: An apparatus for address translation is provided in order to translate virtual addresses used by devices in a data processing system into physical addresses for accessing memory. In accordance with the techniques disclosed herein, state tracking circuitry is provided to maintain the state of a page table entry that specifies such address translations. The state can be used to assess whether or not the address translation entry is worth storing in an address translation cache provided for faster access of previously used address translations. Accordingly, the techniques disclosed herein allow for more efficient use of the limited capacity available in the address translation cache as well as additional uses of a page table entry's state.

Abstract: Subject matter disclosed herein may relate to devices and techniques for cooling three-dimensional integrated circuit (IC) devices. In particular embodiments, an IC device may comprise a three-dimensional structure having a first surface adapted to face a mounting surface and a second surface opposite the first surface, and having one or more cavities to extend at least below the second surface.

Abstract: The present disclosure relates to tile-based rendering systems. In particular there is provided a new primitive list format in which a sequence of commands generated for the primitive list includes a number of different respective types of commands including ‘primitive’ type commands storing primitive data, ‘state’ type commands storing state data and ‘configuration’ type commands for storing configuration data, wherein the primitive, state and configuration data can accordingly be stored separately in the primitive list, using the different respective types of commands. Also disclosed are techniques for encoding the data into the respective different types of commands.

Abstract: A processor, method and computer program for artificial neural network processing and comprising a neural processing element operable to perform processing operations on data; a dedicated neural storage element accessible only by the neural processing element; a shared storage element accessible by the neural processing element and one or more other processing elements configured to perform separate processing operations; and a control element operable to control task processing by the processor, respective tasks to be executed as a graph of operations, wherein each operation maps to a corresponding neural processing element, and wherein each connection between operations in the graph maps to a corresponding storage element for storing in-process data; and wherein, for a given task connection, the control element is configured to select between neural storage and shared storage and to direct reading and writing of in-process data corresponding to the connection to the selected storage.

Abstract: In response to instruction decoding circuitry decoding a conditional write instruction, processing circuitry determines whether a predetermined condition is satisfied for a target cache line corresponding to a target address specified by the conditional write instruction. If the predetermined condition is satisfied for the target cache line, a write request is issued to update the target cache line. If the predetermined condition is not satisfied for the target cache line, a failure indication is returned. The processing circuitry selects, depending on whether the sequence of instructions specifies cache-line-retention hint information applicable to the conditional write instruction, whether to prevent a unique coherency state of the target cache line being relinquished by a local cache associated with the processing circuitry for a retention period following processing of the conditional write instruction.

Abstract: An apparatus is provided with asynchronous boundary transfer circuitry to transfer data across a clock domain boundary. The asynchronous boundary transfer circuitry has buffer circuitry with buffer storage elements, and source and sink synchronisation circuitry to control the transfer of the data. To initiate a transfer of data items, the source synchronisation circuitry sends a transfer request to the sink synchronisation circuitry indicating that the data items have been stored in one or more buffer storage elements and encoding an indication of one or more elements of destination circuitry targeted by the data items. The sink synchronisation circuitry is responsive to a transfer request to decode an indication of the elements of destination circuitry targeted by the data items, provide incoming data item notifications to elements of destination circuitry, and allow the data items to be read from buffer storage elements indicated by the given transfer request.

Abstract: A memory device includes a memory array with first and second memory regions, multiple communication ports and coherency control circuitry. The communication ports couple the memory device to host computers, enabling a first host to write a data block to the second region, write a message, including a data descriptor of the data block, to the first or second region, and write message metadata, associated with the message, to the first region, and also to enable a second host to read the message metadata, the data descriptor and the associated data block. The coherency control circuitry controls coherency of data in the first region, including sending an invalidation request to the second host to invalidate a copy of the message metadata stored in a local cache of the second host. The invalidation request is sent in response to the first host writing the message metadata to the first region.

Abstract: For a set of data points which are desired to be processed according to neural network processing, each data point corresponding to a position in space, data point information indicative of one or more properties of the data points is received (500), and connectivity information indicative of connections between the data points is determined (503). An order for the data points is then determined (504) based on the positions in space of the data points, and updated connectivity information (505) is generated based on the initial connectivity information and the determined order for the set of data points. The updated connectivity information and data point information are provided for further processing (507) to be performed by a processor operable to execute neural network processing.

Abstract: A processing unit is described that receives an instruction to perform a first operation on a first layer of a neural network, block dependency data, and an instruction to perform a second operation on a second layer of the neural network. The processing unit performs the first operation, which includes dividing the first layer into a plurality of input blocks, and operating on the input blocks to generate a plurality of output blocks. The processing unit then performs the second operation after the first operation has generated a set number of output blocks defined by the block dependency data.

Abstract: A technology provides quantified reliance data for at least one of an electronic computing device node and a connection in network, the technology comprising instrumenting at least one of the device and the connection to generate datasets comprising at least one of a device feature vector and a connection feature vector, each feature vector being encoded in a form suitable for transmission over a connection in the network; performing computational inferencing over the datasets to generate quantified reliance data comprising at least one of a trust indicator, a diagnostic indicator and a performance indicator associated with at least one of the device and the connection; and supplying the quantified reliance data in a form usable for selecting an action to be performed, the action being performed by or performed to at least one of the at least one electronic computing device node and the at least one connection.

Abstract: A data integrity tree for memory security comprises a plurality of nodes, wherein a linked series of nodes of the data integrity tree protects a data item stored in memory. A parent node in the linked series of nodes comprises a plurality of counters, each associated with a respective child node and providing an input to a protection function associated with the respective child node. A node authentication code protects the plurality of counters in each parent node and is dependent on a counter in a node above the parent node in the data integrity tree. A plurality of hash value child nodes each comprises a plurality of encrypted hash values generated as a function of a respective block of data stored in the memory and as a function of a counter comprised in a node above the hash value child node in the data integrity tree.

Abstract: A data processing apparatus comprises processing circuitry to execute processing instructions, the processing circuitry comprising: a set of physical registers; instruction decoder circuitry to decode processing instructions; detector circuitry to detect groups of instructions which comply with a conflict condition, in which a group of instructions complies with the conflict condition at least when a given storage element is written to by a maximum of one instruction of that group of instructions; instruction issue circuitry to issue decoded instructions for execution; and instruction execution circuitry to execute instructions decoded by the instruction decoder circuitry.

Abstract: When storing data of an array of data in memory in a graphics processing system, respective memory regions are allocated for storing blocks of the data array, with the allocated region of memory for a block of the data array corresponding to a maximum possible size of the block of the data array when compressed, and being divided into a plurality of memory allocation sub-blocks, having at least one sub-block having a first, larger size and at least one sub-block having a second, smaller size. Blocks of the data array are compressed using a compression scheme, with each compressed block being stored in one or more of the sub-blocks of its allocated memory region.

Abstract: Processing circuitry executes instructions from an instruction stream comprising a state transition instruction followed by a further instruction. The processing circuitry is responsive to the state transition instruction to change a security state of the processing circuitry. Issue circuitry issues the further instruction to be speculatively executed prior to the state transition instruction being completed, and the further instruction has a requirement with respect to the security state. Completion circuitry performs a completion operation on the further instruction comprising checking whether the requirement with respect to the security state is met.

Abstract: A method reduces storage usage during processing of a neural network performed by an information processing apparatus comprising a storage. The network may be represented by operators that operate on an input feature map and generate an output feature map. A representation of the network is generated as a linear sequence of operators. Operators are identified in the sequence that cannot form part of a cascade and are to be processed with the entire input and output feature map of the respective operator in the storage. The method forms one or more cascades of two or more successive operators in the sequence for which the input feature map of each operator of the cascade is processed in portions, which portions are less than the entire input feature map.

Abstract: A processing unit is provided which comprises volatile storage for storing machine learning data in binary representation, and a data processing engine communicatively coupled to the volatile storage. The processing unit is configured to selectively invert the bit values in binary representations of portions of the machine learning data when performing storage operations using the volatile storage. A computer-implemented method, and non-transitory computer-readable storage medium comprising instructions for executing the method are also provided. The method comprises receiving a request to perform a storage operation on the volatile storage using the machine learning data and performing the storage operation, including, selecting a portion of the machine learning data and inverting bit values in a binary representation of the selected portion. A computer-implemented method comprising receiving a request to store machine learning data on volatile storage and storing the machine learning data is also provided.

Abstract: Various implementations described herein are related to a device with fabrication test circuitry having transistors arranged in a parallel branch configuration between a supply voltage and a single pad. In some applications, each transistor in an off-current branch may be separately deactivated so as to test leakage current applied to the pad by way of the off-current branch, and also, each transistor in an on-current branch may be deactivated so as to further test the leakage current applied to the pad by way of the off-current branch.