Abstract: A data processing apparatus includes multithreaded processing circuitry to perform processing operations of a plurality of micro-threads, each micro-thread operating in a corresponding execution context defining an architectural state. Decoder circuitry responds to a first occurrence of a detach instruction to generate a first micro-thread in respect of a first block of instructions, and a second occurrence of the detach instruction to generate a second micro-thread in respect of a second block of instructions. The second block of instructions comprises a data dependency in respect of a resource accessed in the first block of instructions. Also provided is a data processing apparatus with input circuitry that receives input code with a first block of instructions and a second block of instructions. Output circuitry produces output code corresponding to the first block of instructions and the second block of instructions. Processing circuitry generates the output code based on the input code.

Abstract: An integrated circuit data processing system comprises a plurality of request nodes, a plurality of DVM nodes, assignment logic, an interconnect system and a first chip-to-chip gateway. A first request node is configured to send a DVM message to the DVM node, and the DVM node is configured, in response, to send a first category of snoop message to one or more peer DVM nodes. A second DVM node, is configured, in response, to send a second category of snoop message to request nodes within the domain of the second DVM node and a third category of snoop message to a DVM node of a second integrated circuit. The first chip-to-chip gateway is configured, upon receipt of a snoop message from the second integrated circuit, to send a DVM message to the second DVM node, and the second DVM node is configured, in response, to send a fourth category of snoop message to one or more peer DVM nodes.

Abstract: A data processing network comprises an integrated-circuit data processing apparatus and at least one external device, external to the apparatus. The integrated-circuit data processing apparatus comprises an interconnect system, at least one target device coupled to the interconnect system, and a requesting node, coupled to the interconnect system. The requesting node is configured to receive requests from the at least one external device, and output the requests to a target device of the at least one target device via the interconnect system, thereby acting as a bridge for the at least one external device. The requesting node is configured to receive at least one busyness indication from at least one of the target devices, and, based on the received busyness indication(s), to throttle its outputting of requests received from the at least one external device to at least one of the at least one target devices via the interconnect system.

Abstract: An integrated-circuit apparatus comprises a 2D or 3D interconnect comprising a plurality of routers distributed along at least an X axis and a Y axis, wherein the 2D or 3D interconnect comprises at least a first layer of routers logically coupled as a polygonal mesh of routers. The interconnect further comprises a first storage or input-output node coupled to the interconnect along a Y-axis edge of the first layer, or a further layer, of routers of the interconnect; and a second storage or input-output node coupled to the interconnect along an X-axis edge of the first layer, or a further layer, of routers of the interconnect. At least a first router of the first layer of routers is configured to use X-Y routing when routing a flit originating from the first storage or input-output node and destined for a first target node coupled to the interconnect.

Abstract: Processing circuitry is provided to perform vector operations, with instruction decoder circuitry used to decode instructions from a set of instructions to control the processing circuitry to perform the vector operations specified by the instructions. Array storage that has storage elements to store data blocks is used to store at least one two-dimensional array of data blocks accessible to the processing circuitry when performing the vector operations. The set of instructions comprises a complex valued outer product instruction specifying a first source operand, a second source operand, and a destination operand, wherein each of the first source operand and the second source operand is a vector operand comprising a plurality of source data elements, each source data element is a complex number formed of a real part and an imaginary part, and the destination operand identifies a given two-dimensional array of data blocks within the array storage.

Abstract: A data processing system is disclosed that includes one or more data processing units and a data reordering unit. The data reordering unit receives data requested by the one or more data processing units from the memory system, and returns the data to the one or more data processing units in an order that is based on tracking an order of requests issued by the one or more data processing units.

Abstract: An integrated circuit data processing system for processing requests, comprising an interconnect system, at least one requestor; and a data processing apparatus. The interconnect system forms part of a first layer, associated with the transfer of requests. The data processing apparatus comprises an active tracker (2), a request buffer (5), and property decoding logic (11). The active tracker (2) forms part of a second layer (23), associated with the processing of requests. The property decoding logic (11) decodes at least a portion of a payload of a request stored in the request buffer to determine at least one second-layer property of the request. The apparatus determines a request to pass from the request buffer (5) to the active tracker (2) based on the at least one second-layer property. The apparatus issues credits to a requestor, wherein a credit is associated with a request-buffer-storage-element which is reserved for a request (24) from the requestor.

Abstract: An integrated-circuit apparatus comprises a requestor node and a first plurality of coherency nodes configured to provide a distributed system-level cache, each coherency node being configured to provide system-level caching for a respective set of memory addresses allocated to the coherency node. The first plurality of coherency nodes, or a second plurality of coherency nodes, is configured to provide respective distributed local coherency caches for a set of local coherency domains, wherein each of the coherency nodes of the first or second plurality is configured to provide local coherency caching for a respective set of memory addresses allocated to the coherency node. The apparatus is configured to assign the requestor node and each coherency node to a respective local coherency domain of the set of local coherency domains. The requestor node is configured to send a first memory request to a coherency node, in a same local coherency domain as the requestor node, for local-coherency-cache lookup.

Abstract: When performing a tile-based rendering process to generate a render output, a geometry processing part of a graphics processor provides an indication to a fragment processing part of the graphics processor to perform a render for the render output being generated. The indication to perform the render is associated with metadata that can be set be set to indicate that the render to be performed is a first render to be performed for the render output that is being generated, and with metadata that can be set to indicate that the render to be performed is a final render to be performed for the render output that is being generated. In response to the indication, the fragment processing part performs a render for the render output being generated, in accordance with the metadata.

Abstract: A method of operation of a tile-based graphics processor, including: receiving an instruction to process data to produce an output; detecting an indicator that a portion of the output is to be processed with redundancy; associating the indicator with at least one tile associated with the portion of the output; duplicating the processing of the data associated with the at least one tile by one or more execution units of the graphics processor to produce output data for each of a first and a second instance of the at least one tile; comparing output data for the first and the second instances of the at least one tile generated by the one or more execution units of the graphics processor; and responsive to detection of a mismatch between the output data of the first and the second instances, communicating a signal.

Abstract: The present techniques relate to mitigating droop conditions over state transitions in systems having dynamic voltage and frequency scaling and there is disclosed a method of controlling a dynamic voltage and frequency scaling circuit, comprising: initiating a transition from a first voltage and frequency state to a second voltage and frequency state; switching activity from a first nominal source to a first fallback source; retuning the first nominal source to become a second fallback source at the second voltage and frequency state; switching activity from the first fallback source to the second fallback source; retuning the first fallback source to become a second nominal source at the second voltage and frequency state; and switching activity from the second fallback source to the second nominal source.

Abstract: An apparatus comprises exception return state register storage, and processing circuitry. In response to a guarded control stack (GCS) exception return state push instruction, the processing circuitry obtains exception return state information from the exception return state register storage and push the state information to a GCS data structure. In response to a GCS exception return state pop instruction, the processing circuitry obtains GCS-protected exception return state information from the GCS data structure. In at least one operating state, the processing circuitry detects, in response to an attempt to modify the exception return state information stored in the exception return state register storage, whether an exception return state lock parameter is in a locked state or an unlocked state, and signals a fault when it is in the locked state.

Abstract: The present disclosure relates generally to integrated circuits and relates more particularly to indexed vector permutation operations.

Abstract: There is provided an apparatus that includes processing circuitry for performing processing in one of a fixed number of at least two domains. One of those domains is subdivided into a variable number of execution environments and memory protection circuitry uses a key input to perform encryption or decryption on the data of a memory access request issued to a memory address from within a current one of the domains. The key input is different for each of the domains and for each of the execution environments, the key input for each of the domains is fixed at boot time of the apparatus, and the key input for each of the execution environments is dynamic.

Abstract: A method for filtering adversarial noise from an input signal is provided. The method comprises receiving an input signal which has an unknown level of adversarial noise. The input signal is filtered with a neural network to remove noise from the received input signal, thereby producing a filtered signal. A confidence value is calculated, the confidence value being associated with the filtered signal, and indicative of a level of trust relating to the filtered signal. The filtered signal and the confidence value may then be output.

Abstract: An apparatus comprises instruction decoding circuitry configured to decode instructions of a program thread executed by a given processor core; and load/store control circuitry configured to select a target point of a memory system hierarchy at which to allocate data for a target cache line specified by a load/store instruction decoded by the instruction decoding circuitry. The load/store control circuitry is configured to select the target point of the memory system hierarchy depending on whether the load/store instruction is associated with a memory contention hint provided by a contention hint instruction decoded by the instruction decoding circuitry, the memory contention hint indicating that the target cache line is likely to be subject to contention for access from multiple threads of processing.

Abstract: There is provided an apparatus configured to operate as a shader core, the shader core configured to perform a complex rendering process comprising a rendering process and a machine learning process, the shader core comprising: one or more tile buffers configured to store data locally to the shader core, wherein during the rendering process, the one or more tile buffers are configured to store rendered fragment data relating to a tile; and during the machine learning process, the one or more tile buffers are configured to store an input feature map, kernel weights or an output feature map relating to the machine learning process.

Abstract: An integrated circuit data processing system comprises a plurality of request nodes, a plurality of DVM nodes, assignment logic, an interconnect system and a first chip-to-chip gateway. A first request node is configured to send a DVM message to the DVM node, and the DVM node is configured, in response, to send a first category of snoop message to one or more peer DVM nodes. A second DVM node, is configured, in response, to send a second category of snoop message to request nodes within the domain of the second DVM node and a third category of snoop message to a DVM node of a second integrated circuit. The first chip-to-chip gateway is configured, upon receipt of a snoop message from the second integrated circuit, to send a DVM message to the second DVM node, and the second DVM node is configured, in response, to send a fourth category of snoop message to one or more peer DVM nodes.

Abstract: Apparatuses, computer programs and methods are disclosed, relating 2D arrays of data elements and a 2D array of processing elements. A first 2D array of data elements provides data values for processing by each processing element and a second 2D array of data elements provides control values controlling the processing. The 2D array of processing elements has a data flow direction across the 2D array of processing elements, and the data flow direction proceeds from a starting set of processing elements of the 2D array of processing elements. For each processing element not in the starting set of processing elements, the data processing operation preformed takes as an operand a respective data value provided by a neighbouring data element of the first 2D array of data elements and selection of the neighbouring processing element is controlled by a corresponding source control value in the second 2D array of data elements.

Abstract: An apparatus comprises execution circuitry configured to execute a given instruction to produce a given data value. Value analysis circuitry is configured to perform an analysis of the given data value produced by the execution circuitry to determine at least one property of the given data value, and register allocation circuitry is configured to make a register allocation decision regarding storage of the given data value in a physical register file in dependence on the analysis of the given data value.