Abstract: Apparatuses, methods of data processing, computer program, and computer-5 readable media are disclosed. A data processing pipeline performs data processing operations in dependence on a received sequence of instructions. Extension processing circuitry associated with the data processing pipeline and performs a delegated task in response to a delegation signal received from the data processing pipeline. Decoding the received sequence of instructions generates control signals to control the data processing pipeline to perform the data processing operations. The decoding is responsive to an extension start instruction specifying the delegated task to: generate the control signals to control the data processing pipeline to issue the delegation signal to the extension processing circuitry to delegate the delegated task to the extension processing circuitry. The extension processing circuitry performs the delegated task asynchronously to the data processing operations performed by the data processing pipeline.

Abstract: There is provided an apparatus for data processing. The apparatus includes a data processing pipeline that performs one or more data processing operations and extension processing circuitry associated with the data processing pipeline that performs one or more delegated tasks. Page table walk circuitry performs a page table walk operation on memory in response to either the one or more data processing operations or the one or more delegated tasks. The extension processing circuitry performs the one or more delegated tasks asynchronously to the one or more data processing operations performed by the data processing pipeline.

Abstract: A method of debugging a program is disclosed in which one or more sets of one or more instructions are inserted at one or more places in the program which, when executed by a data processor, cause the data processor to determine whether to pause execution of the program using information that indicates whether to continue executing the program without pausing, and when it is determined to pause execution of the program, pause execution of the program.

Abstract: An apparatus and method for responsively downgrading a forwarding snoop flow of the incoming snoop to a non-forwarding snoop flow. A snoopee agent of a data processing network that is configured to respond to detection of a memory encryption context identification (MECID) mismatch between a MECID of an incoming snoop and a locally cached MECID of the snoopee agent and responsively downgrade a forwarding snoop flow of the incoming snoop to a non-forwarding snoop flow.

Abstract: There is provided an apparatus, a method of operating an apparatus, a computer program, and a computer-readable medium. The apparatus comprises a pipeline for processing instructions. The pipeline comprises decoder circuitry responsive to receipt of the instructions to control the pipeline to perform processing operations. The apparatus further comprises extension processing circuitry responsive to identification, by the pipeline, of a delegated task to perform the delegated task asynchronously to the pipeline and configured to maintain extension state information indicative of an execution context of the extension processing circuitry independent of processing state information associated with the pipeline. The decoder circuitry is responsive an extension context save instruction comprising a storage location identifier, at a point of storing the extension state information, to store the extension state information to a location identified by the storage location identifier.

Abstract: There is provided an apparatus, a method, a chip containing product, a system and a medium. The apparatus is provided with an instruction fetch queue for storage of instruction fetch entries, and prefetching circuitry configured, for each instruction fetch entry and in response to a determination that a block of instructions indicated by that instruction fetch entry is not present in instruction storage circuitry, to issue a request to fetch the block and to cause the block to be allocated to the instruction storage circuitry. The apparatus is also provided with control circuitry configured to suppress issuing the request in response to a number of outstanding requests meeting or exceeding a variable throttling threshold. The control circuitry is configured to derive the variable throttling threshold from properties of previously fetched blocks, the properties determined before or during storage of the previously fetched blocks in the instruction storage circuitry.

Abstract: A sequence of operations to process an initial input data array for the sequence of operations to generate a final output data array of the sequence of operations on a processor operable to execute neural network processing, the sequence are performed for respective blocks of the initial input data array on a block-by-block basis, and when performing an operation in the sequence whose output data is input data for another operation in the sequence, the output data is used as input data for another operation of the sequence is stored in local storage of the processor that is performing the neural network processing, and provided as input data for the another operation in the sequence from the local storage, but for the final operation in the sequence, the final output data array is stored in a main memory of the data processing system.

Abstract: When performing texture processing operations in a graphics processing system, for a texture processing operation that requires M input texture data elements from an array of texture data elements, each of the M texture data elements is selected from a different set of texture data elements having a different set of positions within the texture data array. The texture processing operation is then performed using the M texture data elements.

Abstract: When performing a texture sampling operation that uses the results of plural texture filtering operations to provide an overall output sampled texture value in a graphics processing system, it is determined whether a texture filtering operation in the set of plural texture filtering operations that are to be performed to provide the overall output sampled texture value can be at least partially merged with another texture filtering operation in the set of texture filtering operations. If so a merged texture filtering operation is performed for the two texture filtering operations, with the result of the merged texture filtering operation being used when providing the overall output sampled texture value.

Abstract: A system-on-chip comprises processing circuitry to process input data to generate output data, and power management circuitry to control power management policy for at least a portion of the system-on-chip. The power management circuitry controls the power management policy depending on metadata indicative of a property of the input data to be processed by the processing circuitry.

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to enhance capabilities of peer devices. In an implementation, at least one agent to: identify one or more learnable capabilities enabled by one or more parameters that are accessible via receipt of one or more message at the one or more communication devices from one or more other computing devices; and determine a utility of augmenting at least one of the one or more learning engines with at least one of the one or more learnable capabilities.

Abstract: A first series of memory access transactions are received from a first set of compressed data having a number of first transactions indeterminate in a transaction receiver, and a second series of memory access transactions are received from a second set of compressed data having a number of second transactions indeterminate in the transaction receiver. A count of outstanding transactions for the combined first and second sets of compressed data is received in the transaction receiver, and memory space is allocated for the first and second series of transactions based at least in part on the received count of outstanding combined transactions. The first series of transactions are stored sequentially from a first end of the allocated memory space and the second series of transactions are stored sequentially from a second end of the allocated memory space opposite the first end.

Abstract: Multiple successively spatially downsampled versions of a rendered image frame are generated for at least one two-dimensional signal component of one or more two-dimensional signal components of an image frame, and one or more versions of the rendered image frame are selected from among the rendered image frame and the spatially downsampled versions of the rendered image frame for sampling a texture feature based, at least in part, on a prediction computed by a neural network.

Abstract: When generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks from different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks for the different render outputs are enforced. In particular, there is disclosed a mechanism for suspending the sequence of rendering jobs (so that it may subsequently be resumed).

Abstract: A graphics processing system in which a render output is sub-divided into a plurality of tiles for rendering. The graphics processing system includes a memory system, a tiling circuit and a primitive list preparation circuit. The tiling circuit determines which primitives are to be rendered for regions into which the render output is sub-divided. The regions form a plurality of rows and columns of regions. The primitive list preparation circuit prepares and stores primitive lists for regions of the render output identifying the primitives that are to be rendered for the regions. The primitive list preparation circuit also stores a groups of pointers, each group pointing to respective primitive lists. The regions of the render output corresponding to the primitive lists that are pointed to by the pointers of the group of pointers comprise adjacent regions spanning a plurality of rows and a plurality of columns of regions.

Abstract: When performing rendering in a tile-based graphics processor that comprises plural rendering processors, different regions of the render output are allocated to different ones of the rendering processors for processing. The processing of the render output is tracked to determine when a portion of the render output that is still to be allocated to the rendering processors for processing falls below a threshold, and when it is determined that a portion of the render output that is still to be allocated to the rendering processors for processing falls below the threshold, smaller regions of the render output are thereafter allocated to the rendering processors for processing.

Abstract: A method for processing an image. The method comprises receiving intensity values of pixels for each of a plurality of images captured by an image sensor during a detection window. The method comprises identifying, using the intensity values, a plurality of transitions occurring at different times during the detection window, each transition of the plurality of transitions being identified on the basis of detecting intensity values of pixels that have been clipped in images between which such transitions may occur. The method comprises, based on identifying the plurality of transitions occurring during the detection window, at least one of: adjusting an exposure level of the image sensor; and determining a tonemapping function having a tonemapping strength, and applying the tonemapping function to the intensity values of a current image to generate tonemapped intensity values, wherein the image sensor has a current exposure level when the current image is captured.

Abstract: An apparatus and method are provided, the apparatus comprising: interconnect circuitry to couple a device to one or more processing elements, each processing element operating in a trusted execution environment; and secure stashing decision circuitry to receive stashing transactions from the device and to redirect permitted stashing transactions to a given storage structure accessible to at least one of the one or more processing elements. The secure stashing decision circuitry is configured, in response to receiving a given stashing transaction, to determine whether the given stashing transaction comprises a trusted execution environment identifier associated with a given trusted execution environment, and to treat the given stashing transaction as a permitted stashing transaction when redirection requirements, dependent on the trusted execution environment identifier, are met.

Abstract: An apparatus is provided having cache circuitry providing a plurality of cache lines to store data for access by a processing element, and cache control circuitry to control storage of data in the cache circuitry. The cache control circuitry is arranged to manage storage of data within the cache circuitry for data blocks of size X exceeding a size of data that is storeable within a single cache line of the cache circuitry. The cache control circuitry is arranged, for each data block to be stored in the cache circuitry, to determine in which state of a plurality of states to store that data block in the cache circuitry, the plurality of states comprising an uncompressed state where the data block is stored within a plurality Y of cache lines and at least one compressed state where the data block is represented in a form occupying less than Y cache lines within the cache circuitry.

Abstract: Processing circuitry is provided to perform operations, along with instruction decoder circuitry to decode instructions to control the processing circuitry to perform the operations specified by the instructions. A set of registers is used to hold data values for access by the processing circuitry. The instruction decoder circuitry is responsive to an ordering constrained access instruction used to access multiple data values, and providing register indication information and memory address information, to control the processing circuitry to perform a sequence of access operations, where each access operation causes a data value from amongst the multiple data values to be moved between an associated register determined from the register indication information and an associated memory address determined from the memory address information.