Abstract: A counter integrity tree for memory security includes at least one split-counter node specifying at least two counters each defined as a combination of a major count value shared between the at least two counters and a respective minor count value specified separately for each of the at least two counters. This increases the number of child nodes which can be provided per parent node of the tree, and hence reduces the number of tree levels that have to be traversed in a tree covering a given size of memory region. The minor counter size can be varied dynamically by allocating nodes in a mirror counter integrity tree for accommodating larger minor counters which do not fit in the corresponding node of the main counter integrity tree.

Abstract: A method of assigning tenancy to a device during bootstrapping between a device and a server in a network includes transmitting a device identifier to a bootstrap server. The method further includes receiving, at the device, a device server address to enable the device to register with the device server. The tenancy is assigned to the device with the device server address.

Abstract: A data processing apparatus comprising: at least one initiator device for issuing transactions, a hierarchical memory system comprising a plurality of caches and a memory and memory access control circuitry. The initiator device identifies storage locations using virtual addresses and the memory system stores data using physical addresses, the memory access control circuitry is configured to control virtual address to physical address translations. The plurality of caches, comprise a first cache and a second cache. The first cache is configured to store a plurality of address translations of virtual to physical addresses that the initiator device has requested. The second cache is configured to store a plurality of address translations of virtual to physical addresses that it is predicted that the initiator device will subsequently request. The first and second cache are arranged in parallel with each other such that the first and second caches can be accessed during a same access cycle.

Abstract: A transition detection circuit and method of operation of such a circuit are provided, the transition detection circuit having pulse generation circuitry to receive an input signal and to generate a pulse signal in response to a transition in the input signal, and pulse detection circuitry to assert an error signal on detection of the pulse signal generated by the pulse generation circuitry. The pulse generation circuitry has pulse control circuitry to control a property of the pulse signal dependent on a timing window indication signal. In particular, when the pulse signal is generated at least partly while the timing window indication signal is set, the pulse control circuitry controls the property of the pulse signal such that generated pulse signal is detected by the pulse detection circuitry.

Abstract: An apparatus 2 for performing serial data communication with a target device 4, such as an integrated circuit, utilizes serial transfer circuitry 16 to perform a serial transfer of data to a communication register 26 in the target device 4 and serial retrieval circuitry 18 to retrieve an acknowledge signal 32 indicating whether or not the target device is ready to perform further processing following such a transfer. Delay control circuitry 20 serves to apply a predetermined delay period following the transfer of the serial data via the serial transfer circuitry before initiating the retrieval of the acknowledge signal. This predetermined delay period is controlled in dependence upon the ready status indicated by the acknowledge signals retrieved such that the proportion of acknowledge signals retrieved which indicate an unready status meets a predetermined condition, such as being less than a non-zero predetermined value.

Abstract: A processing circuit is responsive to at least one conditional instruction to perform a conditional operation in dependence on a current value of a subset of at least one condition flag. A trace circuit is provided for generating trace data elements indicative of operations performed by the processing circuit. When the processing circuit 4 processes at least one selected instruction, then the trace circuit generates a trace data element including a traced condition value indicating at least the subset of condition flags required to determine the outcome of the conditional instruction. A corresponding diagnostic apparatus uses the traced condition value to determine a processing outcome of the at least one conditional instruction.

Abstract: A graphics processing system comprises a memory that stores graphics data. The graphics data stored in the memory is accessible using virtual memory addresses that map to physical memory addresses in the memory. The graphics processing system further comprises page merging circuitry configured to use metadata provided for a set of graphics data to determine whether any pages of the set of graphics data are similar to each other. The pages of the set of graphics data that are determined as being similar to each other are merged by mapping the virtual memory addresses for those pages to the same physical memory address in the memory. The page merging process can provide a way to reduce the number of physical memory addresses needed to store the pages of the set of graphics data in the memory.

Abstract: When encoding an array of data elements, or a stream of such arrays, using an encoder comprising encoding circuitry operable to encode the array(s) of data elements as a plurality of independent segments, wherein each independent segment can be decoded independently; a header is generated for output with an encoded data stream including the plurality of independent segments wherein the header contains information indicative of the location of each of the plurality of independent segments within the encoded data stream. When an encoded data stream associated with such a header is to be decoded, a decoder may thus read the header to identify the location of the independent segment within the data stream and then read and decode the identified segments from the identified location(s) in the data stream.

Abstract: A data processing apparatus comprises processing circuitry configured to predict whether a region of output data to be generated by the apparatus for a current set of output data will be similar to a region of output data generated and stored in memory for a previous set of output data. When it is predicted that the new region of output data will be similar to the previous region of output data, the new region of output data is prevented from being generated and the previous region of output data is used for the current set of output data instead. The data processing apparatus can provide a way to avoid generating areas of sets of output data that are static from one set of output data to the next.

Abstract: An apparatus and method are provided for maintaining address translation data within an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. The address translation cache is used to store address translation data of a plurality of different types representing address translation data specified at respective different levels of address translation within a multiple-level page table walk. The plurality of different types comprises a final level type of address translation data that identifies a full translation from the virtual address to the physical address, and at least one intermediate level type of address translation data that identifies a partial translation of the virtual address.

Abstract: Broadly speaking, embodiments of the present techniques provide a reconfigurable hardware-based artificial neural network, wherein weights for each neural network node of the artificial neural network are obtained via training performed external to the neural network.

Abstract: Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Abstract: Circuitry comprises: a set of bit processing circuitries to apply two or more successive instances of bitwise processing to an ordered bit array; each bit processing circuitry for a given bit position within the ordered bit array comprising: bit shifting circuitry to selectively apply a bit shift of a respective input bit to a next bit processing circuitry in a first direction relative to the ordered bit array, in response to an active state of a bit shift control signal, the bit shifting circuitry not applying the bit shift in response to an inactive state of the bit shift control signal; and bit shift control circuitry to selectively allow or inhibit a bit shifting operation in response to one or more inhibit control signals; in which: the bit shift control circuitry is configured to selectively propagate an output inhibit control signal, indicating that a bit shifting operation should be inhibited, as an inhibit control signal to bit processing circuitry applying a next instance of the bitwise processing a

Abstract: When encoding an array of quantized frequency domain coefficients for the chrominance data values for a block of data elements being encoded, it is determined whether the encoding of the frequency domain coefficients for the luminance data for the block being considered was indicated as to be omitted. If so, it is then determined whether the non-zero coefficients in the array of quantized chrominance data value frequency domain coefficients for the block are few in number and/or small in size. If the number and/or size of the non-zero quantized chrominance value frequency domain coefficients is determined to be sufficiently few and/or small, then the encoding of the quantized frequency domain coefficients for the chrominance data for the block is omitted.

Abstract: A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.

Abstract: A data processing apparatus implements an artificial neural network to generate a result that indicates one or more encoding options to use when encoding a set of data elements using an encoding scheme. The data processing apparatus can provide an efficient way of selecting between possible encoding options that can be used to encode a set of data elements.

Abstract: A memory system of a data processing system includes one or more storage devices and a data rearrangement engine for moving data between memory regions of the plurality of memory regions. The data rearrangement engine is configured to rearrange data stored at non-contiguous addresses in a source memory region into contiguous address in a destination region responsive to a rearrangement specified by a host processing unit of the data processing system. A description of the rearranged data is maintained in a metadata memory region. Rearranged data may be accessed by one or more host processing units. Write-back of data from the destination to the source region may be reduced by use of Bloom filter or the like.

Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.

Abstract: A data processing apparatus comprises signal receiving circuitry to receive a signal corresponding to a divide instruction that identifies a dividend x and a divisor d. Processing circuitry performs, in response to said divide instruction, a radix-N division algorithm to generate a result value q=x/d, where N is an integer power of 2 and greater than 1. Said division algorithm comprises a plurality of iterations, each of said plurality of iterations being performed by quotient digit calculation circuitry to determine a quotient value of that iteration q[i+1] based on a remainder value of a previous iteration rem[i]; and remainder calculation circuitry to determine a remainder value of that iteration rem[i+1] based on said quotient value of that iteration q[i+1] and said remainder value of said previous iteration rem[i]. Result calculation circuitry derives said result value q based on each quotient value selected by said digit selection circuitry for each of said plurality of iterations.

Abstract: A data processing apparatus (2) has processing circuitry (4) for executing first software (12) at a first privilege level EL1 and second software (10) at a second privilege level EL2 higher than the first privilege level. Attributes may be set by the first and second software (10, 12) to indicate whether execution of the data access instruction can be interrupted. For a predetermined type of data access instruction for which the second attribute set by the second software (10) specifies that the instruction can be interrupted, the instruction may be set as interruptable even if the first attribute set by the first software (12) specifies that the execution of the instruction cannot be interrupted.