Abstract: There is provided an issuer apparatus, translation apparatus and access apparatus for providing a secure mechanism for accessing memory. When the issuer requests an address translation for a block of memory, the translation apparatus provides a translated address and a signature. The signature contains the address and a nonce and is signed using a private key that is not known to the issuer. When the issuer accesses the translated address, it provides the signature. The nonce is updated each time the permissions of the block of memory change. Consequently, the signature can be checked for validity when an access request is made. If the nonce is old, then the access request is prohibited. The issuer cannot simply modify the signature because it cannot access the private key. Consequently, memory is kept secure.

Abstract: A method performed by an information processing apparatus is described. The method comprises: obtaining input data, parameterising a kernel that corresponds to a number of applications of a predetermined filter by a continuous variable associated with the number of applications of the predetermined filter, determining a derivative of the kernel applied to the input data with respect to the continuous variable, and outputting the derivative. An information processing apparatus configured to perform the method above is also described.

Abstract: A multiple-outer-product instruction specifies multiple first source vector operands, at least one second source vector operand and correlation information associated with the second source vector operand(s), each vector operand comprising multiple data elements and the correlation information indicating, for each data element of a given second source vector operand, a corresponding first source vector operand. In response to the multiple-outer-product instruction, instruction decoder circuitry (50) controls processing circuitry (60) to perform computations to implement outer product operations, the outer product operations comprising, for a given first source vector operand, performing an associated outer product of that first source vector operand with a subset of data elements of the second source vector operand(s).

Abstract: Disclosed is a graphics processor that comprises a plurality of processing cores and a cache that is operable to transfer data between the processing cores and a memory that the graphics processor has access to. Access logic is provided to control how memory accesses issued by the processing cores are distributed across the cache slices. The cache slice that is used for a memory access is determined using a function computed by the access logic based on one or more properties associated with the memory access, and the function can be changed over time to vary how memory accesses from the plurality of processing cores are distributed across the plural cache slices.

Abstract: When executing a tile-based graphics processing pipeline, one or more geometry processing stages of a sequence of one or more geometry processing stages of the graphics processing pipeline generate packets storing data for geometry to be processed. For each packet, it is determined whether to defer some geometry processing until a rendering stage. When it is determined to defer some of the geometry processing for a packet, an indication that further geometry processing should be performed for the packet at the rendering stage is associated with the packet. When it is not determined to defer geometry processing for a packet, all of the sequence of one or more geometry processing stages are performed for the packet before providing the packet to a binning stage.

Abstract: A read circuitry for memory includes a column read-out multiplexer (MUX) coupled to a set of columns of the memory, wherein the column read-out MUX receives a column select signal from a control circuit to output a corresponding column output from the set of columns; and a single sense amplifier coupled to receive the corresponding column output of the column read-out MUX.

Abstract: A fault detection scheme for a data processor that comprises a programmable execution unit operable to execute programs to perform processing operations, and in which when executing a program, the execution unit executes the program for respective execution threads, each execution thread corresponding to a respective work item. In order to detect faults, a set of two or more identical execution threads is generated. The identical execution threads when executed perform identical processing for the same work item and a result of the processing of the same work item can thus be compared to determine whether there is a fault associated with the data processor.

Abstract: Processing circuitry 16 performs a stack pointer switch validity checking operation associated with a switch of the stack pointer from an outgoing stack pointer value to an incoming stack pointer value. The validity checking operation comprises verifying whether an incoming data value obtained by memory access circuitry 26 in response to a memory access request specifying an address determined based on the incoming stack pointer value meets at least one stack cap value validity condition, including a condition that a predetermined portion of the incoming data value corresponds to a given page address indicative of a page of address space comprising the address determined based on the incoming stack pointer value. The at least one stack cap value validity condition is determined independent of whether a further portion of the incoming data value other than the predetermined portion corresponds to sub-page address bits of the address determined based on the incoming stack pointer value.

Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. A data structure is also built to allow entire primitives to be culled.

Abstract: A graphics processor is disclosed. A packet processing unit of the graphics processor processes an input packet of primitives by subjecting the input packet to one or more processing operations, and storing data produced by the one or more processing operations in local storage. The packet processing unit stores a corresponding output packet of primitives in memory by allocating an amount of memory space for storing the output packet based on an amount of data produced by the one or more processing operations stored in the local storage, and storing the output packet in the allocated memory space.

Abstract: A method of encoding (e.g. compressing) data is disclosed. The data comprises a sequence of values. It is encoded by delta-encoding the sequence of values to generate a sequence of delta values, and encoding each delta value as an offset into a lookup table of delta values, thereby generating a sequence of offsets. The sequence of offsets, or data representative thereof, is stored or output as encoded data.

Abstract: An apparatus has processing circuitry to perform single instruction, multiple data (SIMD) processing on an array with a plurality of data items and the processing circuitry supports the SIMD processing for a plurality of array sizes. The processing circuitry is able to select an array size with which to perform the SIMD processing based on SIMD processing configuration information. Diagnostic information collection circuitry is provided to collect diagnostic information about software executing on the processing circuitry and the diagnostic information collection circuitry filters collection of the diagnostic information based on the SIMD processing configuration information.

Abstract: A system and method for multiplying first and second matrices are provided. For the first matrix, a number of bit slice vectors for each row are generated based on the bit resolution, and a first bit slice tensor is generated based on the bit slice vectors for each row. For the second matrix, a number of bit slice vectors for each column are generated based on the bit resolution, and a second bit slice tensor is generated based on the bit slice vectors for each row. The first and second bit slice tensors are multiplied by a matrix multiply accelerator (MMA) to generate an output matrix.

Abstract: A method performed by a processor for permuting dimensions of a multi-dimensional tensor is described. The multi-dimensional tensor contains an array of tensor values in three or more dimensions that are stored in a first storage unit. The array of tensor values is transferred from the first storage unit to a second storage unit by reading tensor values from the first storage that are arrayed along a first dimension of the multi-dimensional tensor and writing the corresponding tensor values to the second storage in locations corresponding to a second dimension of the multi-dimensional tensor. The dimensions of the multi-dimensional tensor may be further permuted by a programmable engine within the processor.

Abstract: Execution circuitry executes, in response to an instruction referencing a given source register of a register file, a data processing operation on pre-processed operand data obtained after a pre-processing action has been performed using stored operand data from the given source register of the register file. A buffer separate from the register file stores pre-processed operand data corresponding to a subset of registers. Register reuse detection circuitry detects a register reuse opportunity for a subsequent instruction referencing a reused source register also referenced by a previous instruction for which pre-processed operand data corresponding to the reused source register was written to the buffer, when it is guaranteed that no intervening instruction will cause a write to the reused source register.

Abstract: For a predetermined class of load/store operations, load/store processing circuitry buffers store data of predetermined-class store operations in a predetermined-class store buffer, and controls store-to-load forwarding of store data from that buffer to predetermined-class load operations. A predetermined-class-load/store synchronization instruction controls the load/store processing circuitry to enforce that, for a hazarding younger non-predetermined-class load/store operation occurring after the predetermined-class-load/store synchronization instruction in program order and a hazarding older predetermined-class store operation occurring before the predetermined-class-load/store synchronization instruction in program order, for which address ranges overlap, the hazarding younger non-predetermined-class load/store operation observes a result of the hazarding older predetermined-class store operation.

Abstract: A data communication apparatus having a message receiver, and a message transmitter to transmit messages to the message receiver. The message transmitter being configured to partition a payload greater than a predetermined size into a set of plural successive messages each being no larger than the predetermined size and to associate one or more flags with respective ones of the set of plural successive messages, the one or more flags indicating an ordering of messages within a set of plural successive messages, and the message receiver having a buffer to buffer received messages of a set of plural successive messages to reassemble a payload represented by the given set of plural successive messages, and a detector to detect an expected ordering of the one or more flags with respect to receipt by the message receiver of messages of a given set of plural successive messages.

Abstract: Systems and methods of controlling a read operation and a write operation at a storage device storage device including: core circuitry including one or more bitcells, each bitcell accessible via a corresponding bitline and wordline; column selection circuitry to, responsive to a column select signal, select at least one bitcell via one or more bitlines; wordline selection circuitry to, responsive to a wordline select signal, select the at least one bitcell via one or more wordlines; control circuitry to, in a first mode of operation: provide a first wordline select signal to the wordline selection circuitry responsive to a first control signal; provide first and second column select signals to the column selection circuitry responsive to a second control signal, and where the first column select signal is to control a read operation and the second column select signal is to control a write operation.

Abstract: An apparatus comprises an instruction decoder to decode instructions; processing circuitry to perform data processing in response to decoding of the instructions by the instruction decoder; and at least one control register to specify instruction-function-selecting information. In response to a no-operation-compatible instruction, the instruction decoder is configured to control the processing circuitry to: treat the no-operation-compatible instruction as a no-operation instruction, when the instruction-function-selecting information specified by the at least one control register is in a first state; perform both a first operation and a second operation, when the instruction-function-selecting information specified by the at least one control register is in a second state; and perform the first operation but not the second operation, when the instruction-function-selecting information specified by the at least one control register is in a third state.

Abstract: An apparatus comprises processing circuitry comprising a plurality of execution units; issue circuitry to issue an instruction to be executed by the processing circuitry during a plurality of pipeline stages such that younger instructions are not permitted to be issued before older instructions and scheduling circuitry to schedule instructions for execution in a given cycle during the plurality of pipeline stages, such that the instruction is permitted to be executed in an order different to a program order in response to input operand data being available, by dynamically allocating which of the plurality of pipeline stages a given execution unit of the plurality of execution units is assigned to in the given cycle. In a configuration selectable for the given cycle, the scheduling circuitry causes the given execution unit of the plurality of execution units to be assigned to any pipeline stage of the plurality of pipeline stages.