Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.

Abstract: Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to process requests to execute instance of service functions in a service function chain. In one particular implementation, a request to execute an instance of a second service function in a service function change may be initiated prior to completion of an execution of an instance of a first service function in the service function chain.

Abstract: A mechanism for error containment in a data processing system includes receiving a transaction request at a gateway between a host and a device, allocating an entry for the request in a local request tracker of the gateway and sending a link request, to a port of the gateway. In response to an isolation trigger, the port is moved into isolation by completing in-process requests with entries in the tracker and locking the entries. On receiving a response to an in-process request while the port is in isolation, the response is dropped, the associated entry is unlocked, and allocation of the entry is enabled. A completion response is sent to the requester without dispatching a new link request to the port. When requests are completed, the system is quiesced, locked entries are unlocked, and the port is moved out of isolation.

Abstract: An apparatus comprises processing circuitry to issue store operations to store data to a data store and load operations to load data from the data store and a store buffer comprising entries to store entry information corresponding to store operations in advance of the store operations completing. Store buffer lookup circuitry is provided to lookup, in response to a load operation, whether the store buffer contains a corresponding entry corresponding to an older store operation for which target addresses of the load operation and the older store operation satisfy an address comparison condition. The store buffer lookup circuitry is configured to perform store-to-load forwarding in response to the load operation when the corresponding entry is a first type of store buffer entry satisfying a forwarding condition, and delay processing of the load operation when the corresponding entry is a second type of store buffer entry satisfying the forwarding condition.

Abstract: A data processor is disclosed in which groups of execution threads comprising a thread group can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. In response to an execution thread issuing circuit determining whether a portion of active threads of a first thread group and a portion of active threads of a second thread group use different execution lanes of the plurality of execution lanes, the execution thread issuing circuit issuing both the portion of active threads of a first thread group and a portion of active threads of a second thread group for execution. This can have the effect of increasing data processor efficiency, thereby increasing throughput and reducing latency.

Abstract: An apparatus has processing circuitry with support for transactional memory, and a cache hierarchy comprising at least two levels of cache. In response to a draining trigger event having potential to cause loss of state stored in at least one further level cache beyond a predetermined level cache in which speculative store data generated by a transaction is marked as speculative until the transaction is committed, draining circuitry performs a draining operation to scan a subset of the cache hierarchy to identify dirty cache lines and write data associated with the dirty cache lines to persistent memory. The subset of the cache hierarchy includes the at least one further level cache. In the draining operation, speculative store data marked as speculative in the predetermined level cache is prevented from being drained to the persistent memory.

Abstract: Various implementations described herein are related to a device having logic that operates in multiple voltage domains. The device may include a backside power network with rows of segmented supply rails coupled to the logic. The rows of segmented supply rails may include alternating rail breaks that define an interchanging directional supply of power to the logic in the multiple voltage domains.

Abstract: Methods and apparatus for performing a clipping operation comprised of a plurality of partial clip instructions based on a portion of a clip value. Wherein the partial clip instructions comprise decoding (120) a partial clip instruction using instruction decoding circuitry, and obtaining (110) at least a portion of input data associated with a register having a register size. In response to the decoded instruction the portion of the input data is clipped (130) based on the portion of the clip value; and a flag is set (140) indicating whether further clipping is required. The flag is set when an upper value of the portion of input data is equal to or exceeds the portion of the clip value.

Abstract: Provided is a data stream processor comprising a streamed data transceiver interface, a structure of processing units configurable to transform data received from a data source over the streamed data transceiver interface according to a specified output requirement, and a configuration unit operable in electronic communication with a data consumer to receive an output requirement and to configure the operation and linkage of a processing unit in the structure of processing units to transform input data to output data according to the specified output requirement; wherein the structure of processing units is further operable to provide the output data for output over the streamed data transceiver interface.

Abstract: Provided is a data stream processor comprising: a configurable compute unit comprising plural processing units each configured to receive at least one portion of input data and process the at least one portion of a repetitive arithmetical/logical operation on the data; an input memory unit in electronic communication with the configurable compute unit and configured to supply at least one portion of the input data to at least one of the plural processing units in the configurable compute unit; and at least one accumulator unit in electronic communication with the configurable compute unit and configured to receive at least two portions of processed data from the configurable compute unit and to output accumulated data; wherein each of the plural processing units is further configured to forward its processed data to a next processing unit and/or to an accumulator unit.

Abstract: A machine learning and inferencing system to generate a personalised activity plan comprises a trained world context knowledge base; a trained personal digital memory store; a goal engine to establish an activity goal; an activity decomposition engine to decompose an activity into a logically-consistent sub-activities connected by; a ponderation engine to assign value weights to potential sub-activities; a graph generation engine to generate a multi-layer weighted graph to train a model of personalised outcomes of the sub-activities according to the value weights; a scenario generation engine to analyze the network of logically-consistent potential sub-activities connected by paths to determine a selected scenario path to the activity goal according to at least the model of personalised user outcomes; a feedback engine to apply learning from the scenario generation engine to the world context knowledge base and/or the personal digital memory store; and an output channel to output a personalised activity plan

Abstract: A data processing system that comprises an encoder, and a communication system is disclosed. Compressed data produced by the encoder is decompressed to produce first decompressed data, and a first signature representative of the first decompressed data is generated. Compressed data that has been transferred by the communication system is decompressed to produce second decompressed data, and a second signature representative of the second decompressed data is generated. The first signature and the second signature are compared, and the comparison is used to determine whether an error has occurred.

Abstract: When performing rendering in a tile-based graphics processor that comprises plural rendering processors, different regions of the render output are allocated to different ones of the rendering processors for processing. The processing of the render output is tracked to determine when a portion of the render output that is still to be allocated to the rendering processors for processing falls below a threshold, and when it is determined that a portion of the render output that is still to be allocated to the rendering processors for processing falls below the threshold, smaller regions of the render output are thereafter allocated to the rendering processors for processing.

Abstract: Provided is a graphics processing unit comprising a texture unit, an execution unit, and a machine-learning neural network engine, all configured in a pipeline in electronic communication with an integrated cache memory; and a visual data processing engine comprising a configurable stencil processor integrated into the pipeline, in electronic communication with the integrated cache memory, and configured to execute repetitive image-to-image processing instructions on visual data fetched from the integrated cache memory; wherein a graphics processing unit scheduler is configured to provide a job control function for the visual data processing engine; and wherein the visual data processing engine is configured responsively to the graphics processing unit scheduler to operate in parallel with at least one of the texture unit, the execution unit, or the machine-learning neural network engine using a separate dataflow.

Abstract: Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, techniques to apply an image anti-aliasing operation to an image frame.

Abstract: An apparatus has tag checking circuitry responsive to a target address to: identify a guard tag stored in a memory system in association with a block of one or more memory locations, the block containing a target memory location identified by the target address, perform a tag check based on the guard tag and an address tag associated with the target address, and in response to detecting a mismatch in the tag check, perform an error response action. The apparatus also has tag mapping storage circuitry to store mapping information indicative of a mapping between guard tag values and corresponding address tag values. The tag checking circuitry remaps at least one of the guard tag and the address tag based on the mapping information stored by the tag mapping storage circuitry to generate a remapped tag for use in the tag check.

Abstract: There is provided a processing apparatus comprising decoder circuitry. The decoder circuitry is configured to generate control signals in response to an instruction. The processing apparatus further comprises processing circuitry which comprising a plurality of processing lanes. The processing circuitry is configured, in response to the control signals, to perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing for that processing lane is enabled. The processing apparatus further comprises control circuitry to monitor each processing lane of the plurality of processing lanes for each instruction of a plurality of instructions performed in the plurality of processing lanes and to modify the per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane meeting one or more predetermined conditions.

Abstract: A system for storing geometry data for use by a graphics processor when rendering a frame that represents a view of a scene using a ray tracing process. The system comprises a processing circuit that is configured to prepare a ray tracing acceleration data structure for use when rendering a frame that represents a view of a scene using a ray tracing process. Graphics primitives for an end point of the ray tracing acceleration data structure is sorted into groups of contiguous graphics primitives, and fewer instances of vertex data is stored for a graphics primitive that is shared by at least two graphics primitives of the group of contiguous graphics primitives than the number of graphics primitives in the group of contiguous graphics primitives that share the vertex.

Abstract: A method of image processing. The method comprises obtaining a set of image data, the set being associated with one or more parameters representative of one or more image capture characteristics for the set and comprising pixel intensity values representing image pixels having respective pixel locations in an image. The method comprises, for a given pixel intensity value in the set: determining an estimated noise value based on at least: the one or more parameters associated with the set, and a representative intensity value derived from one or more pixel intensity values in the set. The method comprises associating the estimated noise value with the given pixel intensity value.

Abstract: There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.