Abstract: In one implementation, a circuit includes: a comparator; a shift register chain coupled to the comparator; and one or more converters coupled to respective shift registers of the shift register chain, wherein the one or more converters are configured to convert a source of current from a first voltage to a second voltage, and wherein the circuit is configured to selectively transmit an output signal to the one or more converters. In one implementation, the circuit is configured to selectively control modulation for the one or more converters.

Abstract: A system and method for multiplying matrices are provided. The system includes a processor coupled to a memory and a matrix multiply accelerator (MMA) coupled to the processor. The MMA is configured to multiply, based on a bitmap, a compressed first matrix and a second matrix to generate an output matrix including, for each element i,j of the output matrix, a calculation of a dot product of an ith row of the compressed first matrix and a jth column of the second matrix based on the bitmap. Or, the MMA is configured to multiply, based on the bitmap, the second matrix and the compressed first matrix and to generate the output matrix including, for each element i,j of the output matrix, a calculation of a dot product of an ith row of the second matrix and a jth column of the compressed first matrix based on the bitmap.

Abstract: A method of compressing kernels comprising detecting a plurality of replicated kernels. The plurality of replicated kernels comprise kernels. The method also comprises generating a composite kernel from the replicated kernels. The composite kernel comprises kernel data and meta data indicative of the rotations applied to the composite kernel data. The method also comprises storing a composite kernel.

Abstract: A method of operating a cache system is disclosed. When it is desired to evict a cache entry from the cache, a cache entry to evict from the cache is selected using an age of any compression block that the cache is caching data for, and the selected cache entry is evicted from the cache.

Abstract: An apparatus comprises counter tree circuitry configured to store, in a first node of a counter tree, a representation of a parent counter value and in a second node of the counter tree, wherein the second node is a child node of the first node, an encrypted representation of two or more counter values. The encryption operation for forming the encrypted representation of the two or more counter values takes as an input the parent counter value. The apparatus also comprises integrity checking circuitry to check the integrity of an item of data retrieved from memory based on a comparison between a stored authentication code and a generated authentication code generated based on the item of data and a decrypted counter value determined from an encrypted representation of a counter value retrieved from the second node, decrypted using a parent counter value retrieved from the first node.

Abstract: An apparatus comprises counter integrity tree circuitry to maintain a counter integrity tree having a plurality of nodes. The counter integrity tree circuitry is configured to store, in a first node of the counter integrity tree, an encrypted representation of two or more non-repeating counters and in a second, parent, node, an indication of a function value equal to a non-repeating function of the two or more non-repeating counters of the first node. The apparatus comprises integrity checking circuitry configured to check the integrity of the first node using the function value retrieved from the second node.

Abstract: Disclose herein is a method of operating a graphics processor when performing ray tracing. During a traversal of the nodes of an acceleration data structure, when a parent node that encompasses multiple child node volumes is encountered, a group of rays is tested against the child node volumes to determine which child nodes may need to be visited next. Rather than simply visiting the nodes based on the order in which they are found to be interested, the node traversal order is instead determined based on the group of rays.

Abstract: A method of generating a digital signature. The method comprises calculating a first random number and, based on second and third random numbers, first and second modified versions thereof. A curve point on an elliptic curve is determined based on a base point and the first modified version. A first signature part is calculated based on the curve point. Based on the second and third random numbers, the modified versions of the first random number, data to be signed, the first signature part, and a private key, a second signature part and a check value for the second signature part are calculated. The second signature part is compared with the check value for the second signature part and, responsive to the check value for the second signature part matching the second signature part, a cryptographic signature is output comprising the first signature part and the second signature part.

Abstract: A method and apparatus for performing refactored multiply-and-accumulate operations is provided. A summing array includes a plurality of non-volatile memory elements arranged in columns. Each non-volatile memory element in the summing array is programmed to a high resistance state or a low resistance state based on weights of a neural network. The summing array is configured to generate a summed signal for each column based, at least in part, on a plurality of input signals. A multiplying array is coupled to the summing array, and includes a plurality of non-volatile memory elements. Each non-volatile memory element in the multiplying array is programmed to a different conductance level based on the weights of the neural network. The multiplying array is configured to generate an output signal based, at least in part, on the summed signals from the summing array.

Abstract: Various implementations described herein are related to a device having a level shifter that receives an input signal and reference voltages and provides level-shifted input signals based on the reference voltages. The device may have a pre-driver that receives the level-shifted input signals and reference voltages and provides gate voltages based on the reference voltages. The device may have a gate stabilizer that receives the reference voltages and provides a stabilized reference voltage based on the reference voltages. The device may have an output driver that receives the reference voltages, receives the gate voltages, receives the stabilized reference voltage and provides an output pad voltage to an input-output pad based on the reference voltages, the gate voltages and the stabilized reference voltage.

Abstract: A method for adjusting an exposure level of an image sensor. The method comprises receiving intensity values of a current image captured by the image sensor, the image sensor having an initial exposure level when the current image is captured. The method comprises determining an intensity status based on comparing at least one characteristic of at least the current intensity values to one or more criteria. The method comprises selecting an exposure convergence mode, from a plurality of exposure convergence modes, based on the intensity status. The method comprises calculating, based on the current intensity values and the exposure convergence mode, a new exposure level for use by the image sensor in capturing a subsequent image.

Abstract: A context-information-dependent instruction causes a context-information-dependent operation to be performed based on specified context information indicative of a specified execution context. A context information translation cache 10 stores context information translation entries each specifying untranslated context information and translated context information. Lookup circuitry 14 performs a lookup of the context information translation cache based on the specified context information, to identify whether the context information translation cache includes a matching context information translation entry which is valid and which specifies untranslated context information corresponding to the specified context information. When the matching context information translation entry is identified, the context-information-dependent operation is performed based on the translated context information specified by the matching context information translation entry.

Abstract: A data processing apparatus is provided that includes bimodal control flow prediction circuitry for performing a prediction of whether a conditional control flow instruction will be taken. Storage circuitry stores, in association with the control flow instruction, a stored state of the data processing apparatus and reversal circuitry reverses the prediction in dependence on the stored state of the data processing apparatus corresponding with a current state of the data processing apparatus when execution of the control flow instruction is to be performed.

Abstract: A data processing apparatus is provided, that includes communication configured for receiving, from an origin Peripheral Component Interconnect Express (PCIe) device, a translated PCIe packet comprising a destination field that comprises a physical address of a destination PCIe device. Permission circuitry transmits a permission check packet, separate to the translated PCIe packet, to a root port to determine whether the origin PCIe device has permission to access the destination PCIe device. Buffer circuitry stores the translated PCIe packet until a response to the permission check packet is received.

Abstract: Apparatuses, methods, and programs for performing a translation of a virtual address of a memory access to a physical address associated with a memory location to be accessed are disclosed. A page table descriptor is accessed when performing the translation, which comprises translation parameters for the translation. The descriptor further comprises an integrity check value, wherein the integrity check value is dependent on the translation parameters.

Abstract: Circuitry comprises memory address translation circuitry to access memory circuitry storing translation information defining memory address translations from input memory addresses to respective output memory addresses; in which the translation information stored by the memory circuitry comprises a hierarchy of page table levels from a highest page table level to a lowest page table level, each page table level having one or more level tables each comprising two or more entries, in which an entry of a level table at a page table level other than a last page table level of the hierarchy points to a level table at a next lower page table level in the hierarchy; the memory address translation circuitry being configured to select an entry of a level table at each page table level according to a selection value, the selection value being dependent upon a portion, applicable to that page table level, of a given input memory address; in which the memory circuitry is configured to store entries as groups of entries,

Abstract: A cache is provided having a plurality of entries for storing data. In response to a given access request, lookup circuitry performs a lookup operation in the cache to determine whether one of the entries in the cache is allocated to store data associated with the memory address indicated by the given access request, with a hit indication or a miss indication being generated dependent on the outcome of that lookup operation. During a single lookup period, the lookup circuitry is configured to perform lookup operations in parallel for up to N access requests. In addition, allocation circuitry is provided that is able to determine, during the single lookup period, at least N candidate entries for allocation from amongst the plurality of entries, and to cause one of the candidate entries to be allocated for each of the up to N access requests for which the lookup circuitry generates a miss indication.

Abstract: A data processing apparatus includes receive circuitry that receives an indication of a trigger block of instructions.

Abstract: Data processing apparatuses, methods of data processing, complementary instructions and programs related to ring buffer administration are disclosed. An enqueuing operation performs an atomic compare-and-swap oper-ation to store a first processed data item indication to an enqueuing-target slot in the ring buffer contingent on an in-order marker not being present there and, when successful, determines that a ready-to-dequeue condition is true for the first processed data item indication. A dequeuing operation, when the ready-to-de-queue condition for a dequeuing-target slot is true, comprises writing a null data item to the dequeuing-target slot and, when dequeuing in-order, further comprises, dependent on whether a next contiguous slot has null content, determining a retirement condition and, when the retirement condition is true, performing a retirement process on the next contiguous slot comprising making the next con-tiguous slot available to a subsequent enqueuing operation.

Abstract: A data processing apparatus is provided that includes storage circuitry to store a plurality of interconnected instructions. Analysis circuitry analyses the instructions to determine a degree of uniqueness of profile measurements of a control flow path fragments within the instructions.