Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

Abstract: An on-chip memory is provided. The memory includes wordline sections, input/output (I/O) circuitry, and control circuitry. Each wordline section includes a number of wordlines, and each wordline section is coupled to a different wordline control circuitry. The control circuitry is configured to, in response to receiving an access request including an address, decode the address including determine, based on the address, an associated wordline, and determine, based on the associated wordline, an associated wordline section. The control circuitry is further configured to apply power to wordline control circuitry coupled to the associated wordline section, and access the address.

Abstract: A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.

Abstract: Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The device may include multiple wordlines that are coupled to the multiple transistors. Also, one or more wordlines may be formed with frontside metal, and one or more other wordlines may be formed with buried metal.

Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.

Abstract: Aspects of the present disclosure relate to an apparatus comprising prediction circuitry having a plurality of hierarchical prediction units to perform respective hierarchical predictions of instructions for execution, wherein predictions higher in the hierarchy have a higher expected accuracy than predictions lower in the hierarchy. Responsive to a given prediction higher in the hierarchy being different to a corresponding prediction lower in the hierarchy, the corresponding prediction lower in the hierarchy is corrected. A prediction correction metric determination unit determines a prediction correction metric indicative of an incidence of uncorrected predictions performed by the prediction circuitry. Fetch circuitry fetches instructions predicted by at least one of said plurality of hierarchical predictions, and delays said fetching based on the prediction correction metric indicating an incidence of uncorrected predictions below a threshold.

Abstract: Various implementations described herein are directed to a device with a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first cache memory with first interconnect logic disposed in the first layer. The device may have a second cache memory with second interconnect logic disposed in the second layer, wherein the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer.

Abstract: An apparatus comprises an interconnect providing communication paths between agents coupled to the interconnect. A coordination agent is provided which performs an operation requiring sending a request to each of a plurality of target agents, and receiving a response from each of the target agents, the operation being unable to complete until the response has been received from each of the target agents. Storage circuitry is provided which is accessible to the coordination agent and configured to store, for each agent that the coordination agent may communicate with via the interconnect, a latency indication for communication between that agent and the coordination agent. The coordination agent is configured, prior to performing the operation, to determine a sending order in which to send the request to each of the target agents, the sending order being determined in dependence on the latency indication for each of the target agents.

Abstract: Disclosed is a method of handling thread termination events within a graphics processor when a group of plural execution lanes are executing in a co-operative state. When a group of lanes is in the co-operative state, in response to the graphics processor encountering an event that means that a subset of one or more execution threads associated with the group of execution lanes in the co-operative state should be terminated: it is determined whether a condition to immediately terminate the subset of one or more execution threads is met. When the condition is not met, the group of execution lanes continue their execution in the co-operative state, but a record is stored to track that the threads in the subset of one or more execution threads should subsequently be terminated.

Abstract: In a particular implementation, a method includes: identifying prospective zones for placement of one or more vertical interconnect access pads (via) in a cell, where each of the prospective zones comprises one or more poly pitches; and assigning a first color for a particular poly pitch of a first identified zone of the identified prospective zones or assigning a first color sequence for one or more sections of the first identified zone.

Abstract: A method comprising the steps of obtaining image data captured at an image sensor using a focus configuration. A distance is determined for one or more objects in the image data, based on the focus configuration and a sharpness characteristic of the image data of the object. A depth map is then generated based on the determined distance.

Abstract: When load requests are generated to support data processing operations, the load requests are buffered in pending load buffer circuitry prior to being carried out. Coalescing circuitry determines for a first load request whether a set of one or more subsequent load requests buffered in the pending load buffer circuitry satisfies an address proximity condition. The address proximity condition is satisfied when all data items identified by the set of one or more subsequent load requests are comprised within a series of data items which will be retrieved from the memory system in response to the first load request. When the address proximity condition is satisfied, forwarding of the set of one or more subsequent load requests is suppressed.

Abstract: Various implementations described herein refer to an integrated circuit having multiple stages including a first stage, a second stage, and a third stage. The first stage has first logic structures coupled in series, and the first logic structures are activated with multiple signals. The second stage has second logic structures coupled in parallel, and the second logic structures are activated with the multiple signals. The third stage has a first input, a second input, and an output. The first input is coupled to the first stage, the second input is coupled to the second stage, and the output provides an output signal based on the multiple signals.

Abstract: Address translation circuitry (20) converts virtual addresses into physical addresses with reference to intermediate level and final level page tables. Final level descriptors within final level page tables identify address translation data for an associated region of memory. Intermediate level descriptors within intermediate level page tables identify intermediate address translation data used to identify an associated page table at a next level of the page tables. Page table update circuitry (35) maintains state information within each final and intermediate level descriptor, and updates the state information from a clean state to a dirty state: in the final level descriptors to indicate that a modification of content of the associated memory region is permitted; in the intermediate level descriptors to indicate occurrence of an update from the clean state to the dirty state within the state information of any final level descriptors that are accessed via that intermediate level descriptor.

Abstract: An apparatus and method of converting data into an Enhanced Block Floating Point (EBFP) format with a shared exponent is provided. The EBFP format enables data within a wide range of values to be stored using a reduced number of bits compared with conventional floating-point or fixed-point formats. The data to be converted may be in any other format, such as fixed-point, floating-point, block floating-point or EBFP.

Abstract: Systems, apparatuses and methods suitable for optimizing synchronization mechanisms for multi-core processors are provided. The synchronizing mechanisms may be optimized by receiving a command stream which comprises a plurality of commands including one or more wait commands, wherein each wait command has an associated state and one or more associated conditions; sequentially processing each command in the command stream until a wait command is reached; checking the state associated with the wait command to be processed, wherein if said state is a blocking state, further processing of commands in the command stream is paused until each of said wait command's associated conditions are met, and wherein if said state is a non-blocking state, the next command in the command stream is retrieved and processed.

Abstract: Various implementations described herein are related to a device having sensing circuitry that receives an input signal and provides an output signal based on sensing a resistance differential between multiple shield resistors or based on sensing a change in voltage across a shield wire of a shield wiring network. The device includes comparing circuitry that receives the output signal and provides an alarm signal based on detecting a tampering event associated with the resistance differential or the change in voltage.

Abstract: Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The multiple transistors may include multiple P-type transistors that are arranged in a P-over-P stack configuration, and the multiple transistors may include multiple N-type transistors that are arranged in an N-over-N stack configuration.

Abstract: A method to operate a head-mountable processing system, is provided. The head-mountable processing system comprising generating one or more control signals based upon a visual motion of a sequence of images for display by the head-mountable processing system, and transmitting the generated one or more control signals to a plurality of transducers to stimulate a wearer's vestibular system.

Abstract: A data processor is disclosed in which groups of execution threads comprising a thread group can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. In response to an execution thread issuing circuit determining whether a portion of active threads of a first thread group and a portion of active threads of a second thread group use different execution lanes of the plurality of execution lanes, the execution thread issuing circuit issuing both the portion of active threads of a first thread group and a portion of active threads of a second thread group for execution. This can have the effect of increasing data processor efficiency, thereby increasing throughput and reducing latency.