Abstract: Various implementations described herein are directed to device. The device may include a first tier having a processor and a first cache memory that are coupled together via control logic to operate as a computing architecture. The device may include a second tier having a second cache memory that is coupled to the first cache memory. Also, the first tier and the second tier may be integrated together with the computing architecture to operate as a stackable cache memory architecture.

Abstract: An apparatus has memory management circuitry to control access to a memory system based on access control information defined in table entries of a table structure comprising at least two levels of access control table. Table accessing circuitry accesses the table structure to obtain the access control information corresponding to a target address. For a given access control table at a given level of the table structure other than a starting level, the table accessing circuitry selects a selected table entry of the given access control table corresponding to the target address, based on an offset portion of the target address. A size of the offset portion is selected based on a variable nesting control parameter specified in a table entry of a higher-level access control table at a higher level of the table structure than the given access control table.

Abstract: There is provided a method and apparatus to generate audio data for a user, the apparatus comprising: an input device to receive one or more inputs derived from an environment in which the user is located; and a processor configured to obtain an acoustic profile for the environment based on or in response to the one or more inputs, synthesize audio data having audio characteristics corresponding to a sound source in the environment in accordance with the acoustic profile, and output the synthesized audio data for use by the user.

Abstract: A processor arranged to compress neural network activation data comprising an input module for obtaining neural network activation data. The processor also comprises a block creation module arranged to split the neural network activation data into a plurality of blocks; and a metadata generation module for generating metadata associated with at least one of the plurality of blocks. Based on the metadata generated a selection module selects a compression scheme for each of the plurality of blocks, and a compression module for applying the selected compression scheme to the corresponding block to produce compressed neural network activation data. An output module is also provided for outputting the compressed neural network activation data.

Abstract: Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.

Abstract: Broadly speaking, the present techniques relate to a computer implemented method for establishing a secure communication session between a client device and a server, the method performed at the client device comprising: obtaining a security object comprising at least one security credential and server connection data for multiple connection options to a first server, wherein the security credential is to be used for each of the multiple connection options; generating, a first server security universal resource identifier (URI), the first Server Security URI comprising server contact information for the first server and a first security binding selected from the server connection data; communicating with the first server using the first Server Security URI and the at least one security credential to establish a secure communication session between the client device and the first server.

Abstract: An image processing system for an extended reality, XR, device comprising an eye-tracking subsystem, for determining a focus region of the eye, and a processor. The processor is configured to process application data to render image content for an application for display on the XR device, and obtain metadata indicating that a virtual object is to be generated as a hologram as part of the image content for display. Based on a determination that the virtual object belongs to a predetermined class of objects and is to be displayed in the focus region, the processor performs, using a neural network corresponding to the predetermined class of objects, foveated processing of the image content, including at least part of the hologram, such that relatively high-quality image content is generated for display in the focus region and relatively low-quality image content is generated for display outside the focus region.

Abstract: In response to a replicate partition instruction specifying partition information defining positions of a plurality of variable size partitions within a result vector, an instruction decoder (20) controls the processing circuitry (80) to generate a result vector in which each partition having more than one data element comprises data values or element indices of a sequence of data elements of a source vector starting or ending at a selected data element position. This instruction can be useful for accelerating processing of data structures smaller than the vector length.

Abstract: An apparatus has processing circuitry, load tracking circuitry and load prediction circuitry to determine a prediction for a predicted load operation. It is determined whether the prediction is correct, and whether the tracking information indicates that, for a given younger load operation issued before it is known whether the prediction is correct, there is a risk of second target data associated with that given load operation having changed after having been loaded. Independent of whether the addresses of the predicted load operation and younger load operation correspond, at least the given load operation is re-processed when the prediction is correct and the tracking information indicates there is a risk of the second target data having changes after being loaded. This protects against ordering violations.

Abstract: A device has a content processing component operable in a content processing state, and a content transducer configured to provide augmented reality data to a user of the device based on an output of the content processing component. The device has a receiver operable to receive captured data indicative of a health condition of a user of the device. The device has a processor configured to process the captured data to identify a trigger indicative of a possible change in the health condition of a user, and in response to the trigger, modify the content processing state of the content processing component such that at least one characteristic of the augmented reality data is modified.

Abstract: Disclosed subject matter relates generally to graphics processing, and relates more particularly to processing graphics vertex content.

Abstract: A data processing apparatus provides predictions for hard to predict instructions. Prediction circuitry generates predictions relating to predictable instructions in a stream and stores, with respect to each of the predictable instructions, a reference to a set of monitored instructions in the stream to be used for generating predictions for the predictable instructions. Processing circuitry executes the predictable instructions in the stream using the predictions. A given correlation parameter is stored between a given predictable instruction in the stream and a subset of the set of monitored instructions of the given predictable instruction to assist in generating the predictions. If the given correlation parameter is currently stored, the prediction circuitry generates a given prediction relating to the given predictable instruction based on the subset of the set of monitored instructions.

Abstract: Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

Abstract: There is provided a graphics primitive assembly circuit comprising an early primitive assembly data generator operable to supply primitive input to a shader and a buffer operable to store early primitive assembly data during operation of the shader and to supply the early primitive assembly data to a late primitive assembly circuit element responsive to completion of operation of the shader. The circuit may also include a compressor that compresses the early primitive assembly data to reduce the amount of storage taken up by the buffer and the bandwidth required to transfer the early primitive assembly data.

Abstract: An apparatus and method are provided for storing a plurality of translation entries in a cache, each translation entry corresponding to one of a plurality of page table entries and defining a translation between a first address and a second address, and encoding control information indicative of an attribute of each page table entry; returning, in response to a lookup querying a first lookup address, a corresponding second address when the first lookup address corresponds to one of the plurality of translation entries stored in the cache; modifying at least some of the control information in response to notification of a modification of the attribute in a page table entry; and retaining in the cache at least one translation entry corresponding to the page table entry for use in a subsequent address lookup querying a corresponding first lookup address in response to the notification of the modification of the attribute in the page table entry.

Abstract: A type of translation lookaside buffer (TLB) invalidation instruction is described which specifically targets a first type of TLB which stores combined stage-1-and-2 entries which depend on both stage 1 translation data and the stage 2 translation data, and which is configured to ignore a TLB invalidation command which invalidates based on a first set of one or more invalidation conditions including an address-based invalidation condition depending on matching of intermediate address. A second type of TLB other than the first type ignores the invalidation command triggered by the first type of TLB invalidation instruction. This approach helps to limit the performance impact of stage 2 invalidations in systems supporting a combined stage-1-and-2 TLB which cannot invalidate by intermediate address.

Abstract: An apparatus and method are provided for receiving a request from a plurality of processing units, where multiple of those processing units have associated cache storage. A snoop unit is used to implement a cache coherency protocol when a request is received that identifies a cacheable memory address. The snoop unit has snoop filter storage comprising a plurality of snoop filter tables organized in a hierarchical arrangement. The snoop filter tables comprise a primary snoop filter table at a highest level in the hierarchy, and each snoop filter table at a lower level in the hierarchy forms a backup snoop filter table for an adjacent snoop filter table at a higher level in the hierarchy. Each snoop filter table is arranged as a multi-way set associative storage structure, and each backup snoop filter table has a different number of sets than are provided in the adjacent snoop filter table.

Abstract: The present disclosure advantageously provides a method and system for transferring data over a chip-to-chip interconnect (CCI). At a request node of a coherent interconnect (CHI) of a first chip, receiving at least one peripheral component interface express (PCIe) transaction from a PCIe master device, the PCIe transaction including a stream identifier; selecting a CCI port of the CHI of the first chip based on the stream identifier of the PCIe transaction; and sending the PCIe transaction to the selected CCI port.

Abstract: An apparatus comprises at least one processor to execute software processes, a memory system to store data for access by the at least one processor, and checkpointing circuitry to trigger saving, to the memory system, of checkpoints of context state associated with at least one software process executed by the at least one processor. The saving of checkpoints is a background process performed by the checkpointing circuitry in the background of execution of the software processes by the at least one processor.

Abstract: Circuitry comprises memory access circuitry to control memory access by mapping virtual memory addresses in a virtual memory address space to physical memory addresses in a physical memory address space, the memory access circuitry being configured to provide a sparse mapping in which a mapped subset of the virtual memory address space is mapped to physical memory while an unmapped subset of the virtual memory address space is unmapped, the memory access circuitry being configured to discard write operations to virtual memory addresses in the unmapped subset of the virtual memory address space and processing circuitry to execute program code defining a processing operation to generate processed data and to store the processed data in a memory region of the virtual memory address space applicable to that processing operation; detector circuitry to detect whether the memory region is entirely within the unmapped subset of the virtual memory address space.