Abstract: An embedded memory device having improved BISR capabilities is provided. The embedded memory device includes an internal clock signal for use in accessing a memory array having access to redundant memory cells during normal operation, and a stress clock signal, wherein each pulse of the stress clock signal is of a shorter duration than each pulse of the internal clock signal. Further included are a built-in self-test circuit that performs a built-in self-test using the stress clock signal, and a register that stores defective memory addresses detected by the built-in self-test circuit. Redundant control logic is also included that redirects memory access operations to the defective memory addresses to redundant memory cells.

Abstract: A column redundancy circuitry and a method for implementing the same are provided. One exemplary method provides routing for an access request addressed to a defective cell. The method includes providing a redundant column within a memory circuit, the redundant column in communication with a sense amplifier. Next, a defective cell of a memory circuit is located and the address is programmed. An access request is then processed, the access request containing the address of the defective cell Finally, the access request is routed to the redundant column through enable circuitry. Some notable advantages include the conservation of surface area of the memory circuit induced by locating the redundant column within the memory circuit. The externalization of the fuse box, Built In Self Repair region and the logic circuitry from the memory core also provide increased flexibility.

Abstract: In an environment wherein a microprocessor can operate at several different voltage levels depending upon the instantaneous throughput of the microprocessor, a memory and memory adjustment circuit that permits operating the memory at a plurality of voltages in response to the microprocessor is disclosed. The memory and memory adjustment circuit sense the instantaneous operating voltage of the microprocessor and adjust the operating voltage of the memory in response thereto. The memory adjustment circuit more particularly increases or decreases the memory's bitline sense interval in response respectively to a decrease or increase in the memory's operating voltage.

Abstract: A method and apparatus for improving the manufacturability of Integrated Circuits (ICs) formed on semiconductor dies is described. A plurality of different designs for some or all of the standard cells are made available to the circuit designer. Each different design may address a different problem associated with different manufacturing processes or a different design related yield limiter. Each of the design variants is characterized indicating its relative ease of manufacture, or it's yield sensitivity to certain IC design factors. The designer, typically with assistance from computer aided tools, can then select the standard cell variant for each of the cell used in the IC design that best addresses his or her design constraints. In other embodiments, variant versions of I/O cells and memory cells could also be created and made available to the designer in a similar fashion.

Abstract: A method of designing a memory device that has substantially reduced bitline voltage offsets is provided. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a core cell having a bitline and a complementary bitline, and designing a flipped core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a core cell followed by a flipped core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the core cell is coupled with the flipped complementary bitline of the flipped core cell, and the complementary bitline of the core cell is coupled to the flipped bitline of the flipped core cell.

Abstract: A method for reducing leakage currents in integrated circuits and the integrated circuits with reduced leakage currents that result from this method are disclosed. The present invention determines which transistors in a standard logic cell (also known as a standard cell) are not critical with respect to the ultimate speed of operation of the standard logic cell. After determining which transistors do not critically impact the speed of the standard logic cell's operation, these designated transistors are designed with either lengthened channels or their channels are implanted. Both circuit design techniques will increase the threshold voltage (VT) of the transistors and thereby reduce their leakage current. Standard cells with high VT transistors in their non-critical circuit pathways exhibit reduced leakage currents when compared with known logic cells.

Abstract: A method and circuit for reducing power consumption during write operations in a RAM are disclosed. In A RAM comprised of a plurality of memory cells, the bit lines that are coupled to each memory cell in the RAM and used to read and write data into the cell are coupled through charge share control circuitry to a charge sharing line. During write operations, the bit line that will receive a zero value is coupled to the charge share line before data is written to the cell. The charge sharing line equalizes the charge on the selected bit line and the charge share line and reduces the voltage differential that must be swung to write data into the cell.

Abstract: An invention is disclosed for protecting an input buffer. A current from a p-supply to an input buffer is lowered when an input voltage to the input buffer is tolerant HIGH. The p-supply being a VDD voltage supplied to a p-channel transistor in the input buffer. In addition, the p-supply is set to a particular voltage when the input voltage to the input buffer is LOW, the particular voltage being at a specific value such that input transistors within the input buffer do not experience overstress voltages. Optionally, p-supply can be prevented from supplying current to the input buffer when an input voltage to the input buffer is tolerant HIGH.

Abstract: An invention is provided for a feed forward circuit that reduces delay through an inverting circuit. The feed forward circuit includes an inverter having an input and an output, and an inverting circuit having an input and an output. The input of the inverting circuit is coupled to the output of the inverter. A feed forward transistor having a gate coupled to the input of the inverter and a terminal coupled to the output of the inverting circuit also is included. In operation the feed forward transistor decreases the amount of time required for the output of the inverting circuit to change state. In sum, the invention reduces the delay when the inverting circuit transitions to a high state, without affecting the timing of the transition to a low state.

Abstract: A memory device design is provided. The memory device includes a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The memory device further includes a core cell having a bitline and a complementary bitline, and a flipped core cell that has a flipped bitline and a flipped complementary bitline. The multiple pairs of the global bitline and the global complementary bitline have a plurality of core cells that are defined by alternating ones of the core cell and the flipped core.

Abstract: A Static Random Access Memory (SRAM) dual port memory with an improved core cell design having internally matched capacitances and decreased bit line capacitance is disclosed. The core cell is fabricated on a substrate divided into three approximately equal columns of different substrate materials. In a preferred embodiment, the memory cell is fabricated on a central p-type column that in turn is sandwiched between two n-type columns. The three-column substrate architecture permits reduced bit line height, with an accompanying reduction in bit line capacitance, which increases the speed at which the core cell can operate. The architecture also permits separating the core cell's bitline and complement bitline, reducing capacitive coupling between these lines and increasing the core cell's operating speed. The architecture further permits better matching of internal node capacitances.

Abstract: A method and apparatus for improving the manufacturability of Integrated Circuits (ICs) formed on semiconductor dies is described. A plurality of different designs for some or all of the standard cells are made available to the circuit designer. Each different design may address a different problem associated with different manufacturing processes or a different design related yield limiter. Each of the design variants is characterized indicating its relative ease of manufacture, or it's yield sensitivity to certain IC design factors. The designer, typically with assistance from computer aided tools, can then select the standard cell variant for each of the cell used in the IC design that best addresses his or her design constraints. In other embodiments, variant versions of I/O cells and memory cells could also be created and made available to the designer in a similar fashion.

Abstract: An invention is provided for reducing subthreshold current in memory core cells. A memory array having a plurality of memory core cells is provided. Each memory core cell in the memory array is selectable using a word line. A selected word line addressing a particular memory core cell is charged to a positive voltage. In addition, unselected wordlines of the memory array are charged to a negative voltage. In this manner, subthreshold current associated with unselected memory core cells is reduced.

Abstract: A method for testing a circuit is provided. The method includes providing a normal internal clock signal for use in accessing functional logic, where the functional logic has access to redundant functional logic during normal operation. The method then applies a stress clock signal to the functional logic, and each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. Based on the applied stress clock signal, the method identifies logic elements of the functional logic that fail to operate as intended.

Abstract: An invention is disclosed for protecting an input buffer. A current from a p-supply to an input buffer is lowered when an input voltage to the input buffer is tolerant HIGH. The p-supply being a VDD voltage supplied to a p-channel transistor in the input buffer. In addition, the p-supply is set to a particular voltage when the input voltage to the input buffer is LOW, the particular voltage being at a specific value such that input transistors within the input buffer do not experience overstress voltages. Optionally, p-supply can be prevented from supplying current to the input buffer when an input voltage to the input buffer is tolerant HIGH.

Abstract: The invention provides overlapping row decode in a multiport memory. Overlapping row decode includes predecode wires positioned on a first metallization layer and configured to address wordline drivers of a first port. A second plurality of predecode wires is located on a third metallization layer and configured to address wordline drivers of a second port. The overlapping row decode includes a plurality of wordline connections that are formed on a second metallization layer between the first metallization layer and the third metallization layer. The wordline connections include a first and second portion. The first portion communicates with the first plurality of predecode wires and the wordline drivers of the first port. The second portion communicates with the second plurality of predecode wires and the wordline drivers of the second port.

Abstract: A method and circuit for reducing power consumption during write operations in a RAM are disclosed. In A RAM comprised of a plurality of memory cells, the bit lines that are coupled to each memory cell in the RAM and used to read and write data into the cell are coupled through charge share control circuitry to a charge sharing line. During write operations, the bit line that will receive a zero value is coupled to the charge share line before data is written to the cell. The charge sharing line equalizes the charge on the selected bit line and the charge share line and reduces the voltage differential that must be swung to write data into the cell.

Abstract: A method for reducing leakage currents in integrated circuits and the integrated circuits with reduced leakage currents that result from this method are disclosed. The present invention determines which transistors in a standard logic cell (also known as a standard cell) are not critical with respect to the ultimate speed of operation of the standard logic cell. After determining which transistors do not critically impact the speed of the standard logic cell's operation, these designated transistors are designed with either lengthened channels or their channels are implanted. Both circuit design techniques will increase the threshold voltage (VT) of the transistors and thereby reduce their leakage current. Standard cells with high VT transistors in their non-critical circuit pathways exhibit reduced leakage currents when compared with known logic cells.

Abstract: An invention for self-timing in a memory device is provided. The self-timing system includes a dummy global wordline signal, which is configured to follow a global timing pulse for a memory device. In addition, a row of at least one non-timing memory banks is included. Each non-timing memory bank includes a model row in electrical communication with the dummy global wordline signal. Each model row is comprised of a plurality of load cells. The self-timing system further includes a timing memory bank having a global timing column. The global timing column is comprised of a plurality of load cells that are coupled via at least one bitline. In operation, the global timing column responds to the dummy global wordline signal to provide a self-timing reset signal for the memory device. In this manner, the self-timing reset signal is provided to each active memory bank in the row of memory banks.

Abstract: An invention is provided for an overlapping row decode in a multiport memory. The overlapping row decode includes a first plurality of predecode wires positioned on a first metalization layer. The first plurality of predecode wires is configured to address wordline drivers of a first port. In addition, a second plurality of predecode wires is located on a third metalization layer above the first metalization layer. The second plurality of predecode wires is configured to address wordline drivers of a second port. The overlapping row decode further includes a plurality of wordline connections that are formed on a second metalization layer between the first metalization layer and the third metalization layer. The plurality of wordline connections includes a first portion and a second portion. The first portion of wordline connections is in communication with the first plurality of predecode wires and the wordline drivers of the first port.