Abstract: An invention is provided for an overlapping row decode in a multiport memory. The overlapping row decode includes a first plurality of predecode wires positioned on a first metalization layer. The first plurality of predecode wires is configured to address wordline drivers of a first port. In addition, a second plurality of predecode wires is located on a third metalization layer above the first metalization layer. The second plurality of predecode wires is configured to address wordline drivers of a second port. The overlapping row decode further includes a plurality of wordline connections that are formed on a second metalization layer between the first metalization layer and the third metalization layer. The plurality of wordline connections includes a first portion and a second portion. The first portion of wordline connections is in communication with the first plurality of predecode wires and the wordline drivers of the first port.

Abstract: An invention for self-timing in a memory device is provided. The self-timing system includes a dummy global wordline signal, which is configured to follow a global timing pulse for a memory device. In addition, a row of at least one non-timing memory banks is included. Each non-timing memory bank includes a model row in electrical communication with the dummy global wordline signal. Each model row is comprised of a plurality of load cells. The self-timing system further includes a timing memory bank having a global timing column. The global timing column is comprised of a plurality of load cells that are coupled via at least one bitline. In operation, the global timing column responds to the dummy global wordline signal to provide a self-timing reset signal for the memory device. In this manner, the self-timing reset signal is provided to each active memory bank in the row of memory banks.

Abstract: An invention for a memory core cell is provided. The memory core cell includes a storage cell, which is connected to differential writing circuitry. In addition, the storage cell is connected to single ended reading circuitry. In one aspect, the differential writing circuitry can include a pair of write bitlines coupled to the storage cell by a pair of write access transistors, with each write access transistor having a gate coupled to a write wordline. Also, the signal ended read circuitry can include a read transistor having a gate coupled to the storage element, a first terminal coupled to a read access transistor, and a second terminal coupled to ground. Further, the read access transistor can include a first terminal coupled to a read bitline, a second terminal coupled to the first terminal of the read access transistor, and a gate coupled to a read wordline.

Abstract: A data signaling apparatus includes a differential amplifier for providing an amplified differential output on a pair of outputs in response to a differential signal provided on a pair of inputs, and a clamping resistor between the pair of inputs. The clamping resistor acts to effectively reduce the swing in differential inputs, thereby allowing high gain that does not result in problematic differential outputs. Further, since the resistor is operative for all voltage ranges, it is useful in small signal applications where diodes cannot be used or are too difficult to implement. A data signaling method includes receiving a differential signal on a pair of inputs, reducing the magnitude of the differential signal by a scale factor using a clamping resistor across the pair of inputs, and providing an amplified differential output on a pair of outputs in response to the scaled differential signal provided on the pair of inputs.

Abstract: A low voltage differential signaling circuit employs a mid-point biasing scheme that maintains a desired common mode voltage across all logic states signaled by the circuit. In one driver implementation, separate conduction paths are used to signal respective logic states on a pair of differential signal lines. A common pair of resistors are provided in the conduction path between the two signal lines. The midpoint between the pair of resistors is tied to the desired common mode voltage. A midpoint bias circuit is coupled to a variable resistance in the conduction path so as to maintain the desired common mode voltage by virtue of a voltage division so as to minimize the amount of non-conduction path current at the mid point node. In one example, a replica circuit further provides an anticipated midpoint voltage to the midpoint bias circuit for comparison to the desired midpoint voltage. The midpoint bias circuit adjusts the variable resistance in accordance with the comparison.

Abstract: A method for testing a circuit is provided. The method includes providing a normal internal clock signal for use in accessing functional logic, where the functional logic has access to redundant functional logic during normal operation. The method then applies a stress clock signal to the functional logic, and each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. Based on the applied stress clock signal, the method identifies logic elements of the functional logic that fail to operate as intended.

Abstract: A low voltage differential I/O device and method is modeled using voltage sources and voltage dividers, rather than the current source and sink model of the prior art. In an exemplary implementation, a driver includes two pairs of transistors coupled between voltage sources, each pair associated with a respective logic state. Depending on the logic state to be signaled, one pair of transistors is driven strongly while the other pair is turned off. A differential voltage is established across the true and complement signal lines, the polarity of which is determined by which pair of transistors is driven, and the magnitude of which is readily determined by voltage division of the voltage sources across known resistances. The driver of the invention offers stable and low impedance across both logic states and common mode. Moreover, active devices and feedback are not required to establish a common mode voltage or impedance as in the prior art.

Abstract: A method for identifying faulty and weak memory cells is provided. A normal internal clock signal for use in accessing a memory array is provided, wherein the memory array may contain redundant memory cells that can be accessed during normal operation. In addition, a test is performed on the memory array using a stress clock signal. Each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. In this manner, memory cells that fail the test using the stress clock signal are identified as non-usable memory cells. In some embodiments, the normal internal clock signal is based on required read and write times for the memory cells of the memory array and a margin added to the required read and write times. Each pulse of the stress clock signal can be approximately equal to each pulse of the normal internal clock signal minus the margin.

Abstract: A metal programmable ROM includes a memory cell array having a depth defined by a plurality of wordlines and a width defined by a plurality of bitlines. In addition, a group of memory cells are coupled between a bitline and a ground conection, with each memory cell in the memory cell group coupled to at least one other memory cell in the memory cell group. Finally, a programmed memory cell is defined by a memory cell transistor having its terminals shorted together.

Abstract: A method for identifying faulty and weak memory cells is provided. A normal internal clock signal for use in accessing a memory array is provided, wherein the memory array may contain redundant memory cells that can be accessed during normal operation. In addition, a test is performed on the memory array using a stress clock signal. Each pulse of the stress clock signal is of a shorter duration than each pulse of the normal internal clock signal. In this manner, memory cells that fail the test using the stress clock signal are identified as non-usable memory cells. In some embodiments, the normal internal clock signal is based on required read and write times for the memory cells of the memory array and a margin added to the required read and write times. Each pulse of the stress clock signal can be approximately equal to each pulse of the normal internal clock signal minus the margin.

Abstract: Method and apparatus are disclosed for protection of a circuit against process-induced electrical discharge. The method includes forming a diode in close proximity to a charge collector structure capable of exhibiting the antenna effect, and connecting the diode to the charge collector structure by means of local interconnect techniques during the intermediate processing steps. Additionally, the diode may be formed beneath a connecting pad to educe or eliminate antenna effect problems without significant loss of a die area.

Abstract: An invention is disclosed for setup and hold time characterization in an integrated circuit cell. A setup time is obtained for a first constraint pin. A setup time is also calculated for a test point defined in the integrated circuit cell using the setup time for the first constraint pin and a first propagation delay from the first constraint pin to the test point. A setup time for a second constraint pin is determined based on the setup time for the test point and a second propagation delay from the second constraint pin to the test point. In addition to the setup time, a hold time can be obtained for the first constraint pin, and a hold time for the test point can be calculated using the hold time for the first constraint pin and the first propagation delay. Further, a hold time for the second constraint pin can be determined based on the hold time for the test point and the second propagation delay.

Abstract: An invention is provided for a fuse state sensing circuit that senses the state of a fuse, which is coupled between a ground rail and a fuse state sensing node. The fuse state sensing node indicates a state of the fuse when rail voltage is provided to the fuse state sensing circuit. In addition, a capacitive element is included that is coupled to the fuse state sensing node. The capacitive element is capable of providing a first amount of current to the fuse state sensing node when an initial voltage is supplied to the rail voltage. The capacitive element is further configured to stop supplying the first amount of current upon reaching a threshold voltage of the capacitive element. The fuse state sensing circuit further includes a keeper latch circuit that is coupled to the fuse state sensing node in parallel with the capacitive element. The keeper latch circuit is capable of latching the state of the fuse state sensing node.

Abstract: A load independent single ended sense amplifier is provided. The sense amplifier includes a first current mirror having a first load transistor and a first reflected current transistor, and a second current mirror having a second load transistor and a second reflected current transistor. The first load transistor is capable of communicating a load current to the second load transistor. In addition, a reflected current flowing through the first reflected current transistor and the second reflected current transistor generates an amplified load current.

Abstract: Disclosed is a semiconductor standard cell architecture with local interconnect. The standard cell architecture includes a semiconductor substrate having diffusion regions that are designated for source and drain regions of a functional circuit. The standard cell also includes a polysilicon layer that is patterned to define gate electrodes and interconnections of the semiconductor standard cell architecture. In addition, the standard cell includes a local interconnect metallization layer that is patterned into a plurality of local interconnect metallization lines that are configured to be disposed over the semiconductor substrate and are further configured to substantially interconnect the source and drain regions and gate electrodes to define the functional circuit. The plurality of local interconnect metallization lines are further designed to incorporate local interconnect metallization pins that are connection points for interconnecting the functional circuit to another functional circuit.

Abstract: A metal programmable ROM is disclosed that includes a memory cell array having a depth that is defined by a plurality of wordlines and a width that is defined by a plurality of bitlines. In addition, a group of memory cells are coupled between a bitline and ground, with each memory cell in the memory cell group coupled to at least one other memory cell in the memory cell group. Finally, a programmed memory cell is included that is defined by a memory cell transistor having its terminals shorted together.

Abstract: An automated method for generating input/output (I/O) cells for an integrated circuit chip is provided. The method includes receiving a width parameter (as user requested data) for a desired I/O cell to be used for the integrated circuit chip. The method also includes receiving a tolerance parameter for the desired I/O cell. A cell library is selected to have a plurality of slices to meet the tolerance parameter. Then, the method proceeds to determine a number of the plurality of slices to be used to fit within the width parameter and to satisfy a drive strength parameter. The width parameter is then filled with a first row of the determined number of the plurality of slices. If the first row of slices (in either the N-channel device region or the P-channel device region) does not meet the drive strength parameter, additional rows (e.g., of dynamically adjusted height) can be added to provide an additional amount of transistor width that will meet the drive strength requirement.

Abstract: A metal programmable ROM is disclosed that includes a memory cell array having a depth that is defined by a plurality of wordlines and a width that is defined by a plurality of bitlines. In addition, a group of memory cells are coupled between a bitline and ground, with each memory cell in the memory cell group coupled to at least one other memory cell in the memory cell group. Finally, a programmed memory cell is included that is defined by a memory cell transistor having its terminals shorted together.

Abstract: A metal programmable ROM is disclosed that includes a memory cell array having a depth that is defined by a plurality of wordlines and a width that is defined by a plurality of bitlines. In addition, a group of memory cells are coupled between a bitline and ground, with each memory cell in the memory cell group coupled to at least one other memory cell in the memory cell group. Finally, a programmed memory cell is included that is defined by a memory cell transistor having its terminals shorted together.

Abstract: Disclosed are methods for designing standard cell transistor layouts for minimizing transistor delays and for minimizing power consumption. The method of minimizing transistor delays includes defining a transistor model for a P-type transistor and an N-type transistor of a CMOS standard cell. The method then includes minimizing a ratio between the P-type transistor and the N-type transistor. The ratio is defined by dividing a P-type gate width of the P-type transistor by an N-type gate width of the N-type transistor. The optimizing is performed by substantially minimizing an average delay for the transistor structure. In this embodiment, the CMOS standard cell will define a transistor structure that is implemented to make a logic circuit. The CMOS standard cell is one of a library of standard cells, where each standard cell defines a particular logic circuit.