Abstract: Disclosed is a method of designing a memory device that has substantially reduced bitline voltage offsets. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a six transistor core cell having a bitline and a complementary bitline, and designing a flipped six transistor core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a six transistor core cell followed by a flipped six transistor core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the six transistor core cell is coupled with the flipped complementary bitline of the flipped six transistor core cell, and the complementary bitline of the six transistor core cell is coupled to the flipped bitline of the flipped six transistor core cell.

Abstract: Disclosed is a semiconductor standard cell architecture with local interconnect. The standard cell architecture includes a semiconductor substrate having diffusion regions that are designated for source and drain regions of a functional circuit. The standard cell also includes a polysilicon layer that is patterned to define gate electrodes and interconnections of the semiconductor standard cell architecture. In addition, the standard cell includes a local interconnect metallization layer that is patterned into a plurality of local interconnect metallization lines that are configured to be disposed over the semiconductor substrate and are further configured to substantially interconnect the source and drain regions and gate electrodes to define the functional circuit. The plurality of local interconnect metallization lines are further designed to incorporate local interconnect metallization pins that are connection points for interconnecting the functional circuit to another functional circuit.

Abstract: An automated method for generating input/output (I/O) cells for an integrated circuit chip is provided. The method includes receiving a width parameter (as user requested data) for a desired I/O cell to be used for the integrated circuit chip. The method also includes receiving a tolerance parameter for the desired I/O cell. A cell library is selected to have a plurality of slices to meet the tolerance parameter. Then, the method proceeds to determine a number of the plurality of slices to be used to fit within the width parameter and to satisfy a drive strength parameter. The width parameter is then filled with a first row of the determined number of the plurality of slices. If the first row of slices (in either the N-channel device region or the P-channel device region) does not meet the drive strength parameter, additional rows (e.g., of dynamically adjusted height) can be added to provide an additional amount of transistor width that will meet the drive strength requirement.

Abstract: A highly flexible, heterogeneous architecture for portable, high density, high performance standard cell and gate array applications is disclosed. The architecture is based on the three basic cells and their derivatives, particularly a transmission gate cell, a logic cell, and a drive cell. For gate array implementations, the cells are arranged in a pre-determined regular array format. For standard cell implementations, the arrangement of the cells may be optimized to suit each target logic gate. Optimized transistor sizing is achievable through leaf cells, software sizing, or both.

Abstract: Method and apparatus are disclosed for protection of a circuit against process-induced electrical discharge. The method includes forming a diode in close proximity to a charge collector structure capable of exhibiting the antenna effect, and connecting the diode to the charge collector structure by means of local interconnect techniques during intermediate processing steps. Additionally, the diode may be formed beneath a connecting pad to reduce or eliminate antenna effect problems without significant loss of die area.

Abstract: A method of designing a memory device that has substantially reduced bitline voltage offsets is provided. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a core cell having a bitline and a complementary bitline, and designing a flipped core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a core cell followed by a flipped core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the core cell is coupled with the flipped complementary bitline of the flipped core cell, and the complementary bitline of the core cell is coupled to the flipped bitline of the flipped core cell.

Abstract: A memory device design is provided. The memory device includes a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The memory device further includes a core cell having a bitline and a complementary bitline, and a flipped core cell that has a flipped bitline and a flipped complementary bitline. The multiple pairs of the global bitline and the global complementary bitline have a plurality of core cells that are defined by alternating ones of the core cell and the flipped core.

Abstract: The present invention provides a voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any DC leakage. The voltage tolerant input/output circuit includes (1) an arbiter circuit logically configured to ensure that a gate of a P-driver of the voltage tolerant input/output circuit is biased at the higher of an input/output voltage and an input/output supply voltage when the P-driver is tri-stated, (2) a bias circuit logically configured to biased a floating N-well of the P-driver to ensure that no parasitic diodes formed between any source or drain of a p-device of the voltage tolerant input/output circuit and the N-well of the P-driver is forward biased, and (3) a driver circuit comprising the P-driver.

Abstract: A standard cell circuit architecture and design is provided by way of this disclosure. The standard cell has a plurality of sub-cells that are designed to function together to generate a result and the plurality of sub-cells have at least one input. The standard cell further includes a protection device connected just before and to the at least one input of the plurality of sub-cells. The protection device is designed to prevent charge sharing with circuitry of another standard cell that may be electrically coupled to the standard cell by way of the at least one input. In a specific application of the standard cell, the standard cell can be designed to be a carry chain standard cell. The carry chain standard cell can then be incorporated as part of a library of cells that may be used by a software synthesis layout tool.

Abstract: An approach for reducing antenna effects in integrated circuits involves evaluating an integrated circuit design to identify one or more problem interconnects that satisfy certain antenna effect criteria. The problem interconnects are selectively connected to one or more discharge paths and the integrated circuit design is updated to reflect the connections to the one or more discharge paths.

Abstract: The present invention provides a clock input buffer for a self-timed memory core that is configured to store data. The self-timed memory core generates a reset signal for resetting the clock input buffer. The clock input buffer includes a latch functioning block and a model latch functioning block. The latch functioning block receives a clock signal for generating a control signal for triggering the self-timed memory core to perform an I/O operation. On the other hand, the model latch functioning block receives the clock signal and the control signal for generating a delayed inverse clock signal. The model latch functioning block provides the delayed inverse clock signal to the latch functioning block for generating the control signal. The model latch functioning block is configured to have the same delay and a delay that varies at approximately the same rate as a delay in the latch functioning block.

Abstract: A low power bank architecture implemented in memory access circuitry is disclosed. The bank architecture includes a bank circuit that has a bank core integrated with a pair of bitlines and a bank interface circuit that is coupled to the pair of bitlines. The bank architecture further includes a global data bus pair that is configured to communicate a less than full rail voltage swing. The global data bus pair is coupled to the bank interface circuit of the bank circuit that is designed to convert the less than full rail voltage swing into an up to about full rail voltage swing that is communicated to the pair of bitlines. The bank circuit is configured to be replicated once for each of the pair of bitlines in a memory core having an array of bank cores. By communicating memory access signals, such as differential write data, at a less than full rail voltage over the global data bus pair, a substantial amount of power is saved, which provides excellent power savings for many electronic device applications.

Abstract: A programmable memory test interface for testing a memory device is disclosed. The interface includes a plurality of programmable input pins and output pins. The interface also includes a logic interfacing means for connecting external signals to the plurality of programmable input pins and output pins. The external signals are processed by the logic interfacing means and then communicated to a plurality of memory connection pins that couple up to the memory device. The logic component means is capable of being configured in accordance with one or more memory testing methodologies including a serial built-in-self-test (BIST), a parallel built-in-self-test (BIST), a parallel test, a serial test, and a scan test. The configuring is performed by selectively interconnecting selected ones of the plurality of input pins and output pins to the external signals that drive the logic interface means in a test mode that operates in one or more memory testing methodologies or a mission mode.

Abstract: Disclosed is a sense amplifier for amplifying data signals read from memory devices. The sense amplifier includes a sense amplifying core having an amplifier circuit and an output data latching circuit. The amplifier circuit is configured to voltage amplify the data signal, and the output data latching circuit is configured to latch the amplified data signal. The sense amplifier further includes a dummy sense amplifying core for generating a read enable signal to be communicated to the output data latching circuit of the sense amplifying core. The read enable signal preferably operates to switch-on the output data latching circuit. And, the amplifier circuit is configured to switch itself off via an internal feedback signal.

Abstract: Disclosed is a method of designing a memory device that has substantially reduced bitline voltage offsets. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a six transistor core cell having a bitline and a complementary bitline, and designing a flipped six transistor core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a six transistor core cell followed by a flipped six transistor core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the six transistor core cell is coupled with the flipped complementary bitline of the flipped six transistor core cell, and the complementary bitline of the six transistor core cell is coupled to the flipped bitline of the flipped six transistor core cell.

Abstract: A memory circuit that includes a memory core having an array of core cells is provided. The array of core cells are coupled to a plurality of wordlines and a plurality of bitline pairs. The memory circuit further includes a self-timing path that has a model core cell that is coupled to a model wordline, and the model wordline is driven by a model wordline driver. The self-timing path also includes a model sense amplifier that is coupled to the model core cell through a pair of model bitlines. The model wordline and the pair of model bitlines are each coupled to a plurality of dummy core cells to approximate an RC delay of a worst case core cell of the array of core cells. Further, the model wordline is a folded wordline, such that the model wordline has a termination at a location that is proximate to the model wordline driver.

Abstract: Disclosed is a programmable memory test interface. The test interface includes logic circuitry configured to be integrated to a memory device. The memory device has a plurality of receiving connections that are configured to be coupled to a plurality of internal connections that couple to the logic circuitry. The interface further includes a plurality of programmable input pins and output pins leading to and from the logic circuitry, and the programmable input pins and output pins are configured to receive control signals from a test controller for operating the memory device in either a test mode or a mission mode. The programmable input pins and output pins are selectively interconnected to transform the logic circuitry into at least one type of memory testing methodology interface.

Abstract: Disclosed is a semiconductor layout design for use in integrated circuits that use balance circuitry. The semiconductor layout design includes a set of four substantially self enclosing gate transistors being arranged symmetrically about a common point. Wherein, each of the set of four substantially self enclosing gate transistors have a gate width that is defined by a perimeter around each of the set of four substantially self enclosing gate transistors. The semiconductor layout design preferably includes a balanced circuit having a set of first transistors and a set of second transistors. The set of first transistors being wired diagonally across the set of four substantially self enclosing gate transistors. In a preferred embodiment, the set of second transistors are wired diagonally across the set of four substantially self enclosing gate transistors in a manner that ensures that the set of second transistors are wired substantially perpendicular to the set of first transistors.

Abstract: Disclosed is a method for amplifying a data signal read from a memory device. The method includes sensing an initial voltage difference across a data bus that is coupled to the memory device. Producing an initial voltage difference across a sensed data bus after the sensing detects the initial voltage difference. The initial voltage difference is configured to partially separate a pair of nodes associated with the sensed data bus. The method further includes subsequently isolating the data bus from the sensed data bus to rapidly further separate the pair of nodes associated with the sensed data bus, the rapid separation producing the amplified data signal across the sensed data bus.

Abstract: Disclosed is an apparatus for generating a memory access signal. The apparatus includes a latch having a set state for driving a set transistor, and a reset state for driving a reset transistor. The latch having an input terminal and an output terminal, and the latch transitions between the set and reset states in accordance with a system clock signal. The apparatus further includes a driver coupled to the output terminal of the latch for producing an access signal, and feedback path for feeding back the access signal to the input terminal of the latch. Wherein the latch operates to switch from the set state to the reset state in accordance with the fed back access signal. In this manner, the system clock is isolated from the set transistor when the latch is already in the set state.