Abstract: An embedded memory device structure, and a method for making the embedded memory device structure having self adjusting pre-charge delay characteristics. The method includes selecting a desired memory array having a dummy column of cells. Coupling a pre-charge detect circuit to the dummy column of cells. The pre-charge detect circuit is configured to measure an activation and pre-charge response time of cells contained within the dummy column of cells. Transferring the activation and pre-charge response time to an address transition detect unit. The method further includes generating a custom clock timing signal in response to the activation and pre-charge response time of cells contained within the dummy column of cells.

Abstract: Disclosed is a latch sense amplifier output buffer for amplifying a data signal read from a memory. The latch sense amplifier output buffer includes a sense amplifier core having an amplifier circuit. The amplifier circuit provides amplification on the data signal read from a random access memory cell location. The sense amplifier core is preferably configured to generate an amplified data signal. Further included is an output data latching circuit that is configured to substantially simultaneously store the amplified data signal and generate an output data signal. An output buffer core includes an output driver circuit having a pull up transistor and a pull down transistor. The output driver circuit substantially concurrently receives the amplified data signal from the sense amplifier core and the output data signal from the output data latching circuit.

Abstract: Low power consuming circuitry for amplifying sensed signals in memory devices is disclosed. The low power circuitry includes a amplifier circuit having a data bus line for receiving a data signal from a selected column of a memory array. The data bus line being coupled to a first pre-charger transistor for limiting a data bus voltage swing, and a virtual ground control line for controlling a virtual ground application to a selected column of the memory array. The virtual ground application configured to provide a path to ground for the selected column, and the virtual ground control line being coupled to a second pre-charger transistor for limiting a virtual ground voltage swing. Further included is a gain transistor configured to receive the data signal from the data bus line and provide an amplified data signal to a pull down node located at an input of an inverter. And, a digital data output node located at an output of the inverter.