Patents Assigned to ASM Japan K.K.
  • Interlayer insulation film used for multilayer interconnect of semiconductor integrated circuit and method of manufacturing the same
    Patent number: 7098129
    Abstract: An interlayer insulation film for multilayer interconnect of a semiconductor integrated circuit is formed by forming a first insulation film on a substrate by plasma CVD using a silicon-containing hydrocarbon gas; and continuously forming a second insulation film on the first insulation film at a thickness less than the first insulation film in situ by plasma CVD using a silicon-containing hydrocarbon gas and an oxidizing gas. The second insulation film has a hardness of 6 GPa or higher and is used as a polishing stop layer.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: August 29, 2006
    Assignee: ASM Japan K.K.
    Inventors: Naoto Tsuji, Fumitoshi Ozaki, Satoshi Takahashi
  • METHOD OF FORMING SILICON-CONTAINING INSULATION FILM HAVING LOW DIELECTRIC CONSTANT AND LOW DIFFUSION COEFFICIENT
    Publication number: 20060183341
    Abstract: A method for fabricating a semiconductor device includes: forming on a substrate a silicon-containing insulation film having a diffusion coefficient of about 250 ?m2/min or less as measured using isopropyl alcohol, by plasma reaction using a reaction gas comprising (i) a source gas comprising a silicon-containing hydrocarbon compound containing plural cross-linkable groups, (ii) a cross-linking gas, (iii) an inert gas, and optionally (iv) an oxygen-supplying gas, wherein a flow rate of the oxygen-supplying gas is no more than 25% of that of the source gas; and subjecting the insulation film to an integration process to fabricate a semiconductor device.
    Type: Application
    Filed: May 10, 2006
    Publication date: August 17, 2006
    Applicant: ASM JAPAN K.K.
    Inventors: Naoto Tsuji, Kiyohiro Matsushita, Satoshi Takahashi, Nathan Kameling
  • Two-step formation of etch stop layer
    Patent number: 7091133
    Abstract: A film is formed on a semiconductor substrate where a copper layer is to be formed and in contact with the film, by a method including the steps of: (i) introducing a first reaction gas comprising a deposition gas containing silicon, carbon, and hydrogen, and an inert gas, into a reaction space where a substrate is placed; (ii) depositing a silicon carbide film on the substrate by exciting the first reaction gas into a plasma; (iii) introducing a second reaction gas comprising a deposition gas containing silicon, carbon, and hydrogen, an oxidizing gas, and an inert gas, into the reaction space; and (iv) depositing a carbon-containing silicon oxide film on top of the silicon carbide film by exciting the second reaction gas into a plasma.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: August 15, 2006
    Assignee: ASM Japan K.K.
    Inventors: Kamal Kishore Goundar, Tadashi Kumakura
  • Semiconductor-manufacturing apparatus provided with ultraviolet light-emitting mechanism and method of treating semiconductor substrate using ultraviolet light emission
    Publication number: 20060165904
    Abstract: An apparatus for treating a semiconductor substrate includes a chamber an internal pressure of which can be controlled from a vacuum to the vicinity of an atmospheric pressure, multiple ultraviolet light emitters provided inside the chamber, a heater provided facing and parallel to the emitters inside the chamber, and a filter being disposed between the emitters and the heater and used for uniformizing the intensity of illumination of ultraviolet light; and further includes a configuration for uniformly distributing the intensity of illumination of ultraviolet light emitted from the emitters onto a surface of the heater.
    Type: Application
    Filed: January 21, 2005
    Publication date: July 27, 2006
    Applicant: ASM JAPAN K.K.
    Inventor: Naoki Ohara
  • Method of forming interconnection in semiconductor device
    Publication number: 20060160352
    Abstract: A multilayer interconnection structure is formed by a method comprising the steps of: Forming a low dielectric constant film on a substrate, curing the low dielectric constant film by irradiating it with UV light, laminating a UV blocking film, laminating a next low dielectric constant film, and curing the next low dielectric constant film by irradiating it with UV light.
    Type: Application
    Filed: December 2, 2005
    Publication date: July 20, 2006
    Applicant: ASM JAPAN K.K.
    Inventors: Kiyohiro Matsushita, Naoki Ohara, Nathan Kemeling
  • Plasma processing apparatus with insulated gas inlet pore
    Publication number: 20060137610
    Abstract: A plasma processing apparatus includes: a reaction chamber; two electrodes provided inside the reaction chamber for generating a plasma therebetween, wherein at least one of the electrodes has at least one gas inlet pore through which a gas is introduced into the reaction chamber; and a gas inlet pipe coupled to the gas inlet pore for introducing the gas into the reaction chamber. The gas inlet pipe is grounded and insulated from the gas inlet pore, wherein an insulation member is placed inside the gas inlet pipe and the gas inlet pore.
    Type: Application
    Filed: September 28, 2005
    Publication date: June 29, 2006
    Applicant: ASM JAPAN K.K.
    Inventors: Yu Yoshizaki, Ryu Nakano
  • Method for forming low-k hard film
    Patent number: 7064088
    Abstract: A hard film is formed on an insulation film formed on a semiconductor substrate by vaporizing a silicon-containing hydrocarbon compound to provide a source gas, introducing a reaction gas composed of the source gas and optionally an additive gas such as alcohol to a reaction space of a plasma CVD apparatus, and applying low-frequency RF power and high-frequency RF power. The silicon-containing hydrocarbon compound includes a cyclic Si-containing hydrocarbon compound and/or a linear Si-containing hydrocarbon compound, as a basal structure, with reactive groups for form oligomers using the basal structure. The residence time of the reaction gas in the reaction space is lengthened by reducing the total flow of the reaction gas in such a way as to form a siloxan polymer film with a low dielectric constant.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: June 20, 2006
    Assignee: ASM Japan K.K.
    Inventors: Yasuyoshi Hyodo, Atsuki Fukazawa, Yoshinori Morisada, Masashi Yamaguchi, Nobuo Matsuki
  • Wafer transfer mechanism
    Publication number: 20060113806
    Abstract: A transfer mechanism for transferring a workpiece includes an arm member including a tip projection provided at a tip end thereof for contacting a periphery of the workpiece and restricting movement of the workpiece. The arm member further includes multiple supporting projections protruding from a top surface thereof for contacting and supporting a back side of the workpiece.
    Type: Application
    Filed: November 29, 2004
    Publication date: June 1, 2006
    Applicant: ASM JAPAN K.K.
    Inventors: Naota Tsuji, Yukihiro Mori, Takashi Hagino
  • Method for forming insulation film
    Publication number: 20060110931
    Abstract: A method for forming an insulation film on a semiconductor substrate by plasma reaction includes: vaporizing a silicon-containing hydrocarbon having a Si—O bond compound to provide a source gas; introducing the source gas and a carrier gas without an oxidizing gas into a reaction space for plasma CVD processing; and forming an insulation film constituted by Si, C, O, and H on a substrate by plasma reaction using a combination of low-frequency RF power and high-frequency RF power in the reaction space. The plasma reaction is activated while controlling the flow of the reaction gas to lengthen a residence time, Rt, of the reaction gas in the reaction space.
    Type: Application
    Filed: December 5, 2005
    Publication date: May 25, 2006
    Applicant: ASM JAPAN K.K.
    Inventors: Atsuki Fukazawa, Kenichi Kagami
  • Formation technology of nano-particle films having low dielectric constant
    Publication number: 20060105583
    Abstract: A method for forming a low dielectric constant film includes the steps of: introducing reaction gas comprising an organo Si gas and an inert gas into a reactor of a capacitively-coupled CVD apparatus; adjusting a size of fine particles being generated in the vapor phase to a nanometer order size as a function of a plasma discharge period inside the reactor; and depositing fine particles generated on a substrate being placed inside the reactor.
    Type: Application
    Filed: November 17, 2004
    Publication date: May 18, 2006
    Applicants: ASM JAPAN K.K., Kyushu University, National University Corporation
    Inventors: Shingo Ikeda, Nobuo Matsuki, Yoshinori Morisada, Yukio Watanabe, Masaharu Shiratani, Kazunori Koga, Shota Nunomura
  • Gas-introducing system and plasma CVD apparatus
    Publication number: 20060090700
    Abstract: A gas-introducing system for plasma CVD and cleaning includes: a showerhead including a top plate with a gas inlet port and a shower plate; a rectifying plate installed in the interior space of the showerhead and dividing the interior space into an upper space and a lower space; a structure for inhibiting inactivation of active species of the activated cleaning gas at the rectifying plate; and a piping unit for connecting the gas inlet port of the showerhead to a remote plasma unit and a reaction gas introduction port.
    Type: Application
    Filed: October 28, 2005
    Publication date: May 4, 2006
    Applicant: ASM JAPAN K.K.
    Inventors: Kiyoshi Satoh, Yasushi Fukasawa, Kazuya Matsumoto
  • Method of forming fluorine-doped low-dielectric-constant insulating film
    Patent number: 7037855
    Abstract: A method of forming low-dielectric-constant silicon oxide films by capacitive-coupled plasma CVD comprises: introducing a processing gas comprising SiH4 as a silicon source gas, SiF4 as a fluorine source gas, and CO2 as an oxidizing gas to a reaction chamber at a ratio of (SiH4+SiF4)/CO2 in the range of 0.02 to 0.2 and at a total pressure of 250 Pa to 350 Pa; applying first RF power at a frequency of 10 MHz to 30 MHz and second RF power at a frequency of 400 kHz to 500 kHz by overlaying the two RF powers to generate a plasma reaction field within the reaction chamber; and controlling a flow of the respective gases and the respective RF power outputs.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 2, 2006
    Assignee: ASM Japan K.K.
    Inventors: Naoto Tsuji, Yozo Ikedo, Ryu Nakano, Shuzo Hebiguchi
  • Semiconductor processing apparatus comprising chamber partitioned into reaction and transfer sections
    Patent number: 7021881
    Abstract: Semiconductor processing equipment that has increased efficiency, throughput, and stability, as well as reduced operating cost, footprint, and faceprint is provided. Other than during deposition, the atmosphere of both the reaction chamber and the transfer chamber are evacuated using the transfer chamber exhaust port, which is located below the surface of the semiconductor wafer. This configuration prevents particles generated during wafer transfer or during deposition from adhering to the surface of the semiconductor wafer. Additionally, by introducing a purge gas into the transfer chamber during deposition, and by using an insulation separating plate 34, the atmospheres of the transfer and reaction chambers can be effectively isolated from each other, thereby preventing deposition on the walls and components of the transfer chamber.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: April 4, 2006
    Assignee: ASM Japan K.K.
    Inventors: Takayuki Yamagishi, Masaei Suwada, Takeshi Watanabe
  • DC bias voltage measurement circuit and plasma CVD apparatus comprising the same
    Publication number: 20060063284
    Abstract: A circuit for measuring DC bias voltage occurring in an ungrounded electrode of a plasma processing apparatus, includes: a first terminal connected between the ungrounded electrode and the RF power source; a second terminal for determining a value of the DC bias voltage; a first resistance connected between the first terminal and the second terminal; a second resistance connected between the second terminal and a ground; and a condenser disposed in parallel to the second resistance between the second terminal and the ground. The sum of the first resistance value and the second resistance value is about 50 M? or greater.
    Type: Application
    Filed: September 22, 2005
    Publication date: March 23, 2006
    Applicant: ASM JAPAN K.K.
    Inventors: Mitsutoshi Shuto, Yasuaki Suzuki
  • Gas-shield electron-beam gun for thin-film curing application
    Patent number: 7012268
    Abstract: An electron-beam irradiation apparatus includes an evacuatable filament-electron gun chamber housing a filament and an anode and having an inactive-gas inlet through which an inactive gas flows in; an evacuatable treatment chamber connected to an exhaust system; and a separation wall for separating the filament-electrode gun chamber and the treatment chamber. The separation wall has an aperture configured to pass electrons and gas therethrough from the filament-electron gun chamber.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: March 14, 2006
    Assignee: ASM Japan K.K.
    Inventors: Nobuo Matsuki, Atsuki Fukazawa, Naoto Tsuji
  • Polymer film and method for producing the same
    Publication number: 20060052560
    Abstract: A copolymer film having a decreased dielectric constant which is produced by supplying at least two organic monomers as raw materials, forming a film of a copolymer comprising a backbone based on said at least two monomers on a surface of a substrate, and heating the copolymer film at a temperature higher than a temperature at which the copolymer film is formed.
    Type: Application
    Filed: July 22, 2005
    Publication date: March 9, 2006
    Applicants: Sumitomo Chemical Company, Limited, NEC CORPORATION, ASM Japan K.K.
    Inventors: Nobutaka Kunimi, Jun Kawahara, Akinori Nakano, Keizo Kinoshita
  • METHOD OF FORMING FLUORINE-DOPED LOW-DIELECTRIC-CONSTANT INSULATING FILM
    Publication number: 20060046519
    Abstract: A method of forming low-dielectric-constant silicon oxide films by capacitive-coupled plasma CVD comprises: introducing a processing gas comprising SiH4 as a silicon source gas, SiF4 as a fluorine source gas, and CO2 as an oxidizing gas to a reaction chamber at a ratio of (SiH4+SiF4)/CO2 in the range of 0.02 to 0.2 and at a total pressure of 250 Pa to 350 Pa; applying first RF power at a frequency of 10 MHz to 30 MHz and second RF power at a frequency of 400 kHz to 500 kHz by overlaying the two RF powers to generate a plasma reaction field within the reaction chamber; and controlling a flow of the respective gases and the respective RF power outputs.
    Type: Application
    Filed: August 31, 2004
    Publication date: March 2, 2006
    Applicant: ASM JAPAN K.K.
    Inventors: Naoto Tsuji, Yozo Ikedo, Ryu Nakano, Shuzo Hebiguchi
  • Dual-chamber plasma processing apparatus
    Publication number: 20060021701
    Abstract: A dual-chamber plasma processing apparatus comprises two reaction spaces which are equipped with different gas inlet lines and different RF systems. Each reaction space is provided with an RF wave entry path and an RF wave return path to supply RF power from an RF power source and return RF power to the same RF power source.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 2, 2006
    Applicant: ASM JAPAN K.K.
    Inventors: Yasuhiro Tobe, Yoshinori Morisada, Shingo Ikeda, Baiei Kawano
  • Method of manufacturing silicon carbide film
    Patent number: 6991959
    Abstract: A method for forming a silicon carbide film on a semiconductor substrate by plasma CVD includes: introducing a raw material gas containing silicon, carbon, and hydrogen, an inert gas, and optionally an hydrogen source gas, into a reaction chamber at a predetermined mixing formulation of the raw material gas to the inert gas; applying radio-frequency power at the mixing formulation, thereby forming a curable silicon carbide film having a dielectric constant of about 4.0 or higher; and continuously applying radio-frequency power at a mixing formulation reducing the raw material gas and the hydrogen source gas if any, thereby curing the silicon carbide film to give a dielectric constant and a leakage current lower than those of the curable silicon carbide film.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: January 31, 2006
    Assignee: ASM Japan K.K.
    Inventors: Kamal Kishore Goundar, Kiyoshi Satoh
  • Method of forming a fine pattern using a silicon-oxide-based film, semiconductor device with a silicon-oxide-based film and method of manufacture thereof
    Patent number: 6992013
    Abstract: In a method of forming a fine pattern, a silicon-oxide-based film is formed directly or by way of another layer on a substrate or on an underlying layer. The silicon-oxide-based film is formed such that nitrogen content of the surface thereof assumes a value of 0.1 atm. % or less. A chemically-amplified photoresist layer is formed on the silicon-oxide-based film. A mask pattern of a mask is transferred onto the chemically-amplified photoresist layer upon exposure through the mask. Thus, there is prevented generation of a tapered corner in a portion of a resist pattern in the vicinity of a boundary area between the resist pattern and a substrate.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: January 31, 2006
    Assignees: Semiconductor Leading Edge Technologies, Inc., ASM Japan K.K.
    Inventors: Ichiro Okabe, Hiroki Arai