Abstract: Various semiconductor chip package substrates with reinforcement and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder reinforcement structure is formed on the first side of the package substrate outside of the central area to resist bending of the package substrate.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: An apparatus and method for processor core to graphics processor scheduling and execution is disclosed. In one embodiment, an apparatus includes a general purpose processor configured to execute instructions from a first instruction set and a graphic processing unit (GPU) configured to execute instructions from a second instruction set. The apparatus also includes a microcode unit configured to store microcode instructions that, when executed by the general purpose processor core, generate translated instructions, wherein the translated instructions are generated by translating selected instructions from the first instruction set translated into instructions of the second instruction set. The general purpose processor is configured to, responsive to performing a translation, pass the translated instructions to the GPU. The GPU is configured to execute the translated instructions and pass corresponding results back to the general purpose processor.

Abstract: Briefly, a method and apparatus adjusts the power consumption level of an integrated circuit by dynamically scaling the clock frequency based on the real-time determined power consumption level. In one example, the method and apparatus changes an actual clock frequency of the integrated circuit to an effective clock frequency based on the maximum clock frequency and the difference between the threshold power consumption level and the actual power consumption level of the integrated circuit in the previous sampling interval. In one example, an effective clock frequency of the integrated circuit in the current sampling interval is determined. In one example, the difference between the maximum and effective clock frequencies in the current sampling interval is proportional to the difference between the threshold and actual power consumption levels in the previous sampling interval. The actual clock frequency of the integrated circuit is changed to the determined effective clock frequency.

Abstract: A method and apparatus for providing rendering of subsections of screen space receives render commands associated with different screen subsections, such as from a command buffer populated by a coprocessor, and determines which screen section is currently being rendered by a rendering engine, or stated another way, which screen section the host processor wishes to have rendered, and evaluates screen subsection data that is associated with a received rendering command. The screen subsection data identifies a screen subsection for which the command refers. The method includes executing the command if it is determined that the command refers to a current screen section being rendered.

Abstract: A narrow band, tunable antenna uses a series of small inductors wired in series to produce different resonant frequencies from a single antenna across a wide frequency spectrum. Radio Frequency (RF) switches are positioned in parallel with the inductors and are capable of shunting a selected inductor out of the antenna circuit thereby changing the electrical length of the antenna and consequently, the resonant frequency. The RF switch control circuitry is isolated from the RF current in the antenna.

Abstract: A method and apparatus are described for mapping a physical memory having different memory regions. A plurality of virtual non-uniform memory access (NUMA) nodes may be defined in system memory to represent memory segments of various performance characteristics. Memory segments of a high-bandwidth memory (HBM) system memory may be allocated to a first memory region of the physical memory having memory segments represented by a first one of the NUMA nodes. The physical memory may include a second memory region having memory segments represented by a second one of the NUMA nodes. Memory segments of system memory may be allocated to the second memory region. The physical memory may further include a third memory region having memory segments represented by a third one of the NUMA nodes. Memory segments of an interleaved uniform memory access (UMA) graphics memory may be allocated to the third memory region.

Abstract: A low power biasing circuit for powering up split-rail electronic circuits includes an intermediate voltage generator at each pad which is supplied by a temporary supply voltage to generate a temporary intermediate voltage only when a power signal indicates that all external voltage rails are not safe, thereby reducing power consumption.

Abstract: An apparatus, computer readable medium, and method of event based dynamic power management. The method includes responding to receiving an indication of an event that is external to a hardware block engine by adjusting the power to the hardware block engine, if the event indicates that the power to the hardware block engine should be adjusted. The method may include receiving a second event that is external to the hardware block engine. The method may include determining whether or not the power should be adjusted to the hardware block engine based on the event and the second event. If it is determined that the power should be adjusted, then the power may be adjusted to the hardware block based on the event and second event. A method of monitoring a component and sending an indication of an event that the component will not require a hardware block engine is disclosed.

Abstract: A video device having data lanes and a method of operating the video device includes obtaining a stream of debug data in response to a test operation, framing the stream of debug data independent of establishing a video blanking period, and transmitting the framed stream of debug data across one or more data lanes of the video link for operation between a video source device and a video sink device. The method also includes generating a stream of video data related to the test operation, framing the stream of video data to establish a video blanking period, and transmitting the framed stream of debug data concurrently with the framed stream of video data across the one or more data lanes of the video link.

Abstract: The present disclosure relates to a method and system for content presentation in a main processor shutoff mode. A method for content presentation includes transferring content to at least one of a co-processor and storage accessible by the co-processor and shutting off the main processor in response to the transferring of content such that the main processor is disabled while the co-processor presents the content stored in the storage. The content may include at least one of multimedia data, text data, and image data. A disclosed system includes a main processor in communication with a co-processor. The main processor includes data transfer logic operative to transfer the content and to shut off the main processor in response to the transferring of content such that the main processor is disabled while the co-processor presents the content stored in the storage.

Abstract: A method and apparatus determines an activity history context for each of a plurality of virtual machines sharing use of a graphics processing core. Each activity history context provides information related to a power setting of at least one engine of the graphics processing core during at least one prior use of the graphics processing core by the corresponding virtual machine. The method and apparatus controls a power setting of the at least one engine of the graphics processing core based on the activity history context corresponding to an active virtual machine using the graphics processing core.

Abstract: Systems and methods are used to configure a communication channel. A source device can dynamically map Display Port lanes to support both display devices and USB3.0 devices. A method for configuring a communication channel includes detecting a device connection event indicating a change to a configuration of the communication channel in response to a branch device of the communication channel satisfying a dynamic configuration capability criteria indicating that the communication channel is reconfigurable. Configuration parameters of a sink device in the communication channel are identified. The communication channel is reconfigured to carry a source data stream to the sink device based on the configuration parameters.

Abstract: A transmitting interconnect interface inserts clock mismatch compensation symbols into a transmitted data stream so as to allow the receiving interconnect interface to compensate for clock frequency mismatch between transmit-side and receive-side clocks. The transmitting interconnect interface adjusts the rate of insertion of these symbols based on a determination of the clock frequency mismatch. The transmitting interconnect interface can incrementally adjust the insertion rate to change substantially proportionally with changes in the clock frequency mismatch. Alternatively, the transmitting interconnect interface can set the insertion rate to one of two levels. By adapting the insertion rate to the current measured clock frequency mismatch, the bandwidth penalty incurred by transmitting clock mismatch compensation symbols in excess of that necessary to permit receiver clock tolerance compensation can be reduced, thereby permitting more transmit bandwidth to be used for transmitting data.

Abstract: Apparatuses, computer readable mediums, and methods of encoding video are disclosed. A video comprising a plurality of frames is encoded. The method may determine whether to encode a frame as an interframe (I frame) or a predicted frame (P frame). An I frame may be encoded with a quantization parameter (QP), which may be determined for the I frame. A P frame may be encoded with a QP limited to vary between a lower QP and an upper QP. After encoding N P frames, QP may be adjusted, where N is a fixed or dynamically adjusted number of frames. If a number of bits used to encode the N P frames exceeds a first budget threshold then the value of QP may be raised, and if the number of bits used to encode the N P frames is below a second budget threshold then the value of QP may be lowered.

Abstract: A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a display serial interface protocol, and a uni-directional serial link which accords to a camera serial interface protocol. The GMIC receives packets from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a host memory operation and may be connected to a display over a bi-directional serial link and to a camera over a uni-directional serial link and a bi-directional control link allowing the host to control the display and camera.

Abstract: To adjust brightness of at least a portion of a display image, a type of content to be included within the display image is determined and, based on the identified content type, the light source of the display is set to an adjusted intensity. Thereafter, that portion of the display image unrelated to the content requiring adjusted brightness is processed to account for the adjusted intensity of the light source. Because the processing in accordance with the present invention is performed entirely on one or more processors that provide the display images to the display, the present invention overcomes the added complexity and cost associated with prior art techniques, while simultaneously providing the flexibility to quickly adjust display brightness based on types of content being included in the displayed image.

Abstract: An apparatus and method provides an automated mechanism for configuring a position arrangement of displays in a group of displays, such as a display grid. The apparatus and method uses an image capture unit, such as a camera to capture an image of the entire display grid while test patterns are being provided. In one example, a first device outputs the test patterns to the display grid while a second device that includes the camera analyzes the captured images and determines whether a display in the display grid needs to be logically remapped to provide proper image display when the first device outputs full SLS frames in normal operation.

Abstract: An image processing system and method receives one or more digital images in the form of image data, including selected object data of a digital image, and determines, by an electronic recognition process, if a recognition match is available between the selected object data of the digital image and image object library data associated with image descriptor library data. An automated library user interface presents selectable matched object descriptor data associated with the image descriptor library data when a recognition match occurs between the selected object data of the digital image and the image descriptor library data. In response, the automated library user interface provides user feedback data to confirm that the image descriptor library data corresponds with the selected object data of the digital image, or entered descriptor data if no match or an incorrect match occurs, to create library descriptor associated image data.

Abstract: A power converter for a load with varying power requirements dynamically adjusts its supply voltage to the load so as to track the radio frequency (RF) envelope of the signal being carried by the load. The supply voltage can be provided by a multiple-output charge pump providing multiple output voltage levels concurrently, and a switch to provide a selected one of the different output voltage levels as the supply voltage to the load. A controller controls the switch to dynamically modify the voltage level selected for output as the supply voltage such that the supply voltage tracks the RF envelope of the signal being carried by the load. As the switching losses of transistors of the power converter may exceed the power savings achieved through envelope tracking, the power converter employs a peak following frequency divider circuit that limits the switching frequency of the power converter to a threshold frequency.