Abstract: Apparatus and methods for reducing power consumption of a data transfer interface in a computer system are disclosed. In one embodiment, a method for reducing power consumption of a data transfer interface between a first device and a second device, includes, identifying a free interval between a first data and a second data, disabling the data transfer interface during the free interval, enabling the data transfer interface at the end of the free interval, and transmitting the second data. The method may also include a step of notifying the second device that the data transfer interface is being temporarily disabled. Another embodiment, for example, includes the transfer of display data (or video frames) over an interface, such as, a DisplayPort interface, between a graphics controller device and a timing controller device in a computer system.

Abstract: A method, a device, and a non-transitory computer readable medium for performing dithering on an L bit long input data are presented. An M bit long random data is generated, wherein M is a number of least significant bits of the input data. An M bit long frame counter value is added to the random data. The input data is rounded up to L-M most significant bits when the M least significant bits of the input data is greater than the sum of the frame counter value and the random data. The input data is truncated to the L-M most significant bits when the M least significant bits of the input data is less than or equal to the sum of the frame counter value and the random data.

Abstract: An apparatus and a method for selecting an intra prediction mode for use in video transcoding obtain information from a decoder portion of a video transcoder regarding one or more intra prediction modes used in previously encoding one or more data blocks of a source image. The apparatus and method select an intra prediction mode for encoding a decoded data block corresponding to the one or more data blocks of the source image based on the information obtained from the decoder portion regarding the one or more intra prediction modes used in previously encoding the one or more data blocks of the source image.

Abstract: A content player includes a pausable mass storage device player that can be used to record and play content. The pausable mass storage device can become paused in response to an assertion of a pause signal. Once paused, the content player remains paused until the pause signal is deasserted. The content player also includes an event detector that is coupled to the pausable mass storage device player. The content player detects a non-viewer initiated event, (e.g., an automatic event such as the receipt of an email with embedded enhanced content), and to assert the pause signal in response thereto. The content player receives content, detects an event, and in response to detecting the event, pauses the content to a presentation device and spools the content onto the mass storage device.

Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a layer of a first metallic material on a semiconductor chip. The first layer has a first physical quantity. A layer of a second metallic material is deposited on the layer of the first metallic material. The second layer has a second physical quantity. The first and second layers are reflowed to form a solder structure with a desired ratio of the first metallic material to the second metallic material.

Abstract: A shader unit is configured to provide an increased and dynamically changeable amount of ALU processing bandwidth. The shader unit includes a plurality of ALUs for processing pixel data according to a shader program. Each of the ALUs is configurable to be enabled and disabled. When disabled, the ALU is powered off, thereby reducing the power consumption of the shader unit. In one embodiment, the plurality of ALUs are logically configured into groups called ALU-pipes, each of which can be enabled and disabled. When an ALU-pipe is disabled, each ALU associated with the disabled ALU-pipe is disabled. The shader unit includes a sequencer that executes the shader program, determines the number of ALUs to be enabled, receives an input data stream of pixel data, assigns groups of pixel data to each enabled ALU, sends the assigned pixel data to their respective ALUs, and sends ALU instructions to the ALUs to process the received pixel data according to the shader program.

Abstract: A method and apparatus is provided for reconstructing video frames that include missing pixels as a result of video stabilization techniques to compensate for camera movement and/or zooming. In one example, the method and apparatus caches transformed frames of video, identifies coordinates of missing pixels in a current transformed frame, and sequentially processes, for only the missing pixel coordinates, the cached transformed frames in reverse chronological order to identify pixels at coordinates in the cached transformed frames having valid data and corresponding to one of the missing pixel coordinates. Upon identifying a pixel having valid data at a coordinate in a cached transformed frame corresponding to a missing pixel coordinate, the method and apparatus inserts the valid data at the missing pixel coordinate.

Abstract: A method and apparatus for video stream processing is implemented in a monitor scaler chip (MSC). The MSC receives the video stream and determines whether the video stream includes copy protected content. The MSC routes the video stream based upon the determination.

Abstract: A method and system for producing a single view video signal based on a multiview video coding (MVC) signal stream. A MVC signal stream representing multiple spatially related views of a scene, including a base view and at least one dependent view, is decoded to provide multiple decoded video signals representing the spatially related views, with respective portions of the MVC signal stream representing one of multiple temporally adjacent video frames, and the MVC signal stream representing multiple sequences of spatially adjacent video frames. The decoded video signals are processed to provide a processed video signal representing one of the spatially related views using image information from more than one of the decoded video signals. As a result, more image data is used during processing, thereby improving the spatial and temporal image quality.

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

Abstract: A bus protocol compatible device, includes a transmitter having a first mode for providing a reference clock signal to an output, and a second mode for providing a training sequence to the output, and a power state controller for placing the transmitter in the first mode for a first period of time in response to a change in a link state, and in the second mode after an expiration of the first period of time.

Abstract: A filter includes a conventional filtering block and a protection block. The conventional filtering block receives input values and provides filtered values. The protection block receives filtered values and a group of input values proximate the current input, to ensure that the output is lies within a range computed for the current input. The range is determined by the protection block based on the group of input values proximate the current input. Any algorithm or statistical function may be applied to the group of input values to determine the range. If a filtered value provided by the conventional filtering block is outside the range, then the protection block computes and outputs a value that is within the range. The filter may be used in temporal or spatial filtering of images and video to mitigate artifacts such as motion artifacts and static artifacts.

Abstract: A method, computer program product, and system that includes a virtual function module with an emulated display timing device, a first independent resource, and a second independent resource, where the first and second independent resources signal a physical function module that a new surface has been rendered, and where the physical function module signals the virtual function module via the emulated timing device and the first and second independent resources when the rendered new surface has been displayed, copied, used, or otherwise consumed.

Abstract: Briefly, graphics data processing logic includes a plurality of parallel arithmetic logic units (ALUs), such as floating point processors or any other suitable logic, that operate as a vector processor on at least one of pixel data and vertex data (or both) and a programmable storage element that contains data representing which of the plurality of arithmetic logic units are not to receive data for processing. The graphics data processing logic also includes parallel ALU data packing logic that is operatively coupled to the plurality of arithmetic logic processing units and to the programmable storage element to pack data only for the plurality of arithmetic logic units identified by the data in the programmable storage element as being enabled.

Abstract: A pre-emphasis circuit is disclosed. In one embodiment, a pre-emphasis circuit includes a first signal path configured to receive a first signal and a second signal path configured to receive the first signal. The second signal path includes a re-timing circuit configured to delay the first signal by a pre-determined amount to produce a second signal. The pre-emphasis circuit also includes a summing circuit coupled to receive the first signal from the first signal path and the second signal from the second signal path. The summing circuit is configured to add the second signal to the first signal to produce a third signal, wherein the third signal is logically equivalent to the first signal. The third signal has a first magnitude for a first portion of a bit-time of the first signal, and a second magnitude for a second portion of the bit-time of the first signal.

Abstract: Described herein are methods and related apparatus for the allocation of computing resources to perform computing tasks. The methods described herein may be used to allocate computing tasks to many different types of computing resources, such as processor cores, individual computers, and virtual machines. Characteristics of the available computing resources, as well as other aspects of the computing environment, are modeled in a multidimensional coordinate system. Each coordinate point in the coordinate system corresponds to a unique combination of attributes of the computing resources/computing environment, and each coordinate point is associated with a weight that indicates the relative desirability of the coordinate point. To allocate a computing resource to execute a task, the weights of the coordinate points, as well as other related factors, are analyzed.

Abstract: An integrated circuit including an electrostatic discharge (ESD) equalizer is described. The integrated circuit may include a first ESD protection circuit coupled between a first node and a ground node of the integrated circuit and a second ESD protection circuit coupled between a second node and the ground node. The integrated circuit may also include an ESD equalizer that changes from an impedance of a path between the first node and the second node from a high impedance to a low impedance in response to electrostatic discharge (ESD) through the first node or the second node.

Abstract: A method and device for providing synchronized data output is provided. The method includes generating two data streams sending data to be presented in synchronization. Both streams are generated by the same processor-based device. The first data stream follows a first protocol and the second data stream follows a second (different) protocol. The processor of the processor-based device adjusts a data rate of the second data stream to cause a reduction in any timing offset between the streams.

Abstract: Embodiments of a system and method including graphics processing of a pixel sample are described. According to an embodiment, a first depth test processes a value, such as a z/stencil value, of a pixel sample and determines whether the value of the pixel sample satisfies the first depth test. If the value of the pixel sample satisfies the first depth test, the value of the pixel sample is not immediately written to storage, such as a Z-buffer. That is, if the value of the pixel sample satisfies the first depth test, the depth processing logic prevents or delays a write operation for the value of the pixel sample to storage at that time. A second depth test is performed on the value of the pixel sample if the value of the pixel sample satisfied the first depth test. If the value of the pixel sample satisfies the second depth test, the value of the pixel sample is then written to storage.

Abstract: Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing.