Abstract: A method includes generating a first, second and third voltage output from a temperature sensing element of an integrated circuit using a respective, corresponding first, second and third, switched current source, for sequentially switching a respective first, second and third excitation current through the temperature sensing element. The third switched current source generates the corresponding third voltage output as a reference voltage between the first voltage and the second voltage. An error corrected difference is calculated between the first voltage and the second voltage using the reference voltage. In the method, the second excitation current is proportional to the first excitation current by a value n, and the third excitation current is proportional to the first excitation current by the square root of n.

Abstract: A system and method using messages to access registers and memory in a PCI Express communications link environment. Vendor defined PCI Express messages can be used to read and write to the memory-mapped or register space of a device. Four types of accesses are defined using this messaging approach, namely memory read, memory write, configuration read and configuration write. The type of register access desired is defined by the appropriate value in a vendor-specific type field in the header of the vendor defined message. If a PCI Express compliant device at the other end of the PCI Express link does not support these types of messages, the messages are silently discarded by the receiver and no error is reported.

Abstract: A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew.

Abstract: A method comprises disabling a video digital-to-analog converter (DAC) that is configured to provide an output current representative of a video signal to an output node of an accessory connector in an enabled state. The accessory connector is coupleable to an accessory device. The method further comprises determining, while the video DAC is disabled, whether the accessory connector is coupled to the accessory device based on a voltage at the output node while the output node is connected to the first voltage reference via a resistor having a resistance.

Abstract: In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultiplexor. Adaptation field is handled by a separate parser. In addition, primary elementary stream data can be handled by separate primary elementary stream parsers based upon the packet identifier of the primary elementary stream. Video packets can be parsed based upon stream identifier values. Specific packets of data are stored in one or more system memory or video memory buffers by an output controller based upon allocation table information. Private data associated with specific elementary streams or packet adaptation fields are repacketized, and written to an output buffer location. In specific implementations, the hardware associated with the system is used to acquire the data stream without any knowledge of the specific protocol of the stream.

Abstract: A method of operating a processing device is provided. The method includes, responsive to an idle state of the processing device, transitioning the processing device to a substantially disabled state. The processing device, for example, may be a graphics processing unit (GPU). Transitioning the processing device to a substantially disabled state upon detection of an idle state may result in power savings. Corresponding systems and computer program products are also provided.

Abstract: Methods and apparatus provide for voltage level shifting with concurrent synchronization. The apparatus includes level shifting logic that in response to a non-level shifted clock signal from a first voltage domain, provides level shifted concurrently synchronous differential data signals in a second voltage domain based on pre-level shifted differential data signals from the first voltage domain. The first voltage domain may be, for example, a core logic voltage domain in which core logic operates. The second voltage domain may be, for example, an input/output (I/O) voltage domain in which an I/O buffer operates. The voltage level of the level shifted concurrently synchronous differential data signals is shifted from the pre-level shifted differential data signals, and the timing of the level shifted concurrently synchronous differential data signals is concurrently referenced to the non-level shifted clock signal.

Abstract: A circuit and method for monitoring current flow to an integrated circuit (IC), alone or mounted on a substrate, in a temperature-compensated manner. In accordance with a preferred embodiment, a plurality of resistances having substantially equal temperature coefficients establishes a ratio of an output voltage and an internally measured voltage, with the output voltage corresponding to a voltage drop across an inherent resistance within the IC or on the substrate.

Abstract: Systems and methods and computer program products are disclosed to determine the source data rate even in cases where the sink device is not directly coupled to the source device. A method includes, forming a logical channel from a source device to a sink device where the logical channel is configured to carry the source data stream and one or more rate parameters. The rate parameters relate a data rate of the source data stream to a data rate of the logical channel. Another method includes, detecting a logical channel in a received data stream where the logical channel includes the source data stream, recovering one or more rate parameters from the received data stream, determining a data rate of the logical channel, and determining the data rate of the source data stream based on the data rate of the logical channel and the one or more rate parameters.

Abstract: A disclosed integrated circuit logic cell includes a clock input operative to receive a clock input from a clock tree of the integrated circuit, and clocking circuitry, internal to the logic cell, operative to place a plurality of clock nodes, within the logic cell, in a logical off state in response to a predetermined logic state of the logic cell, thereby preventing the clock nodes from toggling during the predetermined logic state of the logic cell. The integrated circuit logic cell includes primary logic circuitry, internal to the logic cell, operatively coupled to the clocking circuitry which is operatively coupled to an input of the primary logic circuitry. The clocking circuitry provides clock outputs operatively coupled to the clock nodes which are within the primary logic circuitry, and is operative to control the clock outputs in response to the predetermined logic state.

Abstract: A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.

Abstract: A method for surviving a link down event in a two-way serial-connection link. The method includes sequentially numbering packets to be transmitted across the link, successfully transmitted packets being acknowledged and after the link down event. Only packets unacknowledged are retransmitted when a device coupled to the link attempts to survive the event, each unacknowledged packet being retransmitted in accordance with its number within the sequence.

Abstract: A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

Abstract: A method and system for producing a single view video signal based on a multiview video coding (MVC) signal stream. A MVC signal stream representing multiple spatially related views of a scene, including a base view and at least one dependent view, is decoded to provide multiple decoded video signals representing the spatially related views, with respective portions of the MVC signal stream representing one of multiple temporally adjacent video frames, and the MVC signal stream representing multiple sequences of spatially adjacent video frames. The decoded video signals are processed to provide a processed video signal representing one of the spatially related views using image information from more than one of the decoded video signals. As a result, more image data is used during processing, thereby improving the spatial and temporal image quality.

Abstract: A system and method for providing user control of the projection of two-dimensional (2D) image information within the three-dimensional (3D) display space of a 3D-capable display device. Advantageously, the system and method disclosed herein allow a user to view 3D video even when the source video includes 2D content, by allowing the user to adjust the z-axis position of the 2D content, thereby causing the 2D content to be projected at a user-specified image depth within 3D space. The user can adjust the z-axis position of the 2D content in real time while contemporaneously viewing the imagery, e.g., via a remote control, and such adjustment can be stored for later use when similar or other 2D content is being viewed.

Abstract: A multiplexed packetized data stream carrying real-time multimedia programs is received at a first hardware demultiplexer. Based on a user input, a video and timing portion of a program associated with the multiplexed packetized data stream can be stored for subsequent display. One type of subsequent display is time shifted display, where the stored portion of the program is played back while new portions of the program are being stored. During time shifted play back, a second hardware demultiplexer can be used, so that one demultiplexer stores new data and maintains a current clock value while the other decodes and displays the stored data.

Abstract: A method for deinterlacing video includes constructing a temporary frame of deinterlaced video based on a first (i.e., current) field of interlaced video, wherein the temporary frame includes pixels in lines of the temporary frame associated with the first field of interlaced video, placeholder pixels in identified areas of motion in lines of the frame associated with a missing field of interlaced video, and pixels from an opposite field of polarity of interlaced video in areas without motion. The method further includes replacing the placeholder pixels in the identified areas of motion with pixels interpolated using an edge direction interpolation scheme based on pixels in the first field of interlaced video, resulting in a reconstructed frame. In one example, a motion adaptive interpolator may construct the temporary frame, and an edge directional interpolator may generate the reconstructed/deinterlaced the frame.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: In one example an electronic device includes a housing that includes an A/C input or DC input, and at least one circuit substrate that includes electronic circuitry, such as graphics processing circuitry that receives power based on the A/C input or DC input. The electronic device also includes a divided multi- connector element differential bus connector that is coupled to the electronic circuitry. The divided multi-connector element differential bus connector includes a single housing that connects with the circuit substrate and the connector housing includes therein a divided electronic contact configuration comprised of a first group of electrical contacts divided from an adjacent second group of mirrored electrical contacts wherein each group of electrical connects includes a row of at least lower and upper contacts.

Abstract: A circuit monitors and resets a co-processor. The circuit includes a hang detector module for detecting a hang in co-processor. The circuit also includes a selective processor reset module for resetting the co-processor without resetting a processor in response to detecting a hang in the co-processor.