Abstract: A narrow band, tunable antenna uses a series of small inductors wired in series to produce different resonant frequencies from a single antenna across a wide frequency spectrum. Radio Frequency (RF) switches are positioned in parallel with the inductors and are capable of shunting a selected inductor out of the antenna circuit thereby changing the electrical length of the antenna and consequently, the resonant frequency. The RF switch control circuitry is isolated from the RF current in the antenna.

Abstract: An apparatus includes at least one general purpose register and at least one special purpose register and an execution unit that executes at least two instructions in parallel, to decode variable length codes, wherein each of the instructions share use of the at least one general purpose register and the at least one special purpose register. In one example, a processor stores variable length code information among a plurality of general purpose registers and generates decoded variable length code information by decoding the at least one variable length code. The processor also stores the decoded variable length code information among the plurality of general purpose registers.

Abstract: In one example an electronic device includes a housing that includes an A/C input or DC input, and at least one circuit substrate that includes electronic circuitry, such as graphics processing circuitry that receives power based on the A/C input or DC input. The electronic device also includes a divided multi-connector element differential bus connector that is coupled to the electronic circuitry. The divided multi-connector element differential bus connector includes a single housing that connects with the circuit substrate and the connector housing includes therein a divided electronic contact configuration comprised of a first group of electrical contacts divided from an adjacent second group of mirrored electrical contacts wherein each group of electrical connects includes a row of at least lower and upper contacts. In one example, the electronic device housing includes air flow passages, such as grills, adapted to provide air flow through the housing.

Abstract: In one aspect, there is provided a video decoder including a first write port to write uncompressed video data to a first buffer in a first format adapted based on an input required by the video decoder and to suppress writing to the first buffer. The video decoder also includes a second write port to write uncompressed video data to a second buffer in a second format adapted to provide the uncompressed video data for subsequent processing external to the video decoder.

Abstract: A method and apparatus provides for controlling movement of one or more graphical user interface (GUI) objects such as a cursor and/or a window. In one example, the method and apparatus applies a warp operation to the GUI object that uses display content information to determine where to move the cursor and/or window. The destination position of the GUI object is determined based on content identification information associated with display content such as name, serial number or label that identifies the display content. The display content may be any visible object to be displayed on the display screen, including but is not limited to, windows, taskbars, sidebars, docks, program launchers, icons, controls, and background (wallpaper). The warp operation may be an immediate relocation of the GUI object to the destination position without any user intervention during the relocation.

Abstract: Apparatus provides for providing multi-mode warping of graphical user interface (GUI) objects, such as but not limited to a pointing object (e.g., cursor) and a window. In one example, the apparatus includes logic operative to provide a user interface that allows a user to select different warping modes. In one example, a user may select a pointing object warping mode and/or a window warping mode. In the pointing object warping mode, the apparatus applies a warp operation to one or more pointing objects that uses display content information to determine where to move the pointing object. In the window warping mode, the apparatus applies a warp operation to one or more windows that also uses display content information to determine where to move the window. The destination position of the GUI object is determined based on content identification information associated with display content such as name, serial number or label that identifies the display content.

Abstract: An apparatus includes a display location sensor based mapping circuit. The display location sensor based mapping circuit maps multiple displays to collectively display a single large surface in response to sensed location information from at least one of the displays.

Abstract: A digital communications receiver includes an input configured to receive, via a communications channel, a received first signal representing a sequence of symbols, each symbol being encoded to be representative of a plurality of data bits. A processor adjusts a magnitude and filters the received signal. An equalizer applies a cyclic prefix restoration to the adjusted and filtered signal, producing a second signal, converts the second signal from time domain to frequency domain to produce a frequency domain signal, and determines a first quantity of values representing a first portion of the symbols by evaluating a relationship of channel values representing characteristics of the communications channel and a second quantity of values representing a portion of the frequency domain signal, the first quantity being smaller than the second quantity.

Abstract: A method and apparatus provides for the accommodation of display migration among a plurality of physical displays. In one example, the method and apparatus detects a display migration condition from at least a second physical display to a first physical display. The method and apparatus then controls compositing of a plurality of desktop surfaces so as enable access of each one of the plurality of desktop surfaces on the first physical display. The plurality of desktop surfaces include at least a desktop surface associated with the second physical display. The desktop surface is the content in a piece of memory in a frame buffer, which represents all the display content presented on the associated physical display. In one example, the plurality of desktop surfaces may be composited into at least one three-dimensional display object. The three-dimensional display object includes but is not limited to a revolving door object or other three-dimensional shape or object (e.g., a cube object).

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

Abstract: Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler.

Abstract: System and method for mapping audio and video streams from an audio/video (AV) source to respective ones of a plurality of AV sinks. In accordance with one or more embodiments, the audio and video playback and content protection capabilities of each one of the AV sinks are determined based on AV data received via a video channel interface from each one of the AV sinks. Also determined are the audio and video streams available from the AV source. Respective ones of the audio and video streams available from the AV source are mapped to each one of the AV sinks in accordance with their audio and video playback and content protection capabilities.

Abstract: A pulsed latch circuit with conditional shutoff prevents an input node, such as a node receiving data, of the pulsed latch circuit, from latching data based on a delayed input control signal, such as an internal clocking signal, and based on a feedback latch state transition detection signal indicating that a current state of input data is stored in the latch. As such, two control conditions are used to shut down the latch. In one example, a condition generator detects when the latch has captured data correctly and outputs a signal to disable the input node. In addition, a variable delay circuit is used to adjust the width of the allowable input signal to set a worst case shutoff time. If data is latched early, a feedback latch state transition detection signal causes the input node to be disabled. If data is not latched early, the maximum allowable latch time is set by the variable delay circuit.

Abstract: A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

Abstract: An integrated circuit package employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.

Abstract: A device for rapidly instituting an active mode of a digital-television enabled system, the system including a first, volatile memory configured to load and store software instructions, includes: an input configured to receive first digital audio and video information; a first output configured to convey second audio and information toward a display regarding the first audio and video information; at least one second output configured to convey commands to, and receive information from, the first memory; and a processor configured to perform functions in accordance with software instructions stored in first and second memories and to cause the first memory to load software instructions for provision to the processor such that first instructions for processing at least one of the first audio information and the first video information are loaded and stored by the first memory with a higher priority than second instructions for performing other functionality.

Abstract: Methods of rendering a view of a scene include steps that specify quality levels of anti-aliasing and texture filtering for predetermined regions of a display, or selected objects within the scene, or both. Methods of processing data for display include steps adapted to process portions of the image according to selected or predetermined anti-aliasing and texture filtering quality levels. Graphics processing equipment includes hardware or software adapted to perform non-uniform anti-aliasing of images according to specified criteria.

Abstract: The present invention provides a scheme for compressing the color components of image data, and in particular, data used in multi-sampled anti-aliasing applications. Adjacent pixels are grouped into rectangular tiles, with the sample colors stored in compressed formats accessible via an encoded pointer. In one embodiment, duplicate colors are stored once. Unlike prior compression schemes that rely on pixel to pixel correlation, the present invention takes advantages of the sample to sample correlation that exists within the pixels. A memory and graphics processor configuration incorporating the tile compression schemes is also provided. The configuration defines the tile sizes in main memory and cache memory. In one embodiment, graphics processor relies on a Tile Format Table (TFT) to process incoming tiles in compressed formats. The present invention reduces memory consumption and speeds up essential and oft-repeated operations in rendering.

Abstract: Methods and apparatus provide for indicating multi-power rail status of integrated circuits by taking into account a clock signal provided by, for example, core logic, in addition to considering voltage levels of multiple power rails. In one example, the apparatus includes multi-power rail status indicating logic that provides a multi-power rail status signal. The multi-power rail status signal is synchronized for assertion with a clock signal of the integrated circuit, such as the core logic of the integrated circuit, in response to an assertion of an asynchronous multi-power rail voltage stability signal. The asynchronous multi-power rail voltage stability signal indicates a state of a plurality of voltage signals from a plurality of power rails supplied to the integrated circuit.

Abstract: Methods and apparatus provide for voltage level shifting with concurrent synchronization. The apparatus includes level shifting logic that in response to a non-level shifted clock signal from a first voltage domain, provides level shifted concurrently synchronous differential data signals in a second voltage domain based on pre-level shifted differential data signals from the first voltage domain. The first voltage domain may be, for example, a core logic voltage domain in which core logic operates. The second voltage domain may be, for example, an input/output (I/O) voltage domain in which an I/O buffer operates. The voltage level of the level shifted concurrently synchronous differential data signals is shifted from the pre-level shifted differential data signals, and the timing of the level shifted concurrently synchronous differential data signals is concurrently referenced to the non-level shifted clock signal.