Abstract: A method and integrated circuit renders a shunt structure non-conductive during a power up event or noise event for and in addition, during an electrostatic discharge event, keeps the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a shunt structure, such as a transistor, is interposed between a power node and a ground node. Circuitry is operative during a power up event or noise event, to render the shunt structure non-conductive for a period of time during the power up event or during the noise event (when power is applied). Second circuit is operative, during an electrostatic discharge event, to keep the shunt structure conductive for a period of time to discharge electrostatic energy through the shunt structure. In one example, a plurality of resistor/capacitors (RC) circuits are utilized wherein the RC circuits have different time constants.

Abstract: A method and apparatus of processing image data comprises correlating received image data. Image statistics are computed based upon the correlated image and eccentricity is estimated based upon the computed image statistics. An entropy metric of the correlated received image data is determined. An interpretation based upon the image statistics, estimated eccentricity, and entropy metric is performed and a report including the content of the processed image data is generated.

Abstract: A multi-supply power supply circuit has a first power supply regulating circuit that produces a first power supply voltage; and a second power supply regulating circuit that receives the first power supply voltage from the first power supply regulating circuit as an enable input signal and is operative to produce a second and different power supply voltage. In one embodiment, the first power supply voltage may reach a steady state condition prior to the second power supply voltage reaching a steady state condition. In one example, the multi-supply power supply circuit includes a plurality of cascaded low drop out power supply regulating circuits.

Abstract: Methods and test receiver apparatus are provided for loopback testing of a unidirectional physical layer device. The disclosed methods and test receiver apparatus allow for the phase of a sampling clock implemented at the test receiver apparatus to be aligned with the phase of a test data signal.

Abstract: A display device that has multiple inputs for receiving video data and peripheral data from multiple computing devices, and an output for attaching a peripheral. The display is operable in one of two states, to provide both a video and peripheral signal paths between a selected one of the interconnected computing devices and the display's panel and attached peripherals. At any given time only one of the computing devices may utilize both the display and any attached peripherals. Exemplary embodiments may handle video and peripheral data streams received from a computing device over a single physical link.

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract: The present invention provides a scheme for compressing the color components of image data, and in particular, data used in multi-sampled anti-aliasing applications. Adjacent pixels are grouped into rectangular tiles, with the sample colors stored in compressed formats accessible via an encoded pointer. In one embodiment, duplicate colors are stored once. Unlike prior compression schemes that rely on pixel to pixel correlation, the present invention takes advantages of the sample to sample correlation that exists within the pixels. A memory and graphics processor configuration incorporating the tile compression schemes is also provided. The configuration defines the tile sizes in main memory and cache memory. In one embodiment, graphics processor relies on a Tile Format Table (TFT) to process incoming tiles in compressed formats. The present invention reduces memory consumption and speeds up essential and oft-repeated operations in rendering.

Abstract: A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host.

Abstract: A memory interface allows access to SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n (n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access.

Abstract: A configurable register method and structure included configuration logic to form a register value. A data bridge system, for connecting an interface of a computer system to a plurality of application-specific integrated circuits (ASIC), has a data bridge operatively coupled between the computer interface and the plurality of ASICs that employs the configurable registers. The data bridge has a read only memory for storing at least the initial values and mask values for each ASIC of the plurality of ASICs. The data bridge upon initialization forms base address registers and other configuration data that are queried by the computer system. When the ASICs are graphic processors, the initial values and the mask values stored in the read only memory define the base address registers in the data bridge as a function of the configuration requirements of the graphic processors. The base address registers are thus programmable as a function of the initial values and mask values in the read only memory.

Abstract: Provided herein is a method for synchronizing audio and video clock signals in a system. The method includes comparing, within a comparison module, a system video signal with the determined mathematical relationship to produce an adjustment signal. A system video reference signal is updated with the adjustment signal to produce an updated intermediate signal.

Abstract: An apparatus and method utilizes system memory as backing stores so that local graphics memory may be oversubscribed. Surfaces may be paged in and out of system memory based on the amount of usage of the surfaces. The apparatus and method also prioritizes surfaces among different tiers of local memory (e.g. frame buffer), non-local memory (e.g. page locked system memory), and system memory backing stores (e.g. pageable system memory) locations based on predefined criteria and runtime statistics relating to the surfaces. As such, local memory may be, for example, expanded without extra memory costs such as adding a frame buffer memory to allow graphics applications to effectively use more memory and run faster.

Abstract: A narrow band, tunable antenna uses a series of small inductors wired in series to produce different resonant frequencies from a single antenna across a wide frequency spectrum. Radio Frequency (RF) switches are positioned in parallel with the inductors and are capable of shunting a selected inductor out of the antenna circuit thereby changing the electrical length of the antenna and consequently, the resonant frequency. The RF switch control circuitry is isolated from the RF current in the antenna.

Abstract: A method for the display of compressed supertile images is disclosed. In one embodiment, a method for displaying an image frame from a plurality of compressed supertile frames includes: reading the compressed supertile frames; expanding the compressed supertile frames; and combining the expanded supertile frames to generate the image frame. The expanding can include generating an expanded supertile frame corresponding to each of the compressed supertile frames by inserting blank pixels for tiles in the expanded supertile frame that are not in the corresponding compressed supertile frame. Corresponding system and computer program products are also disclosed.

Abstract: A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.

Abstract: An apparatus includes a plurality of image processing circuits. Each image processing circuit generates an image frame corresponding to a single large surface. The first image processing circuit provides a portion of the generated image frame for a first display or plurality of displays and provides a remaining portion of the image frame to the remaining image processing circuits. The next image processing circuits provides the remaining portion of the image frame for the next plurality of displays.

Abstract: Various apparatus and methods of addressing crosstalk in a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first layer of a circuit board with a first signal trace and forming a second layer of the circuit board with a second signal trace. A first guard trace is formed on the first layer and offset laterally from the first signal trace but at least partially overlapping the second signal trace and a second guard trace is formed on the second layer and offset laterally from the second signal trace but at least partially overlapping the first signal trace.

Abstract: The subject matter disclosed herein provides methods and apparatus, including computer program products, for providing intermediate compression or decompression for use with a video decoder and a memory. In one aspect, there is provided a method including receiving information to enable compression of a macroblock. At an intermediate section coupled to a video decoder and a memory, a macroblock may be compressed. The compression of the macroblock may be based on the received information. The compressed macroblock may be provided to memory. Related apparatus, systems, methods, and articles are also described.

Abstract: In an embodiment, a method in a device of controlling a display is provided. The method includes transmitting a heartbeat signal in a self-refresh state. The heartbeat signal is configured to be used by a display to remain in sync with the device while the device is in the self-refresh state.

Abstract: A method and apparatus provides for providing an indication of a static frame. In one example, the method and apparatus notifies the arrival of a static frame by changing a vertical blanking interval for the static frame. For example, the method and apparatus may determine that a display frame is a static frame if no graphic processing activity and/or lack of update to the frame buffer have been detected for a period of time. In response to a display frame being a static frame, the method and apparatus may change the vertical blanking interval that is immediately before the static frame by increasing the number of blanking scan lines in the vertical blanking interval. The changed vertical blanking interval may be transmitted with the static frame as an indicator of the arrival of a static frame, so that the apparatus may enter a self-refresh mode to repeatedly display the static frame.