Patents Assigned to ATI Technologies
  • Patent number: 11445214
    Abstract: Techniques are provided for determining variance of a pixel block in a frame of video based on variance of pixel blocks in a reference frame of the video, instead of directly, for example, by calculating variance based on pixel values of the pixel block. The techniques include identifying a motion vector for a pixel block in a current frame, the motion vector pointing to a pixel block in a reference frame. The techniques also include determining the cost associated with the motion vector and comparing the cost to first and second thresholds. The techniques include determining the variance for the pixel block of the current frame based on the comparison of the cost to the first and second threshold and based on the variance of the pixel block of the reference frame.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: September 13, 2022
    Assignee: ATI Technologies ULC
    Inventor: Mehdi Saeedi
  • Publication number: 20220277508
    Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.
    Type: Application
    Filed: May 16, 2022
    Publication date: September 1, 2022
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
  • Patent number: 11424761
    Abstract: An electronic device includes a decoding subsystem having a symbol decoder and a second symbol resolver with a plurality of local symbol decoders and a symbol selector. The symbol decoder outputs a first symbol decoded from an initial code for which a symbol is available in a block of the compressed data. The second symbol resolver decodes, in each local symbol decoder, substantially in parallel with decoding the first symbol in the symbol decoder, a respective symbol from a subsequent initial code for which a symbol is available in a respective sub-block of the block of the compressed data. The second symbol resolver outputs, by the symbol selector, as a second symbol, one of the respective symbols from the local symbol decoders selected by the symbol selector based on the initial code.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: August 23, 2022
    Assignee: ATI Technologies ULC
    Inventor: Vinay Patel
  • Patent number: 11379941
    Abstract: Improvements in the graphics processing pipeline are disclosed. More specifically, a new primitive shader stage performs tasks of the vertex shader stage or a domain shader stage if tessellation is enabled, a geometry shader if enabled, and a fixed function primitive assembler. The primitive shader stage is compiled by a driver from user-provided vertex or domain shader code, geometry shader code, and from code that performs functions of the primitive assembler. Moving tasks of the fixed function primitive assembler to a primitive shader that executes in programmable hardware provides many benefits, such as removal of a fixed function crossbar, removal of dedicated parameter and position buffers that are unusable in general compute mode, and other benefits.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: July 5, 2022
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Todd Martin, Mangesh P. Nijasure, Randy W. Ramsey, Michael Mantor, Laurent Lefebvre
  • Publication number: 20220210429
    Abstract: Methods and devices are provided for encoding video. By using co-sited gradient and variance values to detect text and line in frames of the video. A processor is configured to receive a plurality of frames of video, determine, for a portion of a frame, a variance of the portion of the frame and a gradient of the portion of the frame and encode, using one of a plurality of different encoding qualities, the portion of the frame based on the gradient and the variance of the portion of the frame. Encoding is performed at both the sub-frame level and frame level. The portion of the frame is classified into one of a plurality of categories based on the gradient and variance and encoded based on the category.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Applicant: ATI Technologies ULC
    Inventors: Mehdi Saeedi, Sai Harshita Tupili, Yang Liu, Mingkai Shao, Gabor Sines
  • Publication number: 20220207783
    Abstract: Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to receive frames of image data comprising sub-frame portions, schedule a first sub-frame portion of a first frame to be processed by a first layer of the convolutional neural network when the first sub-frame portion is available for processing, process the first sub-frame portion by the first layer and continue the processing of the first sub-frame portion by the first layer when it is determined that there is sufficient image data available for the first layer to continue processing of the first sub-frame portion. Processing on a sub-frame portion basis continues for subsequent layers such that processing by a layer can begin as soon as sufficient data is available for the layer.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Tung Chuen Kwong, David Porpino Sobreira Marques, King Chiu Tam, Shilpa Rajagopalan, Benjamin Koon Pan Chan, Vickie Youmin Wu
  • Publication number: 20220210432
    Abstract: A processing apparatus and video encoding method are provided which include receiving a portion of a video sequence and determining complexities for blocks of pixels of the portion of the video sequence. Quantization parameter values for corresponding blocks of pixels are selected based on complexities of the corresponding blocks and visually perceived coding artifacts of the corresponding blocks produced by the quantization parameter values. The blocks of pixels are encoded, using the selected quantization parameter values. The blocks of pixels are decoded and the portion of the video sequence is provided for display.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicant: ATI Technologies ULC
    Inventors: Feng Pan, Crystal Yeong-Pian Sau, Wei Gao, Mingkai Shao, Dong Liu, Ihab M. A. Amer, Gabor Sines
  • Publication number: 20220207644
    Abstract: Data processing methods and devices are provided. A processing device comprises memory and a processor. The memory, which comprises a cache, is configured to store portions of data. The processor is configured to issue a store instruction to store one of the portions of data, provide identifying information associated with the one portion of data, compress the one portion of data; and store the compressed one portion of data across multiple lines of the cache using the identifying information. In an example, the one portion of data is a block of pixels and pixels and the processor is configured to request pixel data for a pixel of a compressed block of pixels, send additional requests for data for other pixels determined to belong to the compressed pixel block and provide an indication that the requests are for pixel data belonging to the compressed block of pixels.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Sergey Korobkov, Jimshed B. Mirza, Anthony Hung-Cheong Chan
  • Publication number: 20220206831
    Abstract: A method and system for managing applications on a virtual machine includes creating a plurality of virtual machines on a computer system. Each virtual machine is isolated from one another. Resources are allocated to each virtual machine based upon a resource requirement of an application executing on each virtual machine.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 30, 2022
    Applicant: ATI Technologies ULC
    Inventors: Vignesh Chander, Rohit S. Khaire
  • Patent number: 11368692
    Abstract: Systems, apparatuses, and methods for generating a model for determining a quantization strength to use when encoding video frames are disclosed. A pre-encoder performs multiple encoding passes using different quantization strengths on a portion or the entirety of one or more pre-processed video frames. The pre-encoder captures the bit-size of the encoded output for each of the multiple encoding passes. Then, based on the multiple encoding passes, the pre-encoder generates a model for mapping bit-size to quantization strength for encoding video frames or portion(s) thereof. When the encoder begins the final encoding pass for one or more given video frames or any portion(s) thereof, the encoder uses the model to map a preferred bit-size to a given quantization strength. The encoder uses the given quantization strength when encoding the given video frame(s) or frame portion(s) to meet a specified bit-rate for the encoded bitstream.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 21, 2022
    Assignee: ATI Technologies ULC
    Inventors: Jinbo Qiu, Yang Liu, Ihab Amer, Lei Zhang, Edward A. Harold, Zhiqi Hao, Jiao Wang, Gabor Sines, Haibo Liu, Boris Ivanovic
  • Publication number: 20220188139
    Abstract: A technique for managing access to a micro engine, the method comprising: determining that a virtual function “VF”) is to be given access to direct communication with a micro engine; in response to the determining, configuring the micro engine to accept direct communication from the VF; monitoring for unpermitted communication; and after a time period has expired, configuring the micro engine to no longer accept direct communication from the VF.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 16, 2022
    Applicant: ATI Technologies ULC
    Inventors: Yinan Jiang, Kamraan Nasim, Dezhi Ming, Ahmed M. Abdelkhalek, Dmytro Chenchykov, Andy Sung
  • Publication number: 20220188180
    Abstract: A method and system for recording and logging errors in a computer system includes reading first error handling information with respect to a transaction. The first error handling information is stored in a first component, and based upon a condition of the storage in the first component, an oldest error information is evicted from the first component.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 16, 2022
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Philip Ng, Buheng Xu
  • Publication number: 20220191070
    Abstract: A receiver circuit includes an analog front end and a non-linear equalizer. The analog front end including a super source follower (SSF) amplifier having a first input terminal adapted to couple to a transmission line to receive an input signal referenced to a first voltage level, a second input adapted to receive a reference voltage, and first and second output terminals adapted to provide an amplified signal referenced to a second voltage level. The non-linear equalizer coupled to receive an output signal of the analog front end and compensate for inter-symbol interference at a data rate of at least 14 Gbps. The SSF amplifier includes transistors having relative sizes selected to provide a frequency response of the SSF amplifier with a peak at a frequency approximately ? of the data rate.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 16, 2022
    Applicant: ATI Technologies ULC
    Inventor: Saman Asgaran
  • Patent number: 11361399
    Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 14, 2022
    Assignee: ATI Technologies ULC
    Inventors: Laurent Lefebvre, Andrew Gruber, Stephen Morein
  • Patent number: 11335052
    Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: May 17, 2022
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael Mantor, Laurent Lefebvre, Mark Fowler, Timothy Kelley, Mikko Alho, Mika Tuomi, Kiia Kallio, Patrick Klas Rudolf Buss, Jari Antero Komppa, Kaj Tuomi
  • Publication number: 20220147366
    Abstract: In a system with a master processor and slave processors, sync points are used in boot instructions. While executing the boot instructions, the slave processor determines whether the sync point is enabled. In response to determining the sync point is enabled, the slave processor pauses execution of the boot instructions, waits for commands from the master processor, receives commands from the master processor, executes the received commands until a release command is received, and then continues to execute boot instructions. In response to determining the sync point is not enabled, the slave processor continues to execute boot instructions.
    Type: Application
    Filed: November 12, 2020
    Publication date: May 12, 2022
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Wentao Xu, Randall Alexander Brown, Vaibhav Amarayya Hiremath, Shijie Che, Kamraan Nasim
  • Patent number: 11328382
    Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: May 10, 2022
    Assignee: ATI Technologies ULC
    Inventors: Stephen L. Morein, Laurent Lefebvre, Andrew E. Gruber, Andi Skende
  • Publication number: 20220141472
    Abstract: An encoding method is provided which includes receiving a plurality of images, obtaining values of elements in a portion of the images, sorting the elements according to different values of the elements, sorting the elements according to a number of occurrences of the different values and encoding the elements using a subset of the different values having corresponding numbers of occurrences that are higher than corresponding numbers of occurrences of other values. Examples also include a processing device and method for use with palette mode encoding in which the elements are a portion of pixels in images and the values are color values of the portion of pixels in the images.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Shu-Hsien Wu, Crystal Yeong-Pian Sau, Yang Liu, Wei Gao, Feng Pan, Ihab M. A. Amer, Ying Luo, Edward A. Harold, Gabor Sines, Ehsan Mirhadi
  • Patent number: 11315883
    Abstract: An apparatus includes a substrate including an identification code on a first side of the substrate and near a perimeter of the substrate. The apparatus includes a stiffener structure attached to the first side of the substrate. The stiffener structure has a cutout in an outer perimeter of the stiffener structure. The stiffener structure is oriented with respect to the substrate to cause the cutout to expose the identification code. The cutout may have a first dimension and a second dimension orthogonal to the first dimension. The first dimension may exceed a corresponding first dimension of the identification code and the second dimension may exceed a corresponding second dimension of the identification code, thereby forming a void region between the identification code and edges of the stiffener structure.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: April 26, 2022
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Suming Hu, Roden Topacio, Farshad Ghahghahi, Jianguo Li, Andrew Kwan Wai Leung
  • Patent number: 11310496
    Abstract: A technique for determining a quality value for a subject block of encoded video is provided. Contributing blocks, of the same frame and/or different frames of the subject block, are determined by identifying blocks likely to be a part of the same moving object or background as the subject block. A spatial and/or temporal filter is then applied to the quality values of the contributing blocks and an initial quality value of the subject block. With a spatial filter, quality values for contributing blocks from the same frame are combined and used to modify the quality value of the subject block. With a spatial filter, a temporal characteristic quality value for contributing blocks of one or more other frames (such as the immediately previous frame) is determined and then combined with a quality value representative of the subject block.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 19, 2022
    Assignee: ATI Technologies ULC
    Inventors: Mehdi Saeedi, Boris Ivanovic