Abstract: A method and apparatus for reducing latency in a virtual reality system including a plurality of devices comprises capturing and transmitting, by a first device, a first batch of data to a second device. The second device renders and encodes a second data based upon the first batch of data, and transmits the first encoded image to the first device. Based upon a determination of a likelihood of collision between a transmission of a second batch of data from the first device and the transmission of the second data, the first device adjusts a frequency of capturing and transmitting the second batch of data.

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Abstract: A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit also includes a renamer that renames architectural registers used by the load operation and allocates physical register numbers to the load operation in response to receiving the load operation from the NSQ. The floating point unit further includes a set of pickable scheduler queues that receive the load operation from the renamer and store the load operation prior to execution. A physical register file is implemented in the floating point unit and a free list is used to store physical register numbers of entries in the physical register file that are available for allocation.

Abstract: Systems, apparatuses, and methods for reducing chiplet interrupt latency are disclosed. A system includes one or more processing nodes, one or more memory devices, a communication fabric coupled to the processing unit(s) and memory device(s) via link interfaces, and a power management unit. The power management unit manages the power states of the various components and the link interfaces of the system. If the power management unit detects a request to wake up a given component, and the link interface to the given component is powered down, then the power management unit sends an out-of-band signal to wake up the given component in parallel with powering up the link interface. Also, when multiple link interfaces need to be powered up, the power management unit powers up the multiple link interfaces in an order which complies with voltage regulator load-step requirements while minimizing the latency of pending operations.

Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.

Abstract: Techniques for generating a task graph for workload scheduling based on a task graph specification program are provided. The techniques include executing control flow instructions of the task graph specification program to traverse the task graph specification program; generating pass nodes of the task graph based on pass instructions of the task graph specification program; generating resource nodes and directed edges based on resource declarations of the task graph specification program; and outputting the task graph specification program to a command scheduler for scheduling.

Abstract: Systems, apparatuses, and methods for implementing a broadcast read response protocol are disclosed. A computing system includes a plurality of processing engines coupled to a memory subsystem. A first processing engine executes a read and broadcast response command, wherein the read and broadcast response command targets first data at a first address in the memory subsystem. One or more other processing engines execute a wait command to wait to receive the first data requested by the first processing engine. After receiving the first data from the memory subsystem, the plurality of processing engines process the first data as part of completing a first operation. In one implementation, the first operation is implementing a given layer of a machine learning model. In one implementation, the given layer is a convolutional layer of a neural network.

Abstract: A processing system detects excessive requests sent on behalf of a virtual machine executing at the processing system within a predetermined period of time and denies subsequent requests sent on behalf of that virtual machine until after the predetermined period of time has elapsed in order to grant access to resources of the processing system for servicing requests from other virtual machines and to prevent a virtual machine that has been compromised by an attack from overwhelming the processing system with malicious requests. The processing system sets a threshold number of event requests for each type of event request that can occur within a predetermined period of time. If the number of event requests of a certain type exceeds the threshold for that event type, the processing system ignores subsequent event requests of that type until the predetermined period of time has expired.

Abstract: An apparatus and methods for controlling power consumption in video encoding obtain, before motion estimation is performed on an image frame to be encoded, information regarding an amount of the image frame to be encoded that is static with respect to a previously encoded image frame. The apparatus and methods adjust power consumption of the video encoder based on the obtained information regarding the amount of the image frame to be encoded that is static.

Abstract: A system and method for dynamically changing encode quality at a block level based on runtime pre-encoding analysis of content in a video stream. A video encoder continuously analyzes the content during runtime, and collects statistics and/or characteristics of the content before encoding it. This classifies the block among pre-defined categories of content, where every category has its own compression parameters.

Abstract: A graphics processing unit (GPU) adjusts a frequency of clock based on identifying a program thread executing at the processing unit, wherein the program thread is detected based on a workload to be executed. By adjusting the clock frequency based on the identified program thread, the processing unit adapts to different processing demands of different program threads. Further, by identifying the program thread based on workload, the processing unit adapts the clock frequency based on processing demands, thereby conserving processing resources.

Abstract: Described herein are techniques for removing control of a display from an operating system. The disclosed techniques decouple operation of the physical display device from control of the operating system so that the display device may be powered down while not needed during streaming. The device driver for the graphics card, into which a display device cable is plugged, simulates operation of the display but allows the display to be powered down. Simulating the display involves properly responding to queries or commands from the operating system, and generating the signals that would be expected from the display device by the operating system. While simulated in this manner, whether the display device is actually powered down does not matter to the operation of an application being streamed, because the operating system still “believes” the display device is powered on. Thus application streaming is not interrupted by powering down the display device.

Abstract: A technique for varying firmware for different virtual functions in a virtualized device is provided. The virtualized device includes a hardware accelerator and a microcontroller that executes firmware. The virtualized device is virtualized in that the virtualized device performs work for different virtual functions (with different virtual functions associated with different virtual machines), each function getting a “time-slice” during which work is performed for that function. To vary the firmware, each time the virtualized device switches from performing work for a current virtual function to work for a subsequent virtual function, one or more microcontrollers of the virtualized device examines memory storing addresses for firmware for the subsequent virtual function and begins executing the firmware for that subsequent virtual function. The addresses for the firmware are provided by a corresponding virtual machine at configuration time.

Abstract: Techniques are provided herein for processing video data. The techniques include generating predicted macroblock coding modes for a set of macroblocks of a frame, assigning quantization parameters to the macroblocks based on the predicted macroblock coding modes, and encoding the set of macroblocks based on the quantization parameters.

Abstract: A processing system identifies a subset of pages of memory allocated to a source guest virtual machine (VM) running at a first graphics processing unit (GPU) that were modified by the source guest VM and transferring only the subset to a destination guest VM running at a second GPU when performing a live migration from the source guest VM to the destination guest VM. The first GPU maintains a page table of system memory addresses or frame buffer addresses allocated to and accessed by the source guest VM during a session, including an indication of whether the data was modified. Based on the page table information, the processing system identifies and transfers only the modified pages from the source guest VM to the destination guest VM, thereby reducing the time and bandwidth used for migration.

Abstract: A texture decompression method is described. The method comprises receiving a compressed texture block, determining a partition of pixels used for the compressed texture block, wherein the partition includes one or more disjoint subsets into which data in the compressed texture block is to be unpacked, unpacking data for each subset based on the determined partition, and decompressing each of the one or more disjoint subsets to form an approximation of an original texture block.

Abstract: The present disclosure is directed a system and method for exploiting camera and depth information associated with rendered video frames, such as those rendered by a server operating as part of a cloud gaming service, to more efficiently encode the rendered video frames for transmission over a network. The method and system of the present disclosure can be used in a server operating in a cloud gaming service to improve, for example, the amount of latency, downstream bandwidth, and/or computational processing power associated with playing a video game over its service. The method and system of the present disclosure can be further used in other applications where camera and depth information of a rendered or captured video frame is available.

Abstract: Systems, apparatuses, and methods for reducing latency when consuming an encoded video bitstream in real-time are disclosed. A video encoder encodes a video bitstream and writes chunks of the encoded bitstream to a bitstream buffer. Prior to the encoder completing the encoding of an entire frame, or an entire slice of a frame, a consumer module consumes encoded chunks of the bitstream. In one implementation, to enable pipelining of the consumption with the encoding, the encoder updates a buffer write pointer with an indication of the amount of data that has been written to the bitstream buffer. The consumer module retrieves encoded data from the bitstream buffer up to the location indicated by the buffer write pointer. In this way, the consumer module is able to access and consume encoded video data prior to the encoder finishing encoding an entire frame or an entire slice of the frame.

Abstract: Methods, devices, and systems for virtual address translation. A memory management unit (MMU) receives a request to translate a virtual memory address to a physical memory address and searching a translation lookaside buffer (TLB) for a translation to the physical memory address based on the virtual memory address. If the translation is not found in the TLB, the MMU searches an external memory translation lookaside buffer (EMTLB) for the physical memory address and performs a page table walk, using a page table walker (PTW), to retrieve the translation. If the translation is found in the EMTLB, the MMU aborts the page table walk and returns the physical memory address. If the translation is not found in the TLB and not found in the EMTLB, the MMU returns the physical memory address based on the page table walk.

Abstract: An interconnect controller for a data processing platform includes a data link layer controller for selectively receiving data packets from and sending data packets to a higher protocol layer, and a physical layer controller coupled to the data link layer controller and adapted to be coupled to a communication link. The physical layer controller operates according to a predetermined protocol selectively at one of a plurality of enhanced speeds that are not specified by any published standard and are separated from each other by the same predetermined amount. In response to performing a link initialization, the interconnect controller performs at least one setup operation to select a speed, and subsequently operates the communication link using a selected speed.